1/* 2 * Common routines for Tundra Semiconductor TSI108 host bridge. 3 * 4 * 2004-2005 (c) Tundra Semiconductor Corp. 5 * Author: Alex Bounine (alexandreb@tundra.com) 6 * Author: Roy Zang (tie-fei.zang@freescale.com) 7 * Add pci interrupt router host 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the Free 11 * Software Foundation; either version 2 of the License, or (at your option) 12 * any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program; if not, write to the Free Software Foundation, Inc., 59 21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 */ 23 24#include <linux/kernel.h> 25#include <linux/init.h> 26#include <linux/pci.h> 27#include <linux/slab.h> 28#include <linux/irq.h> 29#include <linux/interrupt.h> 30 31#include <asm/byteorder.h> 32#include <asm/io.h> 33#include <asm/irq.h> 34#include <asm/uaccess.h> 35#include <asm/machdep.h> 36#include <asm/pci-bridge.h> 37#include <asm/tsi108.h> 38#include <asm/tsi108_pci.h> 39#include <asm/tsi108_irq.h> 40#include <asm/prom.h> 41 42#undef DEBUG 43#ifdef DEBUG 44#define DBG(x...) printk(x) 45#else 46#define DBG(x...) 47#endif 48 49#define tsi_mk_config_addr(bus, devfunc, offset) \ 50 ((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base) 51 52u32 tsi108_pci_cfg_base; 53static u32 tsi108_pci_cfg_phys; 54u32 tsi108_csr_vir_base; 55static struct device_node *pci_irq_node; 56static struct irq_host *pci_irq_host; 57 58extern u32 get_vir_csrbase(void); 59extern u32 tsi108_read_reg(u32 reg_offset); 60extern void tsi108_write_reg(u32 reg_offset, u32 val); 61 62int 63tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc, 64 int offset, int len, u32 val) 65{ 66 volatile unsigned char *cfg_addr; 67 68 if (ppc_md.pci_exclude_device) 69 if (ppc_md.pci_exclude_device(bus->number, devfunc)) 70 return PCIBIOS_DEVICE_NOT_FOUND; 71 72 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number, 73 devfunc, offset) | 74 (offset & 0x03)); 75 76#ifdef DEBUG 77 printk("PCI CFG write : "); 78 printk("%d:0x%x:0x%x ", bus->number, devfunc, offset); 79 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr); 80 printk("data = 0x%08x\n", val); 81#endif 82 83 switch (len) { 84 case 1: 85 out_8((u8 *) cfg_addr, val); 86 break; 87 case 2: 88 out_le16((u16 *) cfg_addr, val); 89 break; 90 default: 91 out_le32((u32 *) cfg_addr, val); 92 break; 93 } 94 95 return PCIBIOS_SUCCESSFUL; 96} 97 98void tsi108_clear_pci_error(u32 pci_cfg_base) 99{ 100 u32 err_stat, err_addr, pci_stat; 101 102 /* 103 * Quietly clear PB and PCI error flags set as result 104 * of PCI/X configuration read requests. 105 */ 106 107 /* Read PB Error Log Registers */ 108 109 err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS); 110 err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR); 111 112 if (err_stat & TSI108_PB_ERRCS_ES) { 113 /* Clear error flag */ 114 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS, 115 TSI108_PB_ERRCS_ES); 116 117 /* Clear read error reported in PB_ISR */ 118 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR, 119 TSI108_PB_ISR_PBS_RD_ERR); 120 121 /* Clear PCI/X bus cfg errors if applicable */ 122 if ((err_addr & 0xFF000000) == pci_cfg_base) { 123 pci_stat = 124 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR); 125 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR, 126 pci_stat); 127 } 128 } 129 130 return; 131} 132 133#define __tsi108_read_pci_config(x, addr, op) \ 134 __asm__ __volatile__( \ 135 " "op" %0,0,%1\n" \ 136 "1: eieio\n" \ 137 "2:\n" \ 138 ".section .fixup,\"ax\"\n" \ 139 "3: li %0,-1\n" \ 140 " b 2b\n" \ 141 ".section __ex_table,\"a\"\n" \ 142 " .align 2\n" \ 143 " .long 1b,3b\n" \ 144 ".text" \ 145 : "=r"(x) : "r"(addr)) 146 147int 148tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 149 int len, u32 * val) 150{ 151 volatile unsigned char *cfg_addr; 152 u32 temp; 153 154 if (ppc_md.pci_exclude_device) 155 if (ppc_md.pci_exclude_device(bus->number, devfn)) 156 return PCIBIOS_DEVICE_NOT_FOUND; 157 158 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number, 159 devfn, 160 offset) | (offset & 161 0x03)); 162 163 switch (len) { 164 case 1: 165 __tsi108_read_pci_config(temp, cfg_addr, "lbzx"); 166 break; 167 case 2: 168 __tsi108_read_pci_config(temp, cfg_addr, "lhbrx"); 169 break; 170 default: 171 __tsi108_read_pci_config(temp, cfg_addr, "lwbrx"); 172 break; 173 } 174 175 *val = temp; 176 177#ifdef DEBUG 178 if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) { 179 printk("PCI CFG read : "); 180 printk("%d:0x%x:0x%x ", bus->number, devfn, offset); 181 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr); 182 printk("data = 0x%x\n", *val); 183 } 184#endif 185 return PCIBIOS_SUCCESSFUL; 186} 187 188void tsi108_clear_pci_cfg_error(void) 189{ 190 tsi108_clear_pci_error(tsi108_pci_cfg_phys); 191} 192 193static struct pci_ops tsi108_direct_pci_ops = { 194 tsi108_direct_read_config, 195 tsi108_direct_write_config 196}; 197 198int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary) 199{ 200 int len; 201 struct pci_controller *hose; 202 struct resource rsrc; 203 const int *bus_range; 204 int has_address = 0; 205 206 /* PCI Config mapping */ 207 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE); 208 tsi108_pci_cfg_phys = cfg_phys; 209 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__, 210 tsi108_pci_cfg_base); 211 212 /* Fetch host bridge registers address */ 213 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 214 215 /* Get bus range if any */ 216 bus_range = of_get_property(dev, "bus-range", &len); 217 if (bus_range == NULL || len < 2 * sizeof(int)) { 218 printk(KERN_WARNING "Can't get bus-range for %s, assume" 219 " bus 0\n", dev->full_name); 220 } 221 222 hose = pcibios_alloc_controller(); 223 224 if (!hose) { 225 printk("PCI Host bridge init failed\n"); 226 return -ENOMEM; 227 } 228 hose->arch_data = dev; 229 hose->set_cfg_type = 1; 230 231 hose->first_busno = bus_range ? bus_range[0] : 0; 232 hose->last_busno = bus_range ? bus_range[1] : 0xff; 233 234 (hose)->ops = &tsi108_direct_pci_ops; 235 236 printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. " 237 "Firmware bus number: %d->%d\n", 238 rsrc.start, hose->first_busno, hose->last_busno); 239 240 /* Interpret the "ranges" property */ 241 /* This also maps the I/O region and sets isa_io/mem_base */ 242 pci_process_bridge_OF_ranges(hose, dev, primary); 243 return 0; 244} 245 246/* 247 * Low level utility functions 248 */ 249 250static void tsi108_pci_int_mask(u_int irq) 251{ 252 u_int irp_cfg; 253 int int_line = (irq - IRQ_PCI_INTAD_BASE); 254 255 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 256 mb(); 257 irp_cfg |= (1 << int_line); /* INTx_DIR = output */ 258 irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */ 259 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg); 260 mb(); 261 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 262} 263 264static void tsi108_pci_int_unmask(u_int irq) 265{ 266 u_int irp_cfg; 267 int int_line = (irq - IRQ_PCI_INTAD_BASE); 268 269 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 270 mb(); 271 irp_cfg &= ~(1 << int_line); 272 irp_cfg |= (3 << (8 + (int_line * 2))); 273 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg); 274 mb(); 275} 276 277static void init_pci_source(void) 278{ 279 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, 280 0x0000ff00); 281 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, 282 TSI108_PCI_IRP_ENABLE_P_INT); 283 mb(); 284} 285 286static inline unsigned int get_pci_source(void) 287{ 288 u_int temp = 0; 289 int irq = -1; 290 int i; 291 u_int pci_irp_stat; 292 static int mask = 0; 293 294 /* Read PCI/X block interrupt status register */ 295 pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT); 296 mb(); 297 298 if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) { 299 /* Process Interrupt from PCI bus INTA# - INTD# lines */ 300 temp = 301 tsi108_read_reg(TSI108_PCI_OFFSET + 302 TSI108_PCI_IRP_INTAD) & 0xf; 303 mb(); 304 for (i = 0; i < 4; i++, mask++) { 305 if (temp & (1 << mask % 4)) { 306 irq = IRQ_PCI_INTA + mask % 4; 307 mask++; 308 break; 309 } 310 } 311 312 /* Disable interrupts from PCI block */ 313 temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); 314 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, 315 temp & ~TSI108_PCI_IRP_ENABLE_P_INT); 316 mb(); 317 (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); 318 mb(); 319 } 320#ifdef DEBUG 321 else { 322 printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n"); 323 pci_irp_stat = 324 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT); 325 temp = 326 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD); 327 mb(); 328 printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp); 329 temp = 330 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL); 331 mb(); 332 printk("cfg_ctl=0x%08x ", temp); 333 temp = 334 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE); 335 mb(); 336 printk("irp_enable=0x%08x\n", temp); 337 } 338#endif /* end of DEBUG */ 339 340 return irq; 341} 342 343 344/* 345 * Linux descriptor level callbacks 346 */ 347 348static void tsi108_pci_irq_enable(u_int irq) 349{ 350 tsi108_pci_int_unmask(irq); 351} 352 353static void tsi108_pci_irq_disable(u_int irq) 354{ 355 tsi108_pci_int_mask(irq); 356} 357 358static void tsi108_pci_irq_ack(u_int irq) 359{ 360 tsi108_pci_int_mask(irq); 361} 362 363static void tsi108_pci_irq_end(u_int irq) 364{ 365 tsi108_pci_int_unmask(irq); 366 367 /* Enable interrupts from PCI block */ 368 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, 369 tsi108_read_reg(TSI108_PCI_OFFSET + 370 TSI108_PCI_IRP_ENABLE) | 371 TSI108_PCI_IRP_ENABLE_P_INT); 372 mb(); 373} 374 375/* 376 * Interrupt controller descriptor for cascaded PCI interrupt controller. 377 */ 378 379static struct irq_chip tsi108_pci_irq = { 380 .typename = "tsi108_PCI_int", 381 .mask = tsi108_pci_irq_disable, 382 .ack = tsi108_pci_irq_ack, 383 .end = tsi108_pci_irq_end, 384 .unmask = tsi108_pci_irq_enable, 385}; 386 387static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct, 388 u32 *intspec, unsigned int intsize, 389 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 390{ 391 *out_hwirq = intspec[0]; 392 *out_flags = IRQ_TYPE_LEVEL_HIGH; 393 return 0; 394} 395 396static int pci_irq_host_map(struct irq_host *h, unsigned int virq, 397 irq_hw_number_t hw) 398{ unsigned int irq; 399 DBG("%s(%d, 0x%lx)\n", __FUNCTION__, virq, hw); 400 if ((virq >= 1) && (virq <= 4)){ 401 irq = virq + IRQ_PCI_INTAD_BASE - 1; 402 get_irq_desc(irq)->status |= IRQ_LEVEL; 403 set_irq_chip(irq, &tsi108_pci_irq); 404 } 405 return 0; 406} 407 408static int pci_irq_host_match(struct irq_host *h, struct device_node *node) 409{ 410 return pci_irq_node == node; 411} 412 413static struct irq_host_ops pci_irq_host_ops = { 414 .match = pci_irq_host_match, 415 .map = pci_irq_host_map, 416 .xlate = pci_irq_host_xlate, 417}; 418 419/* 420 * Exported functions 421 */ 422 423/* 424 * The Tsi108 PCI interrupts initialization routine. 425 * 426 * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block 427 * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the 428 * PCI block has to be treated as a cascaded interrupt controller connected 429 * to the MPIC. 430 */ 431 432void __init tsi108_pci_int_init(struct device_node *node) 433{ 434 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n"); 435 436 pci_irq_node = of_node_get(node); 437 pci_irq_host = irq_alloc_host(IRQ_HOST_MAP_LEGACY, 0, &pci_irq_host_ops, 0); 438 if (pci_irq_host == NULL) { 439 printk(KERN_ERR "pci_irq_host: failed to allocate irq host !\n"); 440 return; 441 } 442 443 init_pci_source(); 444} 445 446void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) 447{ 448 unsigned int cascade_irq = get_pci_source(); 449 if (cascade_irq != NO_IRQ) 450 generic_handle_irq(cascade_irq); 451 desc->chip->eoi(irq); 452} 453