1/* 2 * SMP support for power macintosh. 3 * 4 * We support both the old "powersurge" SMP architecture 5 * and the current Core99 (G4 PowerMac) machines. 6 * 7 * Note that we don't support the very first rev. of 8 * Apple/DayStar 2 CPUs board, the one with the funky 9 * watchdog. Hopefully, none of these should be there except 10 * maybe internally to Apple. I should probably still add some 11 * code to detect this card though and disable SMP. --BenH. 12 * 13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 14 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 15 * 16 * Support for DayStar quad CPU cards 17 * Copyright (C) XLR8, Inc. 1994-2000 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24#include <linux/kernel.h> 25#include <linux/sched.h> 26#include <linux/smp.h> 27#include <linux/interrupt.h> 28#include <linux/kernel_stat.h> 29#include <linux/delay.h> 30#include <linux/init.h> 31#include <linux/spinlock.h> 32#include <linux/errno.h> 33#include <linux/hardirq.h> 34#include <linux/cpu.h> 35#include <linux/compiler.h> 36 37#include <asm/ptrace.h> 38#include <asm/atomic.h> 39#include <asm/irq.h> 40#include <asm/page.h> 41#include <asm/pgtable.h> 42#include <asm/sections.h> 43#include <asm/io.h> 44#include <asm/prom.h> 45#include <asm/smp.h> 46#include <asm/machdep.h> 47#include <asm/pmac_feature.h> 48#include <asm/time.h> 49#include <asm/mpic.h> 50#include <asm/cacheflush.h> 51#include <asm/keylargo.h> 52#include <asm/pmac_low_i2c.h> 53#include <asm/pmac_pfunc.h> 54 55#define DEBUG 56 57#ifdef DEBUG 58#define DBG(fmt...) udbg_printf(fmt) 59#else 60#define DBG(fmt...) 61#endif 62 63extern void __secondary_start_pmac_0(void); 64extern int pmac_pfunc_base_install(void); 65 66#ifdef CONFIG_PPC32 67 68/* Sync flag for HW tb sync */ 69static volatile int sec_tb_reset = 0; 70 71/* 72 * Powersurge (old powermac SMP) support. 73 */ 74 75/* Addresses for powersurge registers */ 76#define HAMMERHEAD_BASE 0xf8000000 77#define HHEAD_CONFIG 0x90 78#define HHEAD_SEC_INTR 0xc0 79 80/* register for interrupting the primary processor on the powersurge */ 81/* N.B. this is actually the ethernet ROM! */ 82#define PSURGE_PRI_INTR 0xf3019000 83 84/* register for storing the start address for the secondary processor */ 85/* N.B. this is the PCI config space address register for the 1st bridge */ 86#define PSURGE_START 0xf2800000 87 88/* Daystar/XLR8 4-CPU card */ 89#define PSURGE_QUAD_REG_ADDR 0xf8800000 90 91#define PSURGE_QUAD_IRQ_SET 0 92#define PSURGE_QUAD_IRQ_CLR 1 93#define PSURGE_QUAD_IRQ_PRIMARY 2 94#define PSURGE_QUAD_CKSTOP_CTL 3 95#define PSURGE_QUAD_PRIMARY_ARB 4 96#define PSURGE_QUAD_BOARD_ID 6 97#define PSURGE_QUAD_WHICH_CPU 7 98#define PSURGE_QUAD_CKSTOP_RDBK 8 99#define PSURGE_QUAD_RESET_CTL 11 100 101#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 102#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 103#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 104#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 105 106/* virtual addresses for the above */ 107static volatile u8 __iomem *hhead_base; 108static volatile u8 __iomem *quad_base; 109static volatile u32 __iomem *psurge_pri_intr; 110static volatile u8 __iomem *psurge_sec_intr; 111static volatile u32 __iomem *psurge_start; 112 113/* values for psurge_type */ 114#define PSURGE_NONE -1 115#define PSURGE_DUAL 0 116#define PSURGE_QUAD_OKEE 1 117#define PSURGE_QUAD_COTTON 2 118#define PSURGE_QUAD_ICEGRASS 3 119 120/* what sort of powersurge board we have */ 121static int psurge_type = PSURGE_NONE; 122 123/* 124 * Set and clear IPIs for powersurge. 125 */ 126static inline void psurge_set_ipi(int cpu) 127{ 128 if (psurge_type == PSURGE_NONE) 129 return; 130 if (cpu == 0) 131 in_be32(psurge_pri_intr); 132 else if (psurge_type == PSURGE_DUAL) 133 out_8(psurge_sec_intr, 0); 134 else 135 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 136} 137 138static inline void psurge_clr_ipi(int cpu) 139{ 140 if (cpu > 0) { 141 switch(psurge_type) { 142 case PSURGE_DUAL: 143 out_8(psurge_sec_intr, ~0); 144 case PSURGE_NONE: 145 break; 146 default: 147 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 148 } 149 } 150} 151 152/* 153 * On powersurge (old SMP powermac architecture) we don't have 154 * separate IPIs for separate messages like openpic does. Instead 155 * we have a bitmap for each processor, where a 1 bit means that 156 * the corresponding message is pending for that processor. 157 * Ideally each cpu's entry would be in a different cache line. 158 * -- paulus. 159 */ 160static unsigned long psurge_smp_message[NR_CPUS]; 161 162void psurge_smp_message_recv(void) 163{ 164 int cpu = smp_processor_id(); 165 int msg; 166 167 /* clear interrupt */ 168 psurge_clr_ipi(cpu); 169 170 if (num_online_cpus() < 2) 171 return; 172 173 /* make sure there is a message there */ 174 for (msg = 0; msg < 4; msg++) 175 if (test_and_clear_bit(msg, &psurge_smp_message[cpu])) 176 smp_message_recv(msg); 177} 178 179irqreturn_t psurge_primary_intr(int irq, void *d) 180{ 181 psurge_smp_message_recv(); 182 return IRQ_HANDLED; 183} 184 185static void smp_psurge_message_pass(int target, int msg) 186{ 187 int i; 188 189 if (num_online_cpus() < 2) 190 return; 191 192 for_each_online_cpu(i) { 193 if (target == MSG_ALL 194 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id()) 195 || target == i) { 196 set_bit(msg, &psurge_smp_message[i]); 197 psurge_set_ipi(i); 198 } 199 } 200} 201 202/* 203 * Determine a quad card presence. We read the board ID register, we 204 * force the data bus to change to something else, and we read it again. 205 * It it's stable, then the register probably exist (ugh !) 206 */ 207static int __init psurge_quad_probe(void) 208{ 209 int type; 210 unsigned int i; 211 212 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 213 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 214 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 215 return PSURGE_DUAL; 216 217 /* looks OK, try a slightly more rigorous test */ 218 /* bogus is not necessarily cacheline-aligned, 219 though I don't suppose that really matters. -- paulus */ 220 for (i = 0; i < 100; i++) { 221 volatile u32 bogus[8]; 222 bogus[(0+i)%8] = 0x00000000; 223 bogus[(1+i)%8] = 0x55555555; 224 bogus[(2+i)%8] = 0xFFFFFFFF; 225 bogus[(3+i)%8] = 0xAAAAAAAA; 226 bogus[(4+i)%8] = 0x33333333; 227 bogus[(5+i)%8] = 0xCCCCCCCC; 228 bogus[(6+i)%8] = 0xCCCCCCCC; 229 bogus[(7+i)%8] = 0x33333333; 230 wmb(); 231 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 232 mb(); 233 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 234 return PSURGE_DUAL; 235 } 236 return type; 237} 238 239static void __init psurge_quad_init(void) 240{ 241 int procbits; 242 243 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 244 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 245 if (psurge_type == PSURGE_QUAD_ICEGRASS) 246 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 247 else 248 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 249 mdelay(33); 250 out_8(psurge_sec_intr, ~0); 251 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 252 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 253 if (psurge_type != PSURGE_QUAD_ICEGRASS) 254 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 255 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 256 mdelay(33); 257 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 258 mdelay(33); 259 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 260 mdelay(33); 261} 262 263static int __init smp_psurge_probe(void) 264{ 265 int i, ncpus; 266 struct device_node *dn; 267 268 /* We don't do SMP on the PPC601 -- paulus */ 269 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 270 return 1; 271 272 /* 273 * The powersurge cpu board can be used in the generation 274 * of powermacs that have a socket for an upgradeable cpu card, 275 * including the 7500, 8500, 9500, 9600. 276 * The device tree doesn't tell you if you have 2 cpus because 277 * OF doesn't know anything about the 2nd processor. 278 * Instead we look for magic bits in magic registers, 279 * in the hammerhead memory controller in the case of the 280 * dual-cpu powersurge board. -- paulus. 281 */ 282 dn = of_find_node_by_name(NULL, "hammerhead"); 283 if (dn == NULL) 284 return 1; 285 of_node_put(dn); 286 287 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 288 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 289 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 290 291 psurge_type = psurge_quad_probe(); 292 if (psurge_type != PSURGE_DUAL) { 293 psurge_quad_init(); 294 /* All released cards using this HW design have 4 CPUs */ 295 ncpus = 4; 296 } else { 297 iounmap(quad_base); 298 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 299 /* not a dual-cpu card */ 300 iounmap(hhead_base); 301 psurge_type = PSURGE_NONE; 302 return 1; 303 } 304 ncpus = 2; 305 } 306 307 psurge_start = ioremap(PSURGE_START, 4); 308 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 309 310 /* 311 * This is necessary because OF doesn't know about the 312 * secondary cpu(s), and thus there aren't nodes in the 313 * device tree for them, and smp_setup_cpu_maps hasn't 314 * set their bits in cpu_possible_map and cpu_present_map. 315 */ 316 if (ncpus > NR_CPUS) 317 ncpus = NR_CPUS; 318 for (i = 1; i < ncpus ; ++i) { 319 cpu_set(i, cpu_present_map); 320 set_hard_smp_processor_id(i, i); 321 } 322 323 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 324 325 return ncpus; 326} 327 328static void __init smp_psurge_kick_cpu(int nr) 329{ 330 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 331 unsigned long a; 332 int i; 333 334 /* may need to flush here if secondary bats aren't setup */ 335 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 336 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 337 asm volatile("sync"); 338 339 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 340 341 out_be32(psurge_start, start); 342 mb(); 343 344 psurge_set_ipi(nr); 345 /* 346 * We can't use udelay here because the timebase is now frozen. 347 */ 348 for (i = 0; i < 2000; ++i) 349 barrier(); 350 psurge_clr_ipi(nr); 351 352 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 353} 354 355/* 356 * With the dual-cpu powersurge board, the decrementers and timebases 357 * of both cpus are frozen after the secondary cpu is started up, 358 * until we give the secondary cpu another interrupt. This routine 359 * uses this to get the timebases synchronized. 360 * -- paulus. 361 */ 362static void __init psurge_dual_sync_tb(int cpu_nr) 363{ 364 int t; 365 366 set_dec(tb_ticks_per_jiffy); 367 set_tb(0, 0); 368 369 if (cpu_nr > 0) { 370 mb(); 371 sec_tb_reset = 1; 372 return; 373 } 374 375 /* wait for the secondary to have reset its TB before proceeding */ 376 for (t = 10000000; t > 0 && !sec_tb_reset; --t) 377 ; 378 379 /* now interrupt the secondary, starting both TBs */ 380 psurge_set_ipi(1); 381} 382 383static struct irqaction psurge_irqaction = { 384 .handler = psurge_primary_intr, 385 .flags = IRQF_DISABLED, 386 .mask = CPU_MASK_NONE, 387 .name = "primary IPI", 388}; 389 390static void __init smp_psurge_setup_cpu(int cpu_nr) 391{ 392 393 if (cpu_nr == 0) { 394 /* If we failed to start the second CPU, we should still 395 * send it an IPI to start the timebase & DEC or we might 396 * have them stuck. 397 */ 398 if (num_online_cpus() < 2) { 399 if (psurge_type == PSURGE_DUAL) 400 psurge_set_ipi(1); 401 return; 402 } 403 /* reset the entry point so if we get another intr we won't 404 * try to startup again */ 405 out_be32(psurge_start, 0x100); 406 if (setup_irq(30, &psurge_irqaction)) 407 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 408 } 409 410 if (psurge_type == PSURGE_DUAL) 411 psurge_dual_sync_tb(cpu_nr); 412} 413 414void __init smp_psurge_take_timebase(void) 415{ 416 /* Dummy implementation */ 417} 418 419void __init smp_psurge_give_timebase(void) 420{ 421 /* Dummy implementation */ 422} 423 424/* PowerSurge-style Macs */ 425struct smp_ops_t psurge_smp_ops = { 426 .message_pass = smp_psurge_message_pass, 427 .probe = smp_psurge_probe, 428 .kick_cpu = smp_psurge_kick_cpu, 429 .setup_cpu = smp_psurge_setup_cpu, 430 .give_timebase = smp_psurge_give_timebase, 431 .take_timebase = smp_psurge_take_timebase, 432}; 433#endif /* CONFIG_PPC32 - actually powersurge support */ 434 435/* 436 * Core 99 and later support 437 */ 438 439static void (*pmac_tb_freeze)(int freeze); 440static u64 timebase; 441static int tb_req; 442 443static void smp_core99_give_timebase(void) 444{ 445 unsigned long flags; 446 447 local_irq_save(flags); 448 449 while(!tb_req) 450 barrier(); 451 tb_req = 0; 452 (*pmac_tb_freeze)(1); 453 mb(); 454 timebase = get_tb(); 455 mb(); 456 while (timebase) 457 barrier(); 458 mb(); 459 (*pmac_tb_freeze)(0); 460 mb(); 461 462 local_irq_restore(flags); 463} 464 465 466static void __devinit smp_core99_take_timebase(void) 467{ 468 unsigned long flags; 469 470 local_irq_save(flags); 471 472 tb_req = 1; 473 mb(); 474 while (!timebase) 475 barrier(); 476 mb(); 477 set_tb(timebase >> 32, timebase & 0xffffffff); 478 timebase = 0; 479 mb(); 480 set_dec(tb_ticks_per_jiffy/2); 481 482 local_irq_restore(flags); 483} 484 485#ifdef CONFIG_PPC64 486/* 487 * G5s enable/disable the timebase via an i2c-connected clock chip. 488 */ 489static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 490static u8 pmac_tb_pulsar_addr; 491 492static void smp_core99_cypress_tb_freeze(int freeze) 493{ 494 u8 data; 495 int rc; 496 497 /* Strangely, the device-tree says address is 0xd2, but darwin 498 * accesses 0xd0 ... 499 */ 500 pmac_i2c_setmode(pmac_tb_clock_chip_host, 501 pmac_i2c_mode_combined); 502 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 503 0xd0 | pmac_i2c_read, 504 1, 0x81, &data, 1); 505 if (rc != 0) 506 goto bail; 507 508 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 509 510 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 511 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 512 0xd0 | pmac_i2c_write, 513 1, 0x81, &data, 1); 514 515 bail: 516 if (rc != 0) { 517 printk("Cypress Timebase %s rc: %d\n", 518 freeze ? "freeze" : "unfreeze", rc); 519 panic("Timebase freeze failed !\n"); 520 } 521} 522 523 524static void smp_core99_pulsar_tb_freeze(int freeze) 525{ 526 u8 data; 527 int rc; 528 529 pmac_i2c_setmode(pmac_tb_clock_chip_host, 530 pmac_i2c_mode_combined); 531 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 532 pmac_tb_pulsar_addr | pmac_i2c_read, 533 1, 0x2e, &data, 1); 534 if (rc != 0) 535 goto bail; 536 537 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 538 539 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 540 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 541 pmac_tb_pulsar_addr | pmac_i2c_write, 542 1, 0x2e, &data, 1); 543 bail: 544 if (rc != 0) { 545 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 546 freeze ? "freeze" : "unfreeze", rc); 547 panic("Timebase freeze failed !\n"); 548 } 549} 550 551static void __init smp_core99_setup_i2c_hwsync(int ncpus) 552{ 553 struct device_node *cc = NULL; 554 struct device_node *p; 555 const char *name = NULL; 556 const u32 *reg; 557 int ok; 558 559 /* Look for the clock chip */ 560 while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) { 561 p = of_get_parent(cc); 562 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 563 of_node_put(p); 564 if (!ok) 565 continue; 566 567 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 568 if (pmac_tb_clock_chip_host == NULL) 569 continue; 570 reg = of_get_property(cc, "reg", NULL); 571 if (reg == NULL) 572 continue; 573 switch (*reg) { 574 case 0xd2: 575 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 576 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 577 pmac_tb_pulsar_addr = 0xd2; 578 name = "Pulsar"; 579 } else if (of_device_is_compatible(cc, "cy28508")) { 580 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 581 name = "Cypress"; 582 } 583 break; 584 case 0xd4: 585 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 586 pmac_tb_pulsar_addr = 0xd4; 587 name = "Pulsar"; 588 break; 589 } 590 if (pmac_tb_freeze != NULL) 591 break; 592 } 593 if (pmac_tb_freeze != NULL) { 594 /* Open i2c bus for synchronous access */ 595 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 596 printk(KERN_ERR "Failed top open i2c bus for clock" 597 " sync, fallback to software sync !\n"); 598 goto no_i2c_sync; 599 } 600 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 601 name); 602 return; 603 } 604 no_i2c_sync: 605 pmac_tb_freeze = NULL; 606 pmac_tb_clock_chip_host = NULL; 607} 608 609 610 611/* 612 * Newer G5s uses a platform function 613 */ 614 615static void smp_core99_pfunc_tb_freeze(int freeze) 616{ 617 struct device_node *cpus; 618 struct pmf_args args; 619 620 cpus = of_find_node_by_path("/cpus"); 621 BUG_ON(cpus == NULL); 622 args.count = 1; 623 args.u[0].v = !freeze; 624 pmf_call_function(cpus, "cpu-timebase", &args); 625 of_node_put(cpus); 626} 627 628#else /* CONFIG_PPC64 */ 629 630/* 631 * SMP G4 use a GPIO to enable/disable the timebase. 632 */ 633 634static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 635 636static void smp_core99_gpio_tb_freeze(int freeze) 637{ 638 if (freeze) 639 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 640 else 641 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 642 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 643} 644 645 646#endif /* !CONFIG_PPC64 */ 647 648/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 649volatile static long int core99_l2_cache; 650volatile static long int core99_l3_cache; 651 652static void __devinit core99_init_caches(int cpu) 653{ 654#ifndef CONFIG_PPC64 655 if (!cpu_has_feature(CPU_FTR_L2CR)) 656 return; 657 658 if (cpu == 0) { 659 core99_l2_cache = _get_L2CR(); 660 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 661 } else { 662 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 663 _set_L2CR(0); 664 _set_L2CR(core99_l2_cache); 665 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 666 } 667 668 if (!cpu_has_feature(CPU_FTR_L3CR)) 669 return; 670 671 if (cpu == 0){ 672 core99_l3_cache = _get_L3CR(); 673 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 674 } else { 675 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 676 _set_L3CR(0); 677 _set_L3CR(core99_l3_cache); 678 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 679 } 680#endif /* !CONFIG_PPC64 */ 681} 682 683static void __init smp_core99_setup(int ncpus) 684{ 685#ifdef CONFIG_PPC64 686 687 /* i2c based HW sync on some G5s */ 688 if (machine_is_compatible("PowerMac7,2") || 689 machine_is_compatible("PowerMac7,3") || 690 machine_is_compatible("RackMac3,1")) 691 smp_core99_setup_i2c_hwsync(ncpus); 692 693 /* pfunc based HW sync on recent G5s */ 694 if (pmac_tb_freeze == NULL) { 695 struct device_node *cpus = 696 of_find_node_by_path("/cpus"); 697 if (cpus && 698 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 699 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 700 printk(KERN_INFO "Processor timebase sync using" 701 " platform function\n"); 702 } 703 } 704 705#else /* CONFIG_PPC64 */ 706 707 /* GPIO based HW sync on ppc32 Core99 */ 708 if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) { 709 struct device_node *cpu; 710 const u32 *tbprop = NULL; 711 712 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 713 cpu = of_find_node_by_type(NULL, "cpu"); 714 if (cpu != NULL) { 715 tbprop = of_get_property(cpu, "timebase-enable", NULL); 716 if (tbprop) 717 core99_tb_gpio = *tbprop; 718 of_node_put(cpu); 719 } 720 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 721 printk(KERN_INFO "Processor timebase sync using" 722 " GPIO 0x%02x\n", core99_tb_gpio); 723 } 724 725#endif /* CONFIG_PPC64 */ 726 727 /* No timebase sync, fallback to software */ 728 if (pmac_tb_freeze == NULL) { 729 smp_ops->give_timebase = smp_generic_give_timebase; 730 smp_ops->take_timebase = smp_generic_take_timebase; 731 printk(KERN_INFO "Processor timebase sync using software\n"); 732 } 733 734#ifndef CONFIG_PPC64 735 { 736 int i; 737 738 for (i = 1; i < ncpus; ++i) 739 smp_hw_index[i] = i; 740 } 741#endif 742 743 /* 32 bits SMP can't NAP */ 744 if (!machine_is_compatible("MacRISC4")) 745 powersave_nap = 0; 746} 747 748static int __init smp_core99_probe(void) 749{ 750 struct device_node *cpus; 751 int ncpus = 0; 752 753 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 754 755 /* Count CPUs in the device-tree */ 756 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;) 757 ++ncpus; 758 759 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 760 761 /* Nothing more to do if less than 2 of them */ 762 if (ncpus <= 1) 763 return 1; 764 765 /* We need to perform some early initialisations before we can start 766 * setting up SMP as we are running before initcalls 767 */ 768 pmac_pfunc_base_install(); 769 pmac_i2c_init(); 770 771 /* Setup various bits like timebase sync method, ability to nap, ... */ 772 smp_core99_setup(ncpus); 773 774 /* Install IPIs */ 775 mpic_request_ipis(); 776 777 /* Collect l2cr and l3cr values from CPU 0 */ 778 core99_init_caches(0); 779 780 return ncpus; 781} 782 783static void __devinit smp_core99_kick_cpu(int nr) 784{ 785 unsigned int save_vector; 786 unsigned long target, flags; 787 volatile unsigned int *vector 788 = ((volatile unsigned int *)(KERNELBASE+0x100)); 789 790 if (nr < 0 || nr > 3) 791 return; 792 793 if (ppc_md.progress) 794 ppc_md.progress("smp_core99_kick_cpu", 0x346); 795 796 local_irq_save(flags); 797 798 /* Save reset vector */ 799 save_vector = *vector; 800 801 /* Setup fake reset vector that does 802 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE 803 */ 804 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 805 create_branch((unsigned long)vector, target, BRANCH_SET_LINK); 806 807 /* Put some life in our friend */ 808 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 809 810 mdelay(1); 811 812 /* Restore our exception vector */ 813 *vector = save_vector; 814 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); 815 816 local_irq_restore(flags); 817 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 818} 819 820static void __devinit smp_core99_setup_cpu(int cpu_nr) 821{ 822 /* Setup L2/L3 */ 823 if (cpu_nr != 0) 824 core99_init_caches(cpu_nr); 825 826 /* Setup openpic */ 827 mpic_setup_this_cpu(); 828 829 if (cpu_nr == 0) { 830#ifdef CONFIG_PPC64 831 extern void g5_phy_disable_cpu1(void); 832 833 /* Close i2c bus if it was used for tb sync */ 834 if (pmac_tb_clock_chip_host) { 835 pmac_i2c_close(pmac_tb_clock_chip_host); 836 pmac_tb_clock_chip_host = NULL; 837 } 838 839 /* If we didn't start the second CPU, we must take 840 * it off the bus 841 */ 842 if (machine_is_compatible("MacRISC4") && 843 num_online_cpus() < 2) 844 g5_phy_disable_cpu1(); 845#endif /* CONFIG_PPC64 */ 846 847 if (ppc_md.progress) 848 ppc_md.progress("core99_setup_cpu 0 done", 0x349); 849 } 850} 851 852 853#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) 854 855int smp_core99_cpu_disable(void) 856{ 857 cpu_clear(smp_processor_id(), cpu_online_map); 858 859 mpic_cpu_set_priority(0xf); 860 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 861 mb(); 862 udelay(20); 863 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 864 return 0; 865} 866 867extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */ 868static int cpu_dead[NR_CPUS]; 869 870void cpu_die(void) 871{ 872 local_irq_disable(); 873 cpu_dead[smp_processor_id()] = 1; 874 mb(); 875 low_cpu_die(); 876} 877 878void smp_core99_cpu_die(unsigned int cpu) 879{ 880 int timeout; 881 882 timeout = 1000; 883 while (!cpu_dead[cpu]) { 884 if (--timeout == 0) { 885 printk("CPU %u refused to die!\n", cpu); 886 break; 887 } 888 msleep(1); 889 } 890 cpu_dead[cpu] = 0; 891} 892 893#endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */ 894 895/* Core99 Macs (dual G4s and G5s) */ 896struct smp_ops_t core99_smp_ops = { 897 .message_pass = smp_mpic_message_pass, 898 .probe = smp_core99_probe, 899 .kick_cpu = smp_core99_kick_cpu, 900 .setup_cpu = smp_core99_setup_cpu, 901 .give_timebase = smp_core99_give_timebase, 902 .take_timebase = smp_core99_take_timebase, 903#if defined(CONFIG_HOTPLUG_CPU) 904# if defined(CONFIG_PPC32) 905 .cpu_disable = smp_core99_cpu_disable, 906 .cpu_die = smp_core99_cpu_die, 907# endif 908# if defined(CONFIG_PPC64) 909 .cpu_disable = generic_cpu_disable, 910 .cpu_die = generic_cpu_die, 911 /* intentionally do *NOT* assign cpu_enable, 912 * the generic code will use kick_cpu then! */ 913# endif 914#endif 915}; 916