1/* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/pci.h> 15#include <linux/delay.h> 16#include <linux/string.h> 17#include <linux/init.h> 18#include <linux/bootmem.h> 19#include <linux/irq.h> 20 21#include <asm/sections.h> 22#include <asm/io.h> 23#include <asm/prom.h> 24#include <asm/pci-bridge.h> 25#include <asm/machdep.h> 26#include <asm/pmac_feature.h> 27#include <asm/grackle.h> 28#include <asm/ppc-pci.h> 29 30#undef DEBUG 31 32#ifdef DEBUG 33#define DBG(x...) printk(x) 34#else 35#define DBG(x...) 36#endif 37 38static int add_bridge(struct device_node *dev); 39 40static int has_uninorth; 41#ifdef CONFIG_PPC64 42static struct pci_controller *u3_agp; 43static struct pci_controller *u4_pcie; 44static struct pci_controller *u3_ht; 45#else 46static int has_second_ohare; 47#endif /* CONFIG_PPC64 */ 48 49extern int pcibios_assign_bus_offset; 50 51struct device_node *k2_skiplist[2]; 52 53/* 54 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 55 */ 56#define BANDIT_DEVID_2 8 57#define BANDIT_REVID 3 58 59#define BANDIT_DEVNUM 11 60#define BANDIT_MAGIC 0x50 61#define BANDIT_COHERENT 0x40 62 63static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 64{ 65 for (; node != 0;node = node->sibling) { 66 const int * bus_range; 67 const unsigned int *class_code; 68 int len; 69 70 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 71 class_code = of_get_property(node, "class-code", NULL); 72 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 73 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 74 continue; 75 bus_range = of_get_property(node, "bus-range", &len); 76 if (bus_range != NULL && len > 2 * sizeof(int)) { 77 if (bus_range[1] > higher) 78 higher = bus_range[1]; 79 } 80 higher = fixup_one_level_bus_range(node->child, higher); 81 } 82 return higher; 83} 84 85/* This routine fixes the "bus-range" property of all bridges in the 86 * system since they tend to have their "last" member wrong on macs 87 * 88 * Note that the bus numbers manipulated here are OF bus numbers, they 89 * are not Linux bus numbers. 90 */ 91static void __init fixup_bus_range(struct device_node *bridge) 92{ 93 int *bus_range, len; 94 struct property *prop; 95 96 /* Lookup the "bus-range" property for the hose */ 97 prop = of_find_property(bridge, "bus-range", &len); 98 if (prop == NULL || prop->length < 2 * sizeof(int)) 99 return; 100 101 bus_range = prop->value; 102 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 103} 104 105/* 106 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 107 * 108 * The "Bandit" version is present in all early PCI PowerMacs, 109 * and up to the first ones using Grackle. Some machines may 110 * have 2 bandit controllers (2 PCI busses). 111 * 112 * "Chaos" is used in some "Bandit"-type machines as a bridge 113 * for the separate display bus. It is accessed the same 114 * way as bandit, but cannot be probed for devices. It therefore 115 * has its own config access functions. 116 * 117 * The "UniNorth" version is present in all Core99 machines 118 * (iBook, G4, new IMacs, and all the recent Apple machines). 119 * It contains 3 controllers in one ASIC. 120 * 121 * The U3 is the bridge used on G5 machines. It contains an 122 * AGP bus which is dealt with the old UniNorth access routines 123 * and a HyperTransport bus which uses its own set of access 124 * functions. 125 */ 126 127#define MACRISC_CFA0(devfn, off) \ 128 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 129 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 130 | (((unsigned int)(off)) & 0xFCUL)) 131 132#define MACRISC_CFA1(bus, devfn, off) \ 133 ((((unsigned int)(bus)) << 16) \ 134 |(((unsigned int)(devfn)) << 8) \ 135 |(((unsigned int)(off)) & 0xFCUL) \ 136 |1UL) 137 138static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 139 u8 bus, u8 dev_fn, u8 offset) 140{ 141 unsigned int caddr; 142 143 if (bus == hose->first_busno) { 144 if (dev_fn < (11 << 3)) 145 return NULL; 146 caddr = MACRISC_CFA0(dev_fn, offset); 147 } else 148 caddr = MACRISC_CFA1(bus, dev_fn, offset); 149 150 /* Uninorth will return garbage if we don't read back the value ! */ 151 do { 152 out_le32(hose->cfg_addr, caddr); 153 } while (in_le32(hose->cfg_addr) != caddr); 154 155 offset &= has_uninorth ? 0x07 : 0x03; 156 return hose->cfg_data + offset; 157} 158 159static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 160 int offset, int len, u32 *val) 161{ 162 struct pci_controller *hose; 163 volatile void __iomem *addr; 164 165 hose = pci_bus_to_host(bus); 166 if (hose == NULL) 167 return PCIBIOS_DEVICE_NOT_FOUND; 168 if (offset >= 0x100) 169 return PCIBIOS_BAD_REGISTER_NUMBER; 170 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 171 if (!addr) 172 return PCIBIOS_DEVICE_NOT_FOUND; 173 /* 174 * Note: the caller has already checked that offset is 175 * suitably aligned and that len is 1, 2 or 4. 176 */ 177 switch (len) { 178 case 1: 179 *val = in_8(addr); 180 break; 181 case 2: 182 *val = in_le16(addr); 183 break; 184 default: 185 *val = in_le32(addr); 186 break; 187 } 188 return PCIBIOS_SUCCESSFUL; 189} 190 191static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 192 int offset, int len, u32 val) 193{ 194 struct pci_controller *hose; 195 volatile void __iomem *addr; 196 197 hose = pci_bus_to_host(bus); 198 if (hose == NULL) 199 return PCIBIOS_DEVICE_NOT_FOUND; 200 if (offset >= 0x100) 201 return PCIBIOS_BAD_REGISTER_NUMBER; 202 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 203 if (!addr) 204 return PCIBIOS_DEVICE_NOT_FOUND; 205 /* 206 * Note: the caller has already checked that offset is 207 * suitably aligned and that len is 1, 2 or 4. 208 */ 209 switch (len) { 210 case 1: 211 out_8(addr, val); 212 (void) in_8(addr); 213 break; 214 case 2: 215 out_le16(addr, val); 216 (void) in_le16(addr); 217 break; 218 default: 219 out_le32(addr, val); 220 (void) in_le32(addr); 221 break; 222 } 223 return PCIBIOS_SUCCESSFUL; 224} 225 226static struct pci_ops macrisc_pci_ops = 227{ 228 macrisc_read_config, 229 macrisc_write_config 230}; 231 232#ifdef CONFIG_PPC32 233/* 234 * Verify that a specific (bus, dev_fn) exists on chaos 235 */ 236static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 237{ 238 struct device_node *np; 239 const u32 *vendor, *device; 240 241 if (offset >= 0x100) 242 return PCIBIOS_BAD_REGISTER_NUMBER; 243 np = pci_busdev_to_OF_node(bus, devfn); 244 if (np == NULL) 245 return PCIBIOS_DEVICE_NOT_FOUND; 246 247 vendor = of_get_property(np, "vendor-id", NULL); 248 device = of_get_property(np, "device-id", NULL); 249 if (vendor == NULL || device == NULL) 250 return PCIBIOS_DEVICE_NOT_FOUND; 251 252 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 253 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 254 return PCIBIOS_BAD_REGISTER_NUMBER; 255 256 return PCIBIOS_SUCCESSFUL; 257} 258 259static int 260chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 261 int len, u32 *val) 262{ 263 int result = chaos_validate_dev(bus, devfn, offset); 264 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 265 *val = ~0U; 266 if (result != PCIBIOS_SUCCESSFUL) 267 return result; 268 return macrisc_read_config(bus, devfn, offset, len, val); 269} 270 271static int 272chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 273 int len, u32 val) 274{ 275 int result = chaos_validate_dev(bus, devfn, offset); 276 if (result != PCIBIOS_SUCCESSFUL) 277 return result; 278 return macrisc_write_config(bus, devfn, offset, len, val); 279} 280 281static struct pci_ops chaos_pci_ops = 282{ 283 chaos_read_config, 284 chaos_write_config 285}; 286 287static void __init setup_chaos(struct pci_controller *hose, 288 struct resource *addr) 289{ 290 /* assume a `chaos' bridge */ 291 hose->ops = &chaos_pci_ops; 292 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 293 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 294} 295#endif /* CONFIG_PPC32 */ 296 297#ifdef CONFIG_PPC64 298/* 299 * These versions of U3 HyperTransport config space access ops do not 300 * implement self-view of the HT host yet 301 */ 302 303/* 304 * This function deals with some "special cases" devices. 305 * 306 * 0 -> No special case 307 * 1 -> Skip the device but act as if the access was successfull 308 * (return 0xff's on reads, eventually, cache config space 309 * accesses in a later version) 310 * -1 -> Hide the device (unsuccessful acess) 311 */ 312static int u3_ht_skip_device(struct pci_controller *hose, 313 struct pci_bus *bus, unsigned int devfn) 314{ 315 struct device_node *busdn, *dn; 316 int i; 317 318 /* We only allow config cycles to devices that are in OF device-tree 319 * as we are apparently having some weird things going on with some 320 * revs of K2 on recent G5s 321 */ 322 if (bus->self) 323 busdn = pci_device_to_OF_node(bus->self); 324 else 325 busdn = hose->arch_data; 326 for (dn = busdn->child; dn; dn = dn->sibling) 327 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 328 break; 329 if (dn == NULL) 330 return -1; 331 332 /* 333 * When a device in K2 is powered down, we die on config 334 * cycle accesses. Fix that here. 335 */ 336 for (i=0; i<2; i++) 337 if (k2_skiplist[i] == dn) 338 return 1; 339 340 return 0; 341} 342 343#define U3_HT_CFA0(devfn, off) \ 344 ((((unsigned int)devfn) << 8) | offset) 345#define U3_HT_CFA1(bus, devfn, off) \ 346 (U3_HT_CFA0(devfn, off) \ 347 + (((unsigned int)bus) << 16) \ 348 + 0x01000000UL) 349 350static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, 351 u8 bus, u8 devfn, u8 offset) 352{ 353 if (bus == hose->first_busno) { 354 /* For now, we don't self probe U3 HT bridge */ 355 if (PCI_SLOT(devfn) == 0) 356 return NULL; 357 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 358 } else 359 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 360} 361 362static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 363 int offset, int len, u32 *val) 364{ 365 struct pci_controller *hose; 366 volatile void __iomem *addr; 367 368 hose = pci_bus_to_host(bus); 369 if (hose == NULL) 370 return PCIBIOS_DEVICE_NOT_FOUND; 371 if (offset >= 0x100) 372 return PCIBIOS_BAD_REGISTER_NUMBER; 373 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 374 if (!addr) 375 return PCIBIOS_DEVICE_NOT_FOUND; 376 377 switch (u3_ht_skip_device(hose, bus, devfn)) { 378 case 0: 379 break; 380 case 1: 381 switch (len) { 382 case 1: 383 *val = 0xff; break; 384 case 2: 385 *val = 0xffff; break; 386 default: 387 *val = 0xfffffffful; break; 388 } 389 return PCIBIOS_SUCCESSFUL; 390 default: 391 return PCIBIOS_DEVICE_NOT_FOUND; 392 } 393 394 /* 395 * Note: the caller has already checked that offset is 396 * suitably aligned and that len is 1, 2 or 4. 397 */ 398 switch (len) { 399 case 1: 400 *val = in_8(addr); 401 break; 402 case 2: 403 *val = in_le16(addr); 404 break; 405 default: 406 *val = in_le32(addr); 407 break; 408 } 409 return PCIBIOS_SUCCESSFUL; 410} 411 412static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 413 int offset, int len, u32 val) 414{ 415 struct pci_controller *hose; 416 volatile void __iomem *addr; 417 418 hose = pci_bus_to_host(bus); 419 if (hose == NULL) 420 return PCIBIOS_DEVICE_NOT_FOUND; 421 if (offset >= 0x100) 422 return PCIBIOS_BAD_REGISTER_NUMBER; 423 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 424 if (!addr) 425 return PCIBIOS_DEVICE_NOT_FOUND; 426 427 switch (u3_ht_skip_device(hose, bus, devfn)) { 428 case 0: 429 break; 430 case 1: 431 return PCIBIOS_SUCCESSFUL; 432 default: 433 return PCIBIOS_DEVICE_NOT_FOUND; 434 } 435 436 /* 437 * Note: the caller has already checked that offset is 438 * suitably aligned and that len is 1, 2 or 4. 439 */ 440 switch (len) { 441 case 1: 442 out_8(addr, val); 443 (void) in_8(addr); 444 break; 445 case 2: 446 out_le16(addr, val); 447 (void) in_le16(addr); 448 break; 449 default: 450 out_le32((u32 __iomem *)addr, val); 451 (void) in_le32(addr); 452 break; 453 } 454 return PCIBIOS_SUCCESSFUL; 455} 456 457static struct pci_ops u3_ht_pci_ops = 458{ 459 u3_ht_read_config, 460 u3_ht_write_config 461}; 462 463#define U4_PCIE_CFA0(devfn, off) \ 464 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 465 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 466 | ((((unsigned int)(off)) >> 8) << 28) \ 467 | (((unsigned int)(off)) & 0xfcU)) 468 469#define U4_PCIE_CFA1(bus, devfn, off) \ 470 ((((unsigned int)(bus)) << 16) \ 471 |(((unsigned int)(devfn)) << 8) \ 472 | ((((unsigned int)(off)) >> 8) << 28) \ 473 |(((unsigned int)(off)) & 0xfcU) \ 474 |1UL) 475 476static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 477 u8 bus, u8 dev_fn, int offset) 478{ 479 unsigned int caddr; 480 481 if (bus == hose->first_busno) { 482 caddr = U4_PCIE_CFA0(dev_fn, offset); 483 } else 484 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 485 486 /* Uninorth will return garbage if we don't read back the value ! */ 487 do { 488 out_le32(hose->cfg_addr, caddr); 489 } while (in_le32(hose->cfg_addr) != caddr); 490 491 offset &= 0x03; 492 return hose->cfg_data + offset; 493} 494 495static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 496 int offset, int len, u32 *val) 497{ 498 struct pci_controller *hose; 499 volatile void __iomem *addr; 500 501 hose = pci_bus_to_host(bus); 502 if (hose == NULL) 503 return PCIBIOS_DEVICE_NOT_FOUND; 504 if (offset >= 0x1000) 505 return PCIBIOS_BAD_REGISTER_NUMBER; 506 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 507 if (!addr) 508 return PCIBIOS_DEVICE_NOT_FOUND; 509 /* 510 * Note: the caller has already checked that offset is 511 * suitably aligned and that len is 1, 2 or 4. 512 */ 513 switch (len) { 514 case 1: 515 *val = in_8(addr); 516 break; 517 case 2: 518 *val = in_le16(addr); 519 break; 520 default: 521 *val = in_le32(addr); 522 break; 523 } 524 return PCIBIOS_SUCCESSFUL; 525} 526 527static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 528 int offset, int len, u32 val) 529{ 530 struct pci_controller *hose; 531 volatile void __iomem *addr; 532 533 hose = pci_bus_to_host(bus); 534 if (hose == NULL) 535 return PCIBIOS_DEVICE_NOT_FOUND; 536 if (offset >= 0x1000) 537 return PCIBIOS_BAD_REGISTER_NUMBER; 538 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 539 if (!addr) 540 return PCIBIOS_DEVICE_NOT_FOUND; 541 /* 542 * Note: the caller has already checked that offset is 543 * suitably aligned and that len is 1, 2 or 4. 544 */ 545 switch (len) { 546 case 1: 547 out_8(addr, val); 548 (void) in_8(addr); 549 break; 550 case 2: 551 out_le16(addr, val); 552 (void) in_le16(addr); 553 break; 554 default: 555 out_le32(addr, val); 556 (void) in_le32(addr); 557 break; 558 } 559 return PCIBIOS_SUCCESSFUL; 560} 561 562static struct pci_ops u4_pcie_pci_ops = 563{ 564 u4_pcie_read_config, 565 u4_pcie_write_config 566}; 567 568#endif /* CONFIG_PPC64 */ 569 570#ifdef CONFIG_PPC32 571/* 572 * For a bandit bridge, turn on cache coherency if necessary. 573 * N.B. we could clean this up using the hose ops directly. 574 */ 575static void __init init_bandit(struct pci_controller *bp) 576{ 577 unsigned int vendev, magic; 578 int rev; 579 580 /* read the word at offset 0 in config space for device 11 */ 581 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 582 udelay(2); 583 vendev = in_le32(bp->cfg_data); 584 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 585 PCI_VENDOR_ID_APPLE) { 586 /* read the revision id */ 587 out_le32(bp->cfg_addr, 588 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 589 udelay(2); 590 rev = in_8(bp->cfg_data); 591 if (rev != BANDIT_REVID) 592 printk(KERN_WARNING 593 "Unknown revision %d for bandit\n", rev); 594 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 595 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 596 return; 597 } 598 599 /* read the word at offset 0x50 */ 600 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 601 udelay(2); 602 magic = in_le32(bp->cfg_data); 603 if ((magic & BANDIT_COHERENT) != 0) 604 return; 605 magic |= BANDIT_COHERENT; 606 udelay(2); 607 out_le32(bp->cfg_data, magic); 608 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 609} 610 611/* 612 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 613 */ 614static void __init init_p2pbridge(void) 615{ 616 struct device_node *p2pbridge; 617 struct pci_controller* hose; 618 u8 bus, devfn; 619 u16 val; 620 621 p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); 622 if (p2pbridge == NULL 623 || p2pbridge->parent == NULL 624 || strcmp(p2pbridge->parent->name, "pci") != 0) 625 goto done; 626 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 627 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 628 goto done; 629 } 630 /* Warning: At this point, we have not yet renumbered all busses. 631 * So we must use OF walking to find out hose 632 */ 633 hose = pci_find_hose_for_OF_device(p2pbridge); 634 if (!hose) { 635 DBG("Can't find hose for PCI<->PCI bridge\n"); 636 goto done; 637 } 638 if (early_read_config_word(hose, bus, devfn, 639 PCI_BRIDGE_CONTROL, &val) < 0) { 640 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 641 " control\n"); 642 goto done; 643 } 644 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 645 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 646done: 647 of_node_put(p2pbridge); 648} 649 650static void __init init_second_ohare(void) 651{ 652 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); 653 unsigned char bus, devfn; 654 unsigned short cmd; 655 656 if (np == NULL) 657 return; 658 659 /* This must run before we initialize the PICs since the second 660 * ohare hosts a PIC that will be accessed there. 661 */ 662 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 663 struct pci_controller* hose = 664 pci_find_hose_for_OF_device(np); 665 if (!hose) { 666 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 667 return; 668 } 669 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 670 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 671 cmd &= ~PCI_COMMAND_IO; 672 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 673 } 674 has_second_ohare = 1; 675} 676 677/* 678 * Some Apple desktop machines have a NEC PD720100A USB2 controller 679 * on the motherboard. Open Firmware, on these, will disable the 680 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 681 * code re-enables it ;) 682 */ 683static void __init fixup_nec_usb2(void) 684{ 685 struct device_node *nec; 686 687 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 688 struct pci_controller *hose; 689 u32 data; 690 const u32 *prop; 691 u8 bus, devfn; 692 693 prop = of_get_property(nec, "vendor-id", NULL); 694 if (prop == NULL) 695 continue; 696 if (0x1033 != *prop) 697 continue; 698 prop = of_get_property(nec, "device-id", NULL); 699 if (prop == NULL) 700 continue; 701 if (0x0035 != *prop) 702 continue; 703 prop = of_get_property(nec, "reg", NULL); 704 if (prop == NULL) 705 continue; 706 devfn = (prop[0] >> 8) & 0xff; 707 bus = (prop[0] >> 16) & 0xff; 708 if (PCI_FUNC(devfn) != 0) 709 continue; 710 hose = pci_find_hose_for_OF_device(nec); 711 if (!hose) 712 continue; 713 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 714 if (data & 1UL) { 715 printk("Found NEC PD720100A USB2 chip with disabled" 716 " EHCI, fixing up...\n"); 717 data &= ~1UL; 718 early_write_config_dword(hose, bus, devfn, 0xe4, data); 719 } 720 } 721} 722 723static void __init setup_bandit(struct pci_controller *hose, 724 struct resource *addr) 725{ 726 hose->ops = ¯isc_pci_ops; 727 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 728 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 729 init_bandit(hose); 730} 731 732static int __init setup_uninorth(struct pci_controller *hose, 733 struct resource *addr) 734{ 735 pci_assign_all_buses = 1; 736 has_uninorth = 1; 737 hose->ops = ¯isc_pci_ops; 738 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 739 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 740 /* We "know" that the bridge at f2000000 has the PCI slots. */ 741 return addr->start == 0xf2000000; 742} 743#endif /* CONFIG_PPC32 */ 744 745#ifdef CONFIG_PPC64 746static void __init setup_u3_agp(struct pci_controller* hose) 747{ 748 /* On G5, we move AGP up to high bus number so we don't need 749 * to reassign bus numbers for HT. If we ever have P2P bridges 750 * on AGP, we'll have to move pci_assign_all_busses to the 751 * pci_controller structure so we enable it for AGP and not for 752 * HT childs. 753 * We hard code the address because of the different size of 754 * the reg address cell, we shall fix that by killing struct 755 * reg_property and using some accessor functions instead 756 */ 757 hose->first_busno = 0xf0; 758 hose->last_busno = 0xff; 759 has_uninorth = 1; 760 hose->ops = ¯isc_pci_ops; 761 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 762 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 763 u3_agp = hose; 764} 765 766static void __init setup_u4_pcie(struct pci_controller* hose) 767{ 768 /* We currently only implement the "non-atomic" config space, to 769 * be optimised later. 770 */ 771 hose->ops = &u4_pcie_pci_ops; 772 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 773 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 774 775 /* The bus contains a bridge from root -> device, we need to 776 * make it visible on bus 0 so that we pick the right type 777 * of config cycles. If we didn't, we would have to force all 778 * config cycles to be type 1. So we override the "bus-range" 779 * property here 780 */ 781 hose->first_busno = 0x00; 782 hose->last_busno = 0xff; 783 u4_pcie = hose; 784} 785 786static void __init setup_u3_ht(struct pci_controller* hose) 787{ 788 struct device_node *np = (struct device_node *)hose->arch_data; 789 struct pci_controller *other = NULL; 790 int i, cur; 791 792 793 hose->ops = &u3_ht_pci_ops; 794 795 /* We hard code the address because of the different size of 796 * the reg address cell, we shall fix that by killing struct 797 * reg_property and using some accessor functions instead 798 */ 799 hose->cfg_data = ioremap(0xf2000000, 0x02000000); 800 801 /* 802 * /ht node doesn't expose a "ranges" property, so we "remove" 803 * regions that have been allocated to AGP. So far, this version of 804 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions 805 * to /ht. We need to fix that sooner or later by either parsing all 806 * child "ranges" properties or figuring out the U3 address space 807 * decoding logic and then read its configuration register (if any). 808 */ 809 hose->io_base_phys = 0xf4000000; 810 hose->pci_io_size = 0x00400000; 811 hose->io_resource.name = np->full_name; 812 hose->io_resource.start = 0; 813 hose->io_resource.end = 0x003fffff; 814 hose->io_resource.flags = IORESOURCE_IO; 815 hose->pci_mem_offset = 0; 816 hose->first_busno = 0; 817 hose->last_busno = 0xef; 818 hose->mem_resources[0].name = np->full_name; 819 hose->mem_resources[0].start = 0x80000000; 820 hose->mem_resources[0].end = 0xefffffff; 821 hose->mem_resources[0].flags = IORESOURCE_MEM; 822 823 u3_ht = hose; 824 825 if (u3_agp != NULL) 826 other = u3_agp; 827 else if (u4_pcie != NULL) 828 other = u4_pcie; 829 830 if (other == NULL) { 831 DBG("U3/4 has no AGP/PCIE, using full resource range\n"); 832 return; 833 } 834 835 /* Fixup bus range vs. PCIE */ 836 if (u4_pcie) 837 hose->last_busno = u4_pcie->first_busno - 1; 838 839 /* We "remove" the AGP resources from the resources allocated to HT, 840 * that is we create "holes". However, that code does assumptions 841 * that so far happen to be true (cross fingers...), typically that 842 * resources in the AGP node are properly ordered 843 */ 844 cur = 0; 845 for (i=0; i<3; i++) { 846 struct resource *res = &other->mem_resources[i]; 847 if (res->flags != IORESOURCE_MEM) 848 continue; 849 /* We don't care about "fine" resources */ 850 if (res->start >= 0xf0000000) 851 continue; 852 /* Check if it's just a matter of "shrinking" us in one 853 * direction 854 */ 855 if (hose->mem_resources[cur].start == res->start) { 856 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", 857 cur, hose->mem_resources[cur].start, 858 res->end + 1); 859 hose->mem_resources[cur].start = res->end + 1; 860 continue; 861 } 862 if (hose->mem_resources[cur].end == res->end) { 863 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", 864 cur, hose->mem_resources[cur].end, 865 res->start - 1); 866 hose->mem_resources[cur].end = res->start - 1; 867 continue; 868 } 869 /* No, it's not the case, we need a hole */ 870 if (cur == 2) { 871 /* not enough resources for a hole, we drop part 872 * of the range 873 */ 874 printk(KERN_WARNING "Running out of resources" 875 " for /ht host !\n"); 876 hose->mem_resources[cur].end = res->start - 1; 877 continue; 878 } 879 cur++; 880 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", 881 cur-1, res->start - 1, cur, res->end + 1); 882 hose->mem_resources[cur].name = np->full_name; 883 hose->mem_resources[cur].flags = IORESOURCE_MEM; 884 hose->mem_resources[cur].start = res->end + 1; 885 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; 886 hose->mem_resources[cur-1].end = res->start - 1; 887 } 888} 889#endif /* CONFIG_PPC64 */ 890 891/* 892 * We assume that if we have a G3 powermac, we have one bridge called 893 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 894 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 895 */ 896static int __init add_bridge(struct device_node *dev) 897{ 898 int len; 899 struct pci_controller *hose; 900 struct resource rsrc; 901 char *disp_name; 902 const int *bus_range; 903 int primary = 1, has_address = 0; 904 905 DBG("Adding PCI host bridge %s\n", dev->full_name); 906 907 /* Fetch host bridge registers address */ 908 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 909 910 /* Get bus range if any */ 911 bus_range = of_get_property(dev, "bus-range", &len); 912 if (bus_range == NULL || len < 2 * sizeof(int)) { 913 printk(KERN_WARNING "Can't get bus-range for %s, assume" 914 " bus 0\n", dev->full_name); 915 } 916 917#ifdef CONFIG_PPC64 918 hose = pcibios_alloc_controller(dev); 919#else 920 hose = pcibios_alloc_controller(); 921#endif 922 if (!hose) 923 return -ENOMEM; 924 hose->arch_data = dev; 925 hose->first_busno = bus_range ? bus_range[0] : 0; 926 hose->last_busno = bus_range ? bus_range[1] : 0xff; 927 928 disp_name = NULL; 929 930 /* 64 bits only bridges */ 931#ifdef CONFIG_PPC64 932 if (of_device_is_compatible(dev, "u3-agp")) { 933 setup_u3_agp(hose); 934 disp_name = "U3-AGP"; 935 primary = 0; 936 } else if (of_device_is_compatible(dev, "u3-ht")) { 937 setup_u3_ht(hose); 938 disp_name = "U3-HT"; 939 primary = 1; 940 } else if (of_device_is_compatible(dev, "u4-pcie")) { 941 setup_u4_pcie(hose); 942 disp_name = "U4-PCIE"; 943 primary = 0; 944 } 945 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 946 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 947#endif /* CONFIG_PPC64 */ 948 949 /* 32 bits only bridges */ 950#ifdef CONFIG_PPC32 951 if (of_device_is_compatible(dev, "uni-north")) { 952 primary = setup_uninorth(hose, &rsrc); 953 disp_name = "UniNorth"; 954 } else if (strcmp(dev->name, "pci") == 0) { 955 setup_grackle(hose); 956 disp_name = "Grackle (MPC106)"; 957 } else if (strcmp(dev->name, "bandit") == 0) { 958 setup_bandit(hose, &rsrc); 959 disp_name = "Bandit"; 960 } else if (strcmp(dev->name, "chaos") == 0) { 961 setup_chaos(hose, &rsrc); 962 disp_name = "Chaos"; 963 primary = 0; 964 } 965 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 966 "Firmware bus number: %d->%d\n", 967 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 968 hose->last_busno); 969#endif /* CONFIG_PPC32 */ 970 971 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 972 hose, hose->cfg_addr, hose->cfg_data); 973 974 /* Interpret the "ranges" property */ 975 /* This also maps the I/O region and sets isa_io/mem_base */ 976 pci_process_bridge_OF_ranges(hose, dev, primary); 977 978 /* Fixup "bus-range" OF property */ 979 fixup_bus_range(dev); 980 981 return 0; 982} 983 984void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) 985{ 986#ifdef CONFIG_PPC32 987 /* Fixup interrupt for the modem/ethernet combo controller. 988 * on machines with a second ohare chip. 989 * The number in the device tree (27) is bogus (correct for 990 * the ethernet-only board but not the combo ethernet/modem 991 * board). The real interrupt is 28 on the second controller 992 * -> 28+32 = 60. 993 */ 994 if (has_second_ohare && 995 dev->vendor == PCI_VENDOR_ID_DEC && 996 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { 997 dev->irq = irq_create_mapping(NULL, 60); 998 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 999 } 1000#endif /* CONFIG_PPC32 */ 1001} 1002 1003#ifdef CONFIG_PPC64 1004static void __init pmac_fixup_phb_resources(void) 1005{ 1006 struct pci_controller *hose, *tmp; 1007 1008 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1009 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", 1010 hose->global_number, 1011 hose->io_resource.start, hose->io_resource.end); 1012 } 1013} 1014#endif 1015 1016void __init pmac_pci_init(void) 1017{ 1018 struct device_node *np, *root; 1019 struct device_node *ht = NULL; 1020 1021 root = of_find_node_by_path("/"); 1022 if (root == NULL) { 1023 printk(KERN_CRIT "pmac_pci_init: can't find root " 1024 "of device tree\n"); 1025 return; 1026 } 1027 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 1028 if (np->name == NULL) 1029 continue; 1030 if (strcmp(np->name, "bandit") == 0 1031 || strcmp(np->name, "chaos") == 0 1032 || strcmp(np->name, "pci") == 0) { 1033 if (add_bridge(np) == 0) 1034 of_node_get(np); 1035 } 1036 if (strcmp(np->name, "ht") == 0) { 1037 of_node_get(np); 1038 ht = np; 1039 } 1040 } 1041 of_node_put(root); 1042 1043#ifdef CONFIG_PPC64 1044 /* Probe HT last as it relies on the agp resources to be already 1045 * setup 1046 */ 1047 if (ht && add_bridge(ht) != 0) 1048 of_node_put(ht); 1049 1050 /* 1051 * We need to call pci_setup_phb_io for the HT bridge first 1052 * so it gets the I/O port numbers starting at 0, and we 1053 * need to call it for the AGP bridge after that so it gets 1054 * small positive I/O port numbers. 1055 */ 1056 if (u3_ht) 1057 pci_setup_phb_io(u3_ht, 1); 1058 if (u3_agp) 1059 pci_setup_phb_io(u3_agp, 0); 1060 if (u4_pcie) 1061 pci_setup_phb_io(u4_pcie, 0); 1062 1063 /* 1064 * On ppc64, fixup the IO resources on our host bridges as 1065 * the common code does it only for children of the host bridges 1066 */ 1067 pmac_fixup_phb_resources(); 1068 1069 /* Setup the linkage between OF nodes and PHBs */ 1070 pci_devs_phb_init(); 1071 1072 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 1073 * assume there is no P2P bridge on the AGP bus, which should be a 1074 * safe assumptions for now. We should do something better in the 1075 * future though 1076 */ 1077 if (u3_agp) { 1078 struct device_node *np = u3_agp->arch_data; 1079 PCI_DN(np)->busno = 0xf0; 1080 for (np = np->child; np; np = np->sibling) 1081 PCI_DN(np)->busno = 0xf0; 1082 } 1083 /* pmac_check_ht_link(); */ 1084 1085 /* Tell pci.c to not use the common resource allocation mechanism */ 1086 pci_probe_only = 1; 1087 1088#else /* CONFIG_PPC64 */ 1089 init_p2pbridge(); 1090 init_second_ohare(); 1091 fixup_nec_usb2(); 1092 1093 /* We are still having some issues with the Xserve G4, enabling 1094 * some offset between bus number and domains for now when we 1095 * assign all busses should help for now 1096 */ 1097 if (pci_assign_all_buses) 1098 pcibios_assign_bus_offset = 0x10; 1099#endif 1100} 1101 1102int 1103pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) 1104{ 1105 struct device_node* node; 1106 int updatecfg = 0; 1107 int uninorth_child; 1108 1109 node = pci_device_to_OF_node(dev); 1110 1111 /* We don't want to enable USB controllers absent from the OF tree 1112 * (iBook second controller) 1113 */ 1114 if (dev->vendor == PCI_VENDOR_ID_APPLE 1115 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 1116 && !node) { 1117 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 1118 pci_name(dev)); 1119 return -EINVAL; 1120 } 1121 1122 if (!node) 1123 return 0; 1124 1125 uninorth_child = node->parent && 1126 of_device_is_compatible(node->parent, "uni-north"); 1127 1128 /* Firewire & GMAC were disabled after PCI probe, the driver is 1129 * claiming them, we must re-enable them now. 1130 */ 1131 if (uninorth_child && !strcmp(node->name, "firewire") && 1132 (of_device_is_compatible(node, "pci106b,18") || 1133 of_device_is_compatible(node, "pci106b,30") || 1134 of_device_is_compatible(node, "pci11c1,5811"))) { 1135 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 1136 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 1137 updatecfg = 1; 1138 } 1139 if (uninorth_child && !strcmp(node->name, "ethernet") && 1140 of_device_is_compatible(node, "gmac")) { 1141 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 1142 updatecfg = 1; 1143 } 1144 1145 if (updatecfg) { 1146 u16 cmd; 1147 1148 /* 1149 * Make sure PCI is correctly configured 1150 * 1151 * We use old pci_bios versions of the function since, by 1152 * default, gmac is not powered up, and so will be absent 1153 * from the kernel initial PCI lookup. 1154 * 1155 * Should be replaced by 2.4 new PCI mechanisms and really 1156 * register the device. 1157 */ 1158 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1159 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1160 | PCI_COMMAND_INVALIDATE; 1161 pci_write_config_word(dev, PCI_COMMAND, cmd); 1162 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1163 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1164 L1_CACHE_BYTES >> 2); 1165 } 1166 1167 return 0; 1168} 1169 1170/* We power down some devices after they have been probed. They'll 1171 * be powered back on later on 1172 */ 1173void __init pmac_pcibios_after_init(void) 1174{ 1175 struct device_node* nd; 1176 1177#ifdef CONFIG_BLK_DEV_IDE 1178 struct pci_dev *dev = NULL; 1179 1180 /* OF fails to initialize IDE controllers on macs 1181 * (and maybe other machines) 1182 * 1183 * Ideally, this should be moved to the IDE layer, but we need 1184 * to check specifically with Andre Hedrick how to do it cleanly 1185 * since the common IDE code seem to care about the fact that the 1186 * BIOS may have disabled a controller. 1187 * 1188 * -- BenH 1189 */ 1190 for_each_pci_dev(dev) { 1191 if ((dev->class >> 16) != PCI_BASE_CLASS_STORAGE) 1192 continue; 1193 if (pci_enable_device(dev)) 1194 printk(KERN_WARNING 1195 "pci: Failed to enable %s\n", pci_name(dev)); 1196 } 1197#endif /* CONFIG_BLK_DEV_IDE */ 1198 1199 for_each_node_by_name(nd, "firewire") { 1200 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || 1201 of_device_is_compatible(nd, "pci106b,30") || 1202 of_device_is_compatible(nd, "pci11c1,5811")) 1203 && of_device_is_compatible(nd->parent, "uni-north")) { 1204 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1205 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1206 } 1207 } 1208 of_node_put(nd); 1209 for_each_node_by_name(nd, "ethernet") { 1210 if (nd->parent && of_device_is_compatible(nd, "gmac") 1211 && of_device_is_compatible(nd->parent, "uni-north")) 1212 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1213 } 1214 of_node_put(nd); 1215} 1216 1217#ifdef CONFIG_PPC32 1218void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1219{ 1220 if (!machine_is(powermac)) 1221 return; 1222 /* 1223 * Fix the interrupt routing on the various cardbus bridges 1224 * used on powerbooks 1225 */ 1226 if (dev->vendor != PCI_VENDOR_ID_TI) 1227 return; 1228 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1229 dev->device == PCI_DEVICE_ID_TI_1131) { 1230 u8 val; 1231 /* Enable PCI interrupt */ 1232 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1233 pci_write_config_byte(dev, 0x91, val | 0x30); 1234 /* Disable ISA interrupt mode */ 1235 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1236 pci_write_config_byte(dev, 0x92, val & ~0x06); 1237 } 1238 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1239 dev->device == PCI_DEVICE_ID_TI_1211 || 1240 dev->device == PCI_DEVICE_ID_TI_1410 || 1241 dev->device == PCI_DEVICE_ID_TI_1510) { 1242 u8 val; 1243 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1244 signal out the MFUNC0 pin */ 1245 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1246 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1247 /* Disable ISA interrupt mode */ 1248 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1249 pci_write_config_byte(dev, 0x92, val & ~0x06); 1250 } 1251} 1252 1253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1254 1255void pmac_pci_fixup_pciata(struct pci_dev* dev) 1256{ 1257 u8 progif = 0; 1258 1259 /* 1260 * On PowerMacs, we try to switch any PCI ATA controller to 1261 * fully native mode 1262 */ 1263 if (!machine_is(powermac)) 1264 return; 1265 1266 /* Some controllers don't have the class IDE */ 1267 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1268 switch(dev->device) { 1269 case PCI_DEVICE_ID_PROMISE_20246: 1270 case PCI_DEVICE_ID_PROMISE_20262: 1271 case PCI_DEVICE_ID_PROMISE_20263: 1272 case PCI_DEVICE_ID_PROMISE_20265: 1273 case PCI_DEVICE_ID_PROMISE_20267: 1274 case PCI_DEVICE_ID_PROMISE_20268: 1275 case PCI_DEVICE_ID_PROMISE_20269: 1276 case PCI_DEVICE_ID_PROMISE_20270: 1277 case PCI_DEVICE_ID_PROMISE_20271: 1278 case PCI_DEVICE_ID_PROMISE_20275: 1279 case PCI_DEVICE_ID_PROMISE_20276: 1280 case PCI_DEVICE_ID_PROMISE_20277: 1281 goto good; 1282 } 1283 /* Others, check PCI class */ 1284 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1285 return; 1286 good: 1287 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1288 if ((progif & 5) != 5) { 1289 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", 1290 pci_name(dev)); 1291 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1292 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1293 (progif & 5) != 5) 1294 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1295 } 1296} 1297DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1298#endif 1299 1300/* 1301 * Disable second function on K2-SATA, it's broken 1302 * and disable IO BARs on first one 1303 */ 1304static void fixup_k2_sata(struct pci_dev* dev) 1305{ 1306 int i; 1307 u16 cmd; 1308 1309 if (PCI_FUNC(dev->devfn) > 0) { 1310 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1311 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1312 pci_write_config_word(dev, PCI_COMMAND, cmd); 1313 for (i = 0; i < 6; i++) { 1314 dev->resource[i].start = dev->resource[i].end = 0; 1315 dev->resource[i].flags = 0; 1316 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1317 0); 1318 } 1319 } else { 1320 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1321 cmd &= ~PCI_COMMAND_IO; 1322 pci_write_config_word(dev, PCI_COMMAND, cmd); 1323 for (i = 0; i < 5; i++) { 1324 dev->resource[i].start = dev->resource[i].end = 0; 1325 dev->resource[i].flags = 0; 1326 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1327 0); 1328 } 1329 } 1330} 1331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1332