1/* 2 * Copyright (C) 2001 Allan Trautman, IBM Corporation 3 * 4 * iSeries specific routines for PCI. 5 * 6 * Based on code from pci.c and iSeries_pci.c 32bit 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22#include <linux/kernel.h> 23#include <linux/list.h> 24#include <linux/string.h> 25#include <linux/init.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28 29#include <asm/io.h> 30#include <asm/irq.h> 31#include <asm/prom.h> 32#include <asm/machdep.h> 33#include <asm/pci-bridge.h> 34#include <asm/iommu.h> 35#include <asm/abs_addr.h> 36#include <asm/firmware.h> 37 38#include <asm/iseries/hv_call_xm.h> 39#include <asm/iseries/mf.h> 40#include <asm/iseries/iommu.h> 41 42#include <asm/ppc-pci.h> 43 44#include "irq.h" 45#include "pci.h" 46#include "call_pci.h" 47 48/* 49 * Forward declares of prototypes. 50 */ 51static struct device_node *find_Device_Node(int bus, int devfn); 52 53static int Pci_Retry_Max = 3; /* Only retry 3 times */ 54static int Pci_Error_Flag = 1; /* Set Retry Error on. */ 55 56static struct pci_ops iSeries_pci_ops; 57 58/* 59 * Table defines 60 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space. 61 */ 62#define IOMM_TABLE_MAX_ENTRIES 1024 63#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL 64#define BASE_IO_MEMORY 0xE000000000000000UL 65 66static unsigned long max_io_memory = BASE_IO_MEMORY; 67static long current_iomm_table_entry; 68 69/* 70 * Lookup Tables. 71 */ 72static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES]; 73static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES]; 74 75static const char pci_io_text[] = "iSeries PCI I/O"; 76static DEFINE_SPINLOCK(iomm_table_lock); 77 78/* 79 * iomm_table_allocate_entry 80 * 81 * Adds pci_dev entry in address translation table 82 * 83 * - Allocates the number of entries required in table base on BAR 84 * size. 85 * - Allocates starting at BASE_IO_MEMORY and increases. 86 * - The size is round up to be a multiple of entry size. 87 * - CurrentIndex is incremented to keep track of the last entry. 88 * - Builds the resource entry for allocated BARs. 89 */ 90static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) 91{ 92 struct resource *bar_res = &dev->resource[bar_num]; 93 long bar_size = pci_resource_len(dev, bar_num); 94 95 /* 96 * No space to allocate, quick exit, skip Allocation. 97 */ 98 if (bar_size == 0) 99 return; 100 /* 101 * Set Resource values. 102 */ 103 spin_lock(&iomm_table_lock); 104 bar_res->name = pci_io_text; 105 bar_res->start = BASE_IO_MEMORY + 106 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; 107 bar_res->end = bar_res->start + bar_size - 1; 108 /* 109 * Allocate the number of table entries needed for BAR. 110 */ 111 while (bar_size > 0 ) { 112 iomm_table[current_iomm_table_entry] = dev->sysdata; 113 iobar_table[current_iomm_table_entry] = bar_num; 114 bar_size -= IOMM_TABLE_ENTRY_SIZE; 115 ++current_iomm_table_entry; 116 } 117 max_io_memory = BASE_IO_MEMORY + 118 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; 119 spin_unlock(&iomm_table_lock); 120} 121 122/* 123 * allocate_device_bars 124 * 125 * - Allocates ALL pci_dev BAR's and updates the resources with the 126 * BAR value. BARS with zero length will have the resources 127 * The HvCallPci_getBarParms is used to get the size of the BAR 128 * space. It calls iomm_table_allocate_entry to allocate 129 * each entry. 130 * - Loops through The Bar resources(0 - 5) including the ROM 131 * is resource(6). 132 */ 133static void allocate_device_bars(struct pci_dev *dev) 134{ 135 int bar_num; 136 137 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) 138 iomm_table_allocate_entry(dev, bar_num); 139} 140 141/* 142 * Log error information to system console. 143 * Filter out the device not there errors. 144 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx 145 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx 146 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx 147 */ 148static void pci_Log_Error(char *Error_Text, int Bus, int SubBus, 149 int AgentId, int HvRc) 150{ 151 if (HvRc == 0x0302) 152 return; 153 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", 154 Error_Text, Bus, SubBus, AgentId, HvRc); 155} 156 157/* 158 * iSeries_pci_final_fixup(void) 159 */ 160void __init iSeries_pci_final_fixup(void) 161{ 162 struct pci_dev *pdev = NULL; 163 struct device_node *node; 164 int DeviceCount = 0; 165 166 /* Fix up at the device node and pci_dev relationship */ 167 mf_display_src(0xC9000100); 168 169 printk("pcibios_final_fixup\n"); 170 for_each_pci_dev(pdev) { 171 node = find_Device_Node(pdev->bus->number, pdev->devfn); 172 printk("pci dev %p (%x.%x), node %p\n", pdev, 173 pdev->bus->number, pdev->devfn, node); 174 175 if (node != NULL) { 176 struct pci_dn *pdn = PCI_DN(node); 177 const u32 *agent; 178 179 agent = of_get_property(node, "linux,agent-id", NULL); 180 if ((pdn != NULL) && (agent != NULL)) { 181 u8 irq = iSeries_allocate_IRQ(pdn->busno, 0, 182 pdn->bussubno); 183 int err; 184 185 err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno, 186 *agent, irq); 187 if (err) 188 pci_Log_Error("Connect Bus Unit", 189 pdn->busno, pdn->bussubno, *agent, err); 190 else { 191 err = HvCallPci_configStore8(pdn->busno, pdn->bussubno, 192 *agent, 193 PCI_INTERRUPT_LINE, 194 irq); 195 if (err) 196 pci_Log_Error("PciCfgStore Irq Failed!", 197 pdn->busno, pdn->bussubno, *agent, err); 198 } 199 if (!err) 200 pdev->irq = irq; 201 } 202 203 ++DeviceCount; 204 pdev->sysdata = (void *)node; 205 PCI_DN(node)->pcidev = pdev; 206 allocate_device_bars(pdev); 207 iSeries_Device_Information(pdev, DeviceCount); 208 iommu_devnode_init_iSeries(pdev, node); 209 } else 210 printk("PCI: Device Tree not found for 0x%016lX\n", 211 (unsigned long)pdev); 212 } 213 iSeries_activate_IRQs(); 214 mf_display_src(0xC9000200); 215} 216 217/* 218 * Look down the chain to find the matching Device Device 219 */ 220static struct device_node *find_Device_Node(int bus, int devfn) 221{ 222 struct device_node *node; 223 224 for (node = NULL; (node = of_find_all_nodes(node)); ) { 225 struct pci_dn *pdn = PCI_DN(node); 226 227 if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn)) 228 return node; 229 } 230 return NULL; 231} 232 233 234/* 235 * Config space read and write functions. 236 * For now at least, we look for the device node for the bus and devfn 237 * that we are asked to access. It may be possible to translate the devfn 238 * to a subbus and deviceid more directly. 239 */ 240static u64 hv_cfg_read_func[4] = { 241 HvCallPciConfigLoad8, HvCallPciConfigLoad16, 242 HvCallPciConfigLoad32, HvCallPciConfigLoad32 243}; 244 245static u64 hv_cfg_write_func[4] = { 246 HvCallPciConfigStore8, HvCallPciConfigStore16, 247 HvCallPciConfigStore32, HvCallPciConfigStore32 248}; 249 250/* 251 * Read PCI config space 252 */ 253static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, 254 int offset, int size, u32 *val) 255{ 256 struct device_node *node = find_Device_Node(bus->number, devfn); 257 u64 fn; 258 struct HvCallPci_LoadReturn ret; 259 260 if (node == NULL) 261 return PCIBIOS_DEVICE_NOT_FOUND; 262 if (offset > 255) { 263 *val = ~0; 264 return PCIBIOS_BAD_REGISTER_NUMBER; 265 } 266 267 fn = hv_cfg_read_func[(size - 1) & 3]; 268 HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0); 269 270 if (ret.rc != 0) { 271 *val = ~0; 272 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */ 273 } 274 275 *val = ret.value; 276 return 0; 277} 278 279/* 280 * Write PCI config space 281 */ 282 283static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, 284 int offset, int size, u32 val) 285{ 286 struct device_node *node = find_Device_Node(bus->number, devfn); 287 u64 fn; 288 u64 ret; 289 290 if (node == NULL) 291 return PCIBIOS_DEVICE_NOT_FOUND; 292 if (offset > 255) 293 return PCIBIOS_BAD_REGISTER_NUMBER; 294 295 fn = hv_cfg_write_func[(size - 1) & 3]; 296 ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0); 297 298 if (ret != 0) 299 return PCIBIOS_DEVICE_NOT_FOUND; 300 301 return 0; 302} 303 304static struct pci_ops iSeries_pci_ops = { 305 .read = iSeries_pci_read_config, 306 .write = iSeries_pci_write_config 307}; 308 309/* 310 * Check Return Code 311 * -> On Failure, print and log information. 312 * Increment Retry Count, if exceeds max, panic partition. 313 * 314 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234 315 * PCI: Device 23.90 ReadL Retry( 1) 316 * PCI: Device 23.90 ReadL Retry Successful(1) 317 */ 318static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, 319 int *retry, u64 ret) 320{ 321 if (ret != 0) { 322 struct pci_dn *pdn = PCI_DN(DevNode); 323 324 (*retry)++; 325 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", 326 TextHdr, pdn->busno, pdn->devfn, 327 *retry, (int)ret); 328 /* 329 * Bump the retry and check for retry count exceeded. 330 * If, Exceeded, panic the system. 331 */ 332 if (((*retry) > Pci_Retry_Max) && 333 (Pci_Error_Flag > 0)) { 334 mf_display_src(0xB6000103); 335 panic_timeout = 0; 336 panic("PCI: Hardware I/O Error, SRC B6000103, " 337 "Automatic Reboot Disabled.\n"); 338 } 339 return -1; /* Retry Try */ 340 } 341 return 0; 342} 343 344/* 345 * Translate the I/O Address into a device node, bar, and bar offset. 346 * Note: Make sure the passed variable end up on the stack to avoid 347 * the exposure of being device global. 348 */ 349static inline struct device_node *xlate_iomm_address( 350 const volatile void __iomem *IoAddress, 351 u64 *dsaptr, u64 *BarOffsetPtr) 352{ 353 unsigned long OrigIoAddr; 354 unsigned long BaseIoAddr; 355 unsigned long TableIndex; 356 struct device_node *DevNode; 357 358 OrigIoAddr = (unsigned long __force)IoAddress; 359 if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory)) 360 return NULL; 361 BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY; 362 TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE; 363 DevNode = iomm_table[TableIndex]; 364 365 if (DevNode != NULL) { 366 int barnum = iobar_table[TableIndex]; 367 *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24); 368 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE; 369 } else 370 panic("PCI: Invalid PCI IoAddress detected!\n"); 371 return DevNode; 372} 373 374/* 375 * Read MM I/O Instructions for the iSeries 376 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal 377 * else, data is returned in Big Endian format. 378 */ 379static u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) 380{ 381 u64 BarOffset; 382 u64 dsa; 383 int retry = 0; 384 struct HvCallPci_LoadReturn ret; 385 struct device_node *DevNode = 386 xlate_iomm_address(IoAddress, &dsa, &BarOffset); 387 388 if (DevNode == NULL) { 389 static unsigned long last_jiffies; 390 static int num_printed; 391 392 if ((jiffies - last_jiffies) > 60 * HZ) { 393 last_jiffies = jiffies; 394 num_printed = 0; 395 } 396 if (num_printed++ < 10) 397 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", 398 IoAddress); 399 return 0xff; 400 } 401 do { 402 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); 403 } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); 404 405 return ret.value; 406} 407 408static u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) 409{ 410 u64 BarOffset; 411 u64 dsa; 412 int retry = 0; 413 struct HvCallPci_LoadReturn ret; 414 struct device_node *DevNode = 415 xlate_iomm_address(IoAddress, &dsa, &BarOffset); 416 417 if (DevNode == NULL) { 418 static unsigned long last_jiffies; 419 static int num_printed; 420 421 if ((jiffies - last_jiffies) > 60 * HZ) { 422 last_jiffies = jiffies; 423 num_printed = 0; 424 } 425 if (num_printed++ < 10) 426 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", 427 IoAddress); 428 return 0xffff; 429 } 430 do { 431 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, 432 BarOffset, 0); 433 } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); 434 435 return ret.value; 436} 437 438static u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) 439{ 440 u64 BarOffset; 441 u64 dsa; 442 int retry = 0; 443 struct HvCallPci_LoadReturn ret; 444 struct device_node *DevNode = 445 xlate_iomm_address(IoAddress, &dsa, &BarOffset); 446 447 if (DevNode == NULL) { 448 static unsigned long last_jiffies; 449 static int num_printed; 450 451 if ((jiffies - last_jiffies) > 60 * HZ) { 452 last_jiffies = jiffies; 453 num_printed = 0; 454 } 455 if (num_printed++ < 10) 456 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", 457 IoAddress); 458 return 0xffffffff; 459 } 460 do { 461 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, 462 BarOffset, 0); 463 } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); 464 465 return ret.value; 466} 467 468/* 469 * Write MM I/O Instructions for the iSeries 470 * 471 */ 472static void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) 473{ 474 u64 BarOffset; 475 u64 dsa; 476 int retry = 0; 477 u64 rc; 478 struct device_node *DevNode = 479 xlate_iomm_address(IoAddress, &dsa, &BarOffset); 480 481 if (DevNode == NULL) { 482 static unsigned long last_jiffies; 483 static int num_printed; 484 485 if ((jiffies - last_jiffies) > 60 * HZ) { 486 last_jiffies = jiffies; 487 num_printed = 0; 488 } 489 if (num_printed++ < 10) 490 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress); 491 return; 492 } 493 do { 494 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); 495 } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); 496} 497 498static void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) 499{ 500 u64 BarOffset; 501 u64 dsa; 502 int retry = 0; 503 u64 rc; 504 struct device_node *DevNode = 505 xlate_iomm_address(IoAddress, &dsa, &BarOffset); 506 507 if (DevNode == NULL) { 508 static unsigned long last_jiffies; 509 static int num_printed; 510 511 if ((jiffies - last_jiffies) > 60 * HZ) { 512 last_jiffies = jiffies; 513 num_printed = 0; 514 } 515 if (num_printed++ < 10) 516 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", 517 IoAddress); 518 return; 519 } 520 do { 521 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, data, 0); 522 } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); 523} 524 525static void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) 526{ 527 u64 BarOffset; 528 u64 dsa; 529 int retry = 0; 530 u64 rc; 531 struct device_node *DevNode = 532 xlate_iomm_address(IoAddress, &dsa, &BarOffset); 533 534 if (DevNode == NULL) { 535 static unsigned long last_jiffies; 536 static int num_printed; 537 538 if ((jiffies - last_jiffies) > 60 * HZ) { 539 last_jiffies = jiffies; 540 num_printed = 0; 541 } 542 if (num_printed++ < 10) 543 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", 544 IoAddress); 545 return; 546 } 547 do { 548 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, data, 0); 549 } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); 550} 551 552static u8 iseries_readb(const volatile void __iomem *addr) 553{ 554 return iSeries_Read_Byte(addr); 555} 556 557static u16 iseries_readw(const volatile void __iomem *addr) 558{ 559 return le16_to_cpu(iSeries_Read_Word(addr)); 560} 561 562static u32 iseries_readl(const volatile void __iomem *addr) 563{ 564 return le32_to_cpu(iSeries_Read_Long(addr)); 565} 566 567static u16 iseries_readw_be(const volatile void __iomem *addr) 568{ 569 return iSeries_Read_Word(addr); 570} 571 572static u32 iseries_readl_be(const volatile void __iomem *addr) 573{ 574 return iSeries_Read_Long(addr); 575} 576 577static void iseries_writeb(u8 data, volatile void __iomem *addr) 578{ 579 iSeries_Write_Byte(data, addr); 580} 581 582static void iseries_writew(u16 data, volatile void __iomem *addr) 583{ 584 iSeries_Write_Word(cpu_to_le16(data), addr); 585} 586 587static void iseries_writel(u32 data, volatile void __iomem *addr) 588{ 589 iSeries_Write_Long(cpu_to_le32(data), addr); 590} 591 592static void iseries_writew_be(u16 data, volatile void __iomem *addr) 593{ 594 iSeries_Write_Word(data, addr); 595} 596 597static void iseries_writel_be(u32 data, volatile void __iomem *addr) 598{ 599 iSeries_Write_Long(data, addr); 600} 601 602static void iseries_readsb(const volatile void __iomem *addr, void *buf, 603 unsigned long count) 604{ 605 u8 *dst = buf; 606 while(count-- > 0) 607 *(dst++) = iSeries_Read_Byte(addr); 608} 609 610static void iseries_readsw(const volatile void __iomem *addr, void *buf, 611 unsigned long count) 612{ 613 u16 *dst = buf; 614 while(count-- > 0) 615 *(dst++) = iSeries_Read_Word(addr); 616} 617 618static void iseries_readsl(const volatile void __iomem *addr, void *buf, 619 unsigned long count) 620{ 621 u32 *dst = buf; 622 while(count-- > 0) 623 *(dst++) = iSeries_Read_Long(addr); 624} 625 626static void iseries_writesb(volatile void __iomem *addr, const void *buf, 627 unsigned long count) 628{ 629 const u8 *src = buf; 630 while(count-- > 0) 631 iSeries_Write_Byte(*(src++), addr); 632} 633 634static void iseries_writesw(volatile void __iomem *addr, const void *buf, 635 unsigned long count) 636{ 637 const u16 *src = buf; 638 while(count-- > 0) 639 iSeries_Write_Word(*(src++), addr); 640} 641 642static void iseries_writesl(volatile void __iomem *addr, const void *buf, 643 unsigned long count) 644{ 645 const u32 *src = buf; 646 while(count-- > 0) 647 iSeries_Write_Long(*(src++), addr); 648} 649 650static void iseries_memset_io(volatile void __iomem *addr, int c, 651 unsigned long n) 652{ 653 volatile char __iomem *d = addr; 654 655 while (n-- > 0) 656 iSeries_Write_Byte(c, d++); 657} 658 659static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, 660 unsigned long n) 661{ 662 char *d = dest; 663 const volatile char __iomem *s = src; 664 665 while (n-- > 0) 666 *d++ = iSeries_Read_Byte(s++); 667} 668 669static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, 670 unsigned long n) 671{ 672 const char *s = src; 673 volatile char __iomem *d = dest; 674 675 while (n-- > 0) 676 iSeries_Write_Byte(*s++, d++); 677} 678 679/* We only set MMIO ops. The default PIO ops will be default 680 * to the MMIO ops + pci_io_base which is 0 on iSeries as 681 * expected so both should work. 682 * 683 * Note that we don't implement the readq/writeq versions as 684 * I don't know of an HV call for doing so. Thus, the default 685 * operation will be used instead, which will fault a the value 686 * return by iSeries for MMIO addresses always hits a non mapped 687 * area. This is as good as the BUG() we used to have there. 688 */ 689static struct ppc_pci_io __initdata iseries_pci_io = { 690 .readb = iseries_readb, 691 .readw = iseries_readw, 692 .readl = iseries_readl, 693 .readw_be = iseries_readw_be, 694 .readl_be = iseries_readl_be, 695 .writeb = iseries_writeb, 696 .writew = iseries_writew, 697 .writel = iseries_writel, 698 .writew_be = iseries_writew_be, 699 .writel_be = iseries_writel_be, 700 .readsb = iseries_readsb, 701 .readsw = iseries_readsw, 702 .readsl = iseries_readsl, 703 .writesb = iseries_writesb, 704 .writesw = iseries_writesw, 705 .writesl = iseries_writesl, 706 .memset_io = iseries_memset_io, 707 .memcpy_fromio = iseries_memcpy_fromio, 708 .memcpy_toio = iseries_memcpy_toio, 709}; 710 711/* 712 * iSeries_pcibios_init 713 * 714 * Description: 715 * This function checks for all possible system PCI host bridges that connect 716 * PCI buses. The system hypervisor is queried as to the guest partition 717 * ownership status. A pci_controller is built for any bus which is partially 718 * owned or fully owned by this guest partition. 719 */ 720void __init iSeries_pcibios_init(void) 721{ 722 struct pci_controller *phb; 723 struct device_node *root = of_find_node_by_path("/"); 724 struct device_node *node = NULL; 725 726 /* Install IO hooks */ 727 ppc_pci_io = iseries_pci_io; 728 729 if (root == NULL) { 730 printk(KERN_CRIT "iSeries_pcibios_init: can't find root " 731 "of device tree\n"); 732 return; 733 } 734 while ((node = of_get_next_child(root, node)) != NULL) { 735 HvBusNumber bus; 736 const u32 *busp; 737 738 if ((node->type == NULL) || (strcmp(node->type, "pci") != 0)) 739 continue; 740 741 busp = of_get_property(node, "bus-range", NULL); 742 if (busp == NULL) 743 continue; 744 bus = *busp; 745 printk("bus %d appears to exist\n", bus); 746 phb = pcibios_alloc_controller(node); 747 if (phb == NULL) 748 continue; 749 750 phb->pci_mem_offset = phb->local_number = bus; 751 phb->first_busno = bus; 752 phb->last_busno = bus; 753 phb->ops = &iSeries_pci_ops; 754 } 755 756 of_node_put(root); 757 758 pci_devs_phb_init(); 759} 760