1/* 2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10#include <linux/oprofile.h> 11#include <linux/init.h> 12#include <linux/smp.h> 13#include <asm/firmware.h> 14#include <asm/ptrace.h> 15#include <asm/system.h> 16#include <asm/processor.h> 17#include <asm/cputable.h> 18#include <asm/rtas.h> 19#include <asm/oprofile_impl.h> 20#include <asm/reg.h> 21 22#define dbg(args...) 23 24static unsigned long reset_value[OP_MAX_COUNTER]; 25 26static int oprofile_running; 27 28/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */ 29static u32 mmcr0_val; 30static u64 mmcr1_val; 31static u64 mmcra_val; 32 33static void power4_reg_setup(struct op_counter_config *ctr, 34 struct op_system_config *sys, 35 int num_ctrs) 36{ 37 int i; 38 39 /* 40 * The performance counter event settings are given in the mmcr0, 41 * mmcr1 and mmcra values passed from the user in the 42 * op_system_config structure (sys variable). 43 */ 44 mmcr0_val = sys->mmcr0; 45 mmcr1_val = sys->mmcr1; 46 mmcra_val = sys->mmcra; 47 48 for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) 49 reset_value[i] = 0x80000000UL - ctr[i].count; 50 51 /* setup user and kernel profiling */ 52 if (sys->enable_kernel) 53 mmcr0_val &= ~MMCR0_KERNEL_DISABLE; 54 else 55 mmcr0_val |= MMCR0_KERNEL_DISABLE; 56 57 if (sys->enable_user) 58 mmcr0_val &= ~MMCR0_PROBLEM_DISABLE; 59 else 60 mmcr0_val |= MMCR0_PROBLEM_DISABLE; 61} 62 63extern void ppc64_enable_pmcs(void); 64 65/* 66 * Older CPUs require the MMCRA sample bit to be always set, but newer 67 * CPUs only want it set for some groups. Eventually we will remove all 68 * knowledge of this bit in the kernel, oprofile userspace should be 69 * setting it when required. 70 * 71 * In order to keep current installations working we force the bit for 72 * those older CPUs. Once everyone has updated their oprofile userspace we 73 * can remove this hack. 74 */ 75static inline int mmcra_must_set_sample(void) 76{ 77 if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) || 78 __is_processor(PV_970) || __is_processor(PV_970FX) || 79 __is_processor(PV_970MP) || __is_processor(PV_970GX)) 80 return 1; 81 82 return 0; 83} 84 85static void power4_cpu_setup(struct op_counter_config *ctr) 86{ 87 unsigned int mmcr0 = mmcr0_val; 88 unsigned long mmcra = mmcra_val; 89 90 ppc64_enable_pmcs(); 91 92 /* set the freeze bit */ 93 mmcr0 |= MMCR0_FC; 94 mtspr(SPRN_MMCR0, mmcr0); 95 96 mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE; 97 mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE; 98 mtspr(SPRN_MMCR0, mmcr0); 99 100 mtspr(SPRN_MMCR1, mmcr1_val); 101 102 if (mmcra_must_set_sample()) 103 mmcra |= MMCRA_SAMPLE_ENABLE; 104 mtspr(SPRN_MMCRA, mmcra); 105 106 dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(), 107 mfspr(SPRN_MMCR0)); 108 dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(), 109 mfspr(SPRN_MMCR1)); 110 dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(), 111 mfspr(SPRN_MMCRA)); 112} 113 114static void power4_start(struct op_counter_config *ctr) 115{ 116 int i; 117 unsigned int mmcr0; 118 119 /* set the PMM bit (see comment below) */ 120 mtmsrd(mfmsr() | MSR_PMM); 121 122 for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { 123 if (ctr[i].enabled) { 124 classic_ctr_write(i, reset_value[i]); 125 } else { 126 classic_ctr_write(i, 0); 127 } 128 } 129 130 mmcr0 = mfspr(SPRN_MMCR0); 131 132 /* 133 * We must clear the PMAO bit on some (GQ) chips. Just do it 134 * all the time 135 */ 136 mmcr0 &= ~MMCR0_PMAO; 137 138 /* 139 * now clear the freeze bit, counting will not start until we 140 * rfid from this excetion, because only at that point will 141 * the PMM bit be cleared 142 */ 143 mmcr0 &= ~MMCR0_FC; 144 mtspr(SPRN_MMCR0, mmcr0); 145 146 oprofile_running = 1; 147 148 dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0); 149} 150 151static void power4_stop(void) 152{ 153 unsigned int mmcr0; 154 155 /* freeze counters */ 156 mmcr0 = mfspr(SPRN_MMCR0); 157 mmcr0 |= MMCR0_FC; 158 mtspr(SPRN_MMCR0, mmcr0); 159 160 oprofile_running = 0; 161 162 dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0); 163 164 mb(); 165} 166 167/* Fake functions used by canonicalize_pc */ 168static void __attribute_used__ hypervisor_bucket(void) 169{ 170} 171 172static void __attribute_used__ rtas_bucket(void) 173{ 174} 175 176static void __attribute_used__ kernel_unknown_bucket(void) 177{ 178} 179 180/* 181 * On GQ and newer the MMCRA stores the HV and PR bits at the time 182 * the SIAR was sampled. We use that to work out if the SIAR was sampled in 183 * the hypervisor, our exception vectors or RTAS. 184 */ 185static unsigned long get_pc(struct pt_regs *regs) 186{ 187 unsigned long pc = mfspr(SPRN_SIAR); 188 unsigned long mmcra; 189 190 /* Cant do much about it */ 191 if (!cur_cpu_spec->oprofile_mmcra_sihv) 192 return pc; 193 194 mmcra = mfspr(SPRN_MMCRA); 195 196 /* Were we in the hypervisor? */ 197 if (firmware_has_feature(FW_FEATURE_LPAR) && 198 (mmcra & cur_cpu_spec->oprofile_mmcra_sihv)) 199 /* function descriptor madness */ 200 return *((unsigned long *)hypervisor_bucket); 201 202 /* We were in userspace, nothing to do */ 203 if (mmcra & cur_cpu_spec->oprofile_mmcra_sipr) 204 return pc; 205 206#ifdef CONFIG_PPC_RTAS 207 /* Were we in RTAS? */ 208 if (pc >= rtas.base && pc < (rtas.base + rtas.size)) 209 /* function descriptor madness */ 210 return *((unsigned long *)rtas_bucket); 211#endif 212 213 /* Were we in our exception vectors or SLB real mode miss handler? */ 214 if (pc < 0x1000000UL) 215 return (unsigned long)__va(pc); 216 217 /* Not sure where we were */ 218 if (!is_kernel_addr(pc)) 219 /* function descriptor madness */ 220 return *((unsigned long *)kernel_unknown_bucket); 221 222 return pc; 223} 224 225static int get_kernel(unsigned long pc, unsigned long mmcra) 226{ 227 int is_kernel; 228 229 if (!cur_cpu_spec->oprofile_mmcra_sihv) { 230 is_kernel = is_kernel_addr(pc); 231 } else { 232 is_kernel = ((mmcra & cur_cpu_spec->oprofile_mmcra_sipr) == 0); 233 } 234 235 return is_kernel; 236} 237 238static void power4_handle_interrupt(struct pt_regs *regs, 239 struct op_counter_config *ctr) 240{ 241 unsigned long pc; 242 int is_kernel; 243 int val; 244 int i; 245 unsigned int mmcr0; 246 unsigned long mmcra; 247 248 mmcra = mfspr(SPRN_MMCRA); 249 250 pc = get_pc(regs); 251 is_kernel = get_kernel(pc, mmcra); 252 253 /* set the PMM bit (see comment below) */ 254 mtmsrd(mfmsr() | MSR_PMM); 255 256 for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { 257 val = classic_ctr_read(i); 258 if (val < 0) { 259 if (oprofile_running && ctr[i].enabled) { 260 oprofile_add_ext_sample(pc, regs, i, is_kernel); 261 classic_ctr_write(i, reset_value[i]); 262 } else { 263 classic_ctr_write(i, 0); 264 } 265 } 266 } 267 268 mmcr0 = mfspr(SPRN_MMCR0); 269 270 /* reset the perfmon trigger */ 271 mmcr0 |= MMCR0_PMXE; 272 273 /* 274 * We must clear the PMAO bit on some (GQ) chips. Just do it 275 * all the time 276 */ 277 mmcr0 &= ~MMCR0_PMAO; 278 279 /* Clear the appropriate bits in the MMCRA */ 280 mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear; 281 mtspr(SPRN_MMCRA, mmcra); 282 283 /* 284 * now clear the freeze bit, counting will not start until we 285 * rfid from this exception, because only at that point will 286 * the PMM bit be cleared 287 */ 288 mmcr0 &= ~MMCR0_FC; 289 mtspr(SPRN_MMCR0, mmcr0); 290} 291 292struct op_powerpc_model op_model_power4 = { 293 .reg_setup = power4_reg_setup, 294 .cpu_setup = power4_cpu_setup, 295 .start = power4_start, 296 .stop = power4_stop, 297 .handle_interrupt = power4_handle_interrupt, 298}; 299