1/* 2 * $Id: hash_low_32.S,v 1.1.1.1 2007/08/03 18:52:07 Exp $ 3 * 4 * PowerPC version 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Adapted for Power Macintosh by Paul Mackerras. 9 * Low-level exception handlers and MMU support 10 * rewritten by Paul Mackerras. 11 * Copyright (C) 1996 Paul Mackerras. 12 * 13 * This file contains low-level assembler routines for managing 14 * the PowerPC MMU hash table. (PPC 8xx processors don't use a 15 * hash table, so this file is not used on them.) 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License 19 * as published by the Free Software Foundation; either version 20 * 2 of the License, or (at your option) any later version. 21 * 22 */ 23 24#include <asm/reg.h> 25#include <asm/page.h> 26#include <asm/pgtable.h> 27#include <asm/cputable.h> 28#include <asm/ppc_asm.h> 29#include <asm/thread_info.h> 30#include <asm/asm-offsets.h> 31 32#ifdef CONFIG_SMP 33 .section .bss 34 .align 2 35 .globl mmu_hash_lock 36mmu_hash_lock: 37 .space 4 38#endif /* CONFIG_SMP */ 39 40/* 41 * Sync CPUs with hash_page taking & releasing the hash 42 * table lock 43 */ 44#ifdef CONFIG_SMP 45 .text 46_GLOBAL(hash_page_sync) 47 lis r8,mmu_hash_lock@h 48 ori r8,r8,mmu_hash_lock@l 49 lis r0,0x0fff 50 b 10f 5111: lwz r6,0(r8) 52 cmpwi 0,r6,0 53 bne 11b 5410: lwarx r6,0,r8 55 cmpwi 0,r6,0 56 bne- 11b 57 stwcx. r0,0,r8 58 bne- 10b 59 isync 60 eieio 61 li r0,0 62 stw r0,0(r8) 63 blr 64#endif 65 66/* 67 * Load a PTE into the hash table, if possible. 68 * The address is in r4, and r3 contains an access flag: 69 * _PAGE_RW (0x400) if a write. 70 * r9 contains the SRR1 value, from which we use the MSR_PR bit. 71 * SPRG3 contains the physical address of the current task's thread. 72 * 73 * Returns to the caller if the access is illegal or there is no 74 * mapping for the address. Otherwise it places an appropriate PTE 75 * in the hash table and returns from the exception. 76 * Uses r0, r3 - r8, ctr, lr. 77 */ 78 .text 79_GLOBAL(hash_page) 80 tophys(r7,0) /* gets -KERNELBASE into r7 */ 81#ifdef CONFIG_SMP 82 addis r8,r7,mmu_hash_lock@h 83 ori r8,r8,mmu_hash_lock@l 84 lis r0,0x0fff 85 b 10f 8611: lwz r6,0(r8) 87 cmpwi 0,r6,0 88 bne 11b 8910: lwarx r6,0,r8 90 cmpwi 0,r6,0 91 bne- 11b 92 stwcx. r0,0,r8 93 bne- 10b 94 isync 95#endif 96 /* Get PTE (linux-style) and check access */ 97 lis r0,KERNELBASE@h /* check if kernel address */ 98 cmplw 0,r4,r0 99 mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */ 100 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ 101 lwz r5,PGDIR(r8) /* virt page-table root */ 102 blt+ 112f /* assume user more likely */ 103 lis r5,swapper_pg_dir@ha /* if kernel address, use */ 104 addi r5,r5,swapper_pg_dir@l /* kernel page table */ 105 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ 106112: add r5,r5,r7 /* convert to phys addr */ 107 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ 108 lwz r8,0(r5) /* get pmd entry */ 109 rlwinm. r8,r8,0,0,19 /* extract address of pte page */ 110#ifdef CONFIG_SMP 111 beq- hash_page_out /* return if no mapping */ 112#else 113 beqlr- 114#endif 115 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ 116 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ 117 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE 118 119 /* 120 * Update the linux PTE atomically. We do the lwarx up-front 121 * because almost always, there won't be a permission violation 122 * and there won't already be an HPTE, and thus we will have 123 * to update the PTE to set _PAGE_HASHPTE. -- paulus. 124 */ 125retry: 126 lwarx r6,0,r8 /* get linux-style pte */ 127 andc. r5,r3,r6 /* check access & ~permission */ 128#ifdef CONFIG_SMP 129 bne- hash_page_out /* return if access not permitted */ 130#else 131 bnelr- 132#endif 133 or r5,r0,r6 /* set accessed/dirty bits */ 134 stwcx. r5,0,r8 /* attempt to update PTE */ 135 bne- retry /* retry if someone got there first */ 136 137 mfsrin r3,r4 /* get segment reg for segment */ 138 mfctr r0 139 stw r0,_CTR(r11) 140 bl create_hpte /* add the hash table entry */ 141 142#ifdef CONFIG_SMP 143 eieio 144 addis r8,r7,mmu_hash_lock@ha 145 li r0,0 146 stw r0,mmu_hash_lock@l(r8) 147#endif 148 149 /* Return from the exception */ 150 lwz r5,_CTR(r11) 151 mtctr r5 152 lwz r0,GPR0(r11) 153 lwz r7,GPR7(r11) 154 lwz r8,GPR8(r11) 155 b fast_exception_return 156 157#ifdef CONFIG_SMP 158hash_page_out: 159 eieio 160 addis r8,r7,mmu_hash_lock@ha 161 li r0,0 162 stw r0,mmu_hash_lock@l(r8) 163 blr 164#endif /* CONFIG_SMP */ 165 166/* 167 * Add an entry for a particular page to the hash table. 168 * 169 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) 170 * 171 * We assume any necessary modifications to the pte (e.g. setting 172 * the accessed bit) have already been done and that there is actually 173 * a hash table in use (i.e. we're not on a 603). 174 */ 175_GLOBAL(add_hash_page) 176 mflr r0 177 stw r0,4(r1) 178 179 /* Convert context and va to VSID */ 180 mulli r3,r3,897*16 /* multiply context by context skew */ 181 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 182 mulli r0,r0,0x111 /* multiply by ESID skew */ 183 add r3,r3,r0 /* note create_hpte trims to 24 bits */ 184 185#ifdef CONFIG_SMP 186 rlwinm r8,r1,0,0,18 /* use cpu number to make tag */ 187 lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */ 188 oris r8,r8,12 189#endif /* CONFIG_SMP */ 190 191 /* 192 * We disable interrupts here, even on UP, because we don't 193 * want to race with hash_page, and because we want the 194 * _PAGE_HASHPTE bit to be a reliable indication of whether 195 * the HPTE exists (or at least whether one did once). 196 * We also turn off the MMU for data accesses so that we 197 * we can't take a hash table miss (assuming the code is 198 * covered by a BAT). -- paulus 199 */ 200 mfmsr r10 201 SYNC 202 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 203 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 204 mtmsr r0 205 SYNC_601 206 isync 207 208 tophys(r7,0) 209 210#ifdef CONFIG_SMP 211 addis r9,r7,mmu_hash_lock@ha 212 addi r9,r9,mmu_hash_lock@l 21310: lwarx r0,0,r9 /* take the mmu_hash_lock */ 214 cmpi 0,r0,0 215 bne- 11f 216 stwcx. r8,0,r9 217 beq+ 12f 21811: lwz r0,0(r9) 219 cmpi 0,r0,0 220 beq 10b 221 b 11b 22212: isync 223#endif 224 225 /* 226 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. 227 * If _PAGE_HASHPTE was already set, we don't replace the existing 228 * HPTE, so we just unlock and return. 229 */ 230 mr r8,r5 231 rlwimi r8,r4,22,20,29 2321: lwarx r6,0,r8 233 andi. r0,r6,_PAGE_HASHPTE 234 bne 9f /* if HASHPTE already set, done */ 235 ori r5,r6,_PAGE_HASHPTE 236 stwcx. r5,0,r8 237 bne- 1b 238 239 bl create_hpte 240 2419: 242#ifdef CONFIG_SMP 243 eieio 244 li r0,0 245 stw r0,0(r9) /* clear mmu_hash_lock */ 246#endif 247 248 /* reenable interrupts and DR */ 249 mtmsr r10 250 SYNC_601 251 isync 252 253 lwz r0,4(r1) 254 mtlr r0 255 blr 256 257/* 258 * This routine adds a hardware PTE to the hash table. 259 * It is designed to be called with the MMU either on or off. 260 * r3 contains the VSID, r4 contains the virtual address, 261 * r5 contains the linux PTE, r6 contains the old value of the 262 * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the 263 * offset to be added to addresses (0 if the MMU is on, 264 * -KERNELBASE if it is off). 265 * On SMP, the caller should have the mmu_hash_lock held. 266 * We assume that the caller has (or will) set the _PAGE_HASHPTE 267 * bit in the linux PTE in memory. The value passed in r6 should 268 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set 269 * this routine will skip the search for an existing HPTE. 270 * This procedure modifies r0, r3 - r6, r8, cr0. 271 * -- paulus. 272 * 273 * For speed, 4 of the instructions get patched once the size and 274 * physical address of the hash table are known. These definitions 275 * of Hash_base and Hash_bits below are just an example. 276 */ 277Hash_base = 0xc0180000 278Hash_bits = 12 /* e.g. 256kB hash table */ 279Hash_msk = (((1 << Hash_bits) - 1) * 64) 280 281/* defines for the PTE format for 32-bit PPCs */ 282#define PTE_SIZE 8 283#define PTEG_SIZE 64 284#define LG_PTEG_SIZE 6 285#define LDPTEu lwzu 286#define LDPTE lwz 287#define STPTE stw 288#define CMPPTE cmpw 289#define PTE_H 0x40 290#define PTE_V 0x80000000 291#define TST_V(r) rlwinm. r,r,0,0,0 292#define SET_V(r) oris r,r,PTE_V@h 293#define CLR_V(r,t) rlwinm r,r,0,1,31 294 295#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) 296#define HASH_RIGHT 31-LG_PTEG_SIZE 297 298_GLOBAL(create_hpte) 299 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ 300 rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */ 301 rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ 302 and r8,r8,r0 /* writable if _RW & _DIRTY */ 303 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 304 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 305 ori r8,r8,0xe14 /* clear out reserved bits and M */ 306 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */ 307BEGIN_FTR_SECTION 308 ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */ 309END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT) 310 311 /* Construct the high word of the PPC-style PTE (r5) */ 312 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 313 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ 314 SET_V(r5) /* set V (valid) bit */ 315 316 /* Get the address of the primary PTE group in the hash table (r3) */ 317_GLOBAL(hash_page_patch_A) 318 addis r0,r7,Hash_base@h /* base address of hash table */ 319 rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 320 rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 321 xor r3,r3,r0 /* make primary hash */ 322 li r0,8 /* PTEs/group */ 323 324 /* 325 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search 326 * if it is clear, meaning that the HPTE isn't there already... 327 */ 328 andi. r6,r6,_PAGE_HASHPTE 329 beq+ 10f /* no PTE: go look for an empty slot */ 330 tlbie r4 331 332 addis r4,r7,htab_hash_searches@ha 333 lwz r6,htab_hash_searches@l(r4) 334 addi r6,r6,1 /* count how many searches we do */ 335 stw r6,htab_hash_searches@l(r4) 336 337 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 338 mtctr r0 339 addi r4,r3,-PTE_SIZE 3401: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ 341 CMPPTE 0,r6,r5 342 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 343 beq+ found_slot 344 345 /* Search the secondary PTEG for a matching PTE */ 346 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 347_GLOBAL(hash_page_patch_B) 348 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 349 xori r4,r4,(-PTEG_SIZE & 0xffff) 350 addi r4,r4,-PTE_SIZE 351 mtctr r0 3522: LDPTEu r6,PTE_SIZE(r4) 353 CMPPTE 0,r6,r5 354 bdnzf 2,2b 355 beq+ found_slot 356 xori r5,r5,PTE_H /* clear H bit again */ 357 358 /* Search the primary PTEG for an empty slot */ 35910: mtctr r0 360 addi r4,r3,-PTE_SIZE /* search primary PTEG */ 3611: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ 362 TST_V(r6) /* test valid bit */ 363 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 364 beq+ found_empty 365 366 /* update counter of times that the primary PTEG is full */ 367 addis r4,r7,primary_pteg_full@ha 368 lwz r6,primary_pteg_full@l(r4) 369 addi r6,r6,1 370 stw r6,primary_pteg_full@l(r4) 371 372 /* Search the secondary PTEG for an empty slot */ 373 ori r5,r5,PTE_H /* set H (secondary hash) bit */ 374_GLOBAL(hash_page_patch_C) 375 xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ 376 xori r4,r4,(-PTEG_SIZE & 0xffff) 377 addi r4,r4,-PTE_SIZE 378 mtctr r0 3792: LDPTEu r6,PTE_SIZE(r4) 380 TST_V(r6) 381 bdnzf 2,2b 382 beq+ found_empty 383 xori r5,r5,PTE_H /* clear H bit again */ 384 385 /* 386 * Choose an arbitrary slot in the primary PTEG to overwrite. 387 * Since both the primary and secondary PTEGs are full, and we 388 * have no information that the PTEs in the primary PTEG are 389 * more important or useful than those in the secondary PTEG, 390 * and we know there is a definite (although small) speed 391 * advantage to putting the PTE in the primary PTEG, we always 392 * put the PTE in the primary PTEG. 393 * 394 * In addition, we skip any slot that is mapping kernel text in 395 * order to avoid a deadlock when not using BAT mappings if 396 * trying to hash in the kernel hash code itself after it has 397 * already taken the hash table lock. This works in conjunction 398 * with pre-faulting of the kernel text. 399 * 400 * If the hash table bucket is full of kernel text entries, we'll 401 * lockup here but that shouldn't happen 402 */ 403 4041: addis r4,r7,next_slot@ha /* get next evict slot */ 405 lwz r6,next_slot@l(r4) 406 addi r6,r6,PTE_SIZE /* search for candidate */ 407 andi. r6,r6,7*PTE_SIZE 408 stw r6,next_slot@l(r4) 409 add r4,r3,r6 410 LDPTE r0,PTE_SIZE/2(r4) /* get PTE second word */ 411 clrrwi r0,r0,12 412 lis r6,etext@h 413 ori r6,r6,etext@l /* get etext */ 414 tophys(r6,r6) 415 cmpl cr0,r0,r6 /* compare and try again */ 416 blt 1b 417 418#ifndef CONFIG_SMP 419 /* Store PTE in PTEG */ 420found_empty: 421 STPTE r5,0(r4) 422found_slot: 423 STPTE r8,PTE_SIZE/2(r4) 424 425#else /* CONFIG_SMP */ 426/* 427 * Between the tlbie above and updating the hash table entry below, 428 * another CPU could read the hash table entry and put it in its TLB. 429 * There are 3 cases: 430 * 1. using an empty slot 431 * 2. updating an earlier entry to change permissions (i.e. enable write) 432 * 3. taking over the PTE for an unrelated address 433 * 434 * In each case it doesn't really matter if the other CPUs have the old 435 * PTE in their TLB. So we don't need to bother with another tlbie here, 436 * which is convenient as we've overwritten the register that had the 437 * address. :-) The tlbie above is mainly to make sure that this CPU comes 438 * and gets the new PTE from the hash table. 439 * 440 * We do however have to make sure that the PTE is never in an invalid 441 * state with the V bit set. 442 */ 443found_empty: 444found_slot: 445 CLR_V(r5,r0) /* clear V (valid) bit in PTE */ 446 STPTE r5,0(r4) 447 sync 448 TLBSYNC 449 STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ 450 sync 451 SET_V(r5) 452 STPTE r5,0(r4) /* finally set V bit in PTE */ 453#endif /* CONFIG_SMP */ 454 455 sync /* make sure pte updates get to memory */ 456 blr 457 458 .section .bss 459 .align 2 460next_slot: 461 .space 4 462primary_pteg_full: 463 .space 4 464htab_hash_searches: 465 .space 4 466 .previous 467 468/* 469 * Flush the entry for a particular page from the hash table. 470 * 471 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, 472 * int count) 473 * 474 * We assume that there is a hash table in use (Hash != 0). 475 */ 476_GLOBAL(flush_hash_pages) 477 tophys(r7,0) 478 479 /* 480 * We disable interrupts here, even on UP, because we want 481 * the _PAGE_HASHPTE bit to be a reliable indication of 482 * whether the HPTE exists (or at least whether one did once). 483 * We also turn off the MMU for data accesses so that we 484 * we can't take a hash table miss (assuming the code is 485 * covered by a BAT). -- paulus 486 */ 487 mfmsr r10 488 SYNC 489 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 490 rlwinm r0,r0,0,28,26 /* clear MSR_DR */ 491 mtmsr r0 492 SYNC_601 493 isync 494 495 /* First find a PTE in the range that has _PAGE_HASHPTE set */ 496 rlwimi r5,r4,22,20,29 4971: lwz r0,0(r5) 498 cmpwi cr1,r6,1 499 andi. r0,r0,_PAGE_HASHPTE 500 bne 2f 501 ble cr1,19f 502 addi r4,r4,0x1000 503 addi r5,r5,4 504 addi r6,r6,-1 505 b 1b 506 507 /* Convert context and va to VSID */ 5082: mulli r3,r3,897*16 /* multiply context by context skew */ 509 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ 510 mulli r0,r0,0x111 /* multiply by ESID skew */ 511 add r3,r3,r0 /* note code below trims to 24 bits */ 512 513 /* Construct the high word of the PPC-style PTE (r11) */ 514 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ 515 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ 516 SET_V(r11) /* set V (valid) bit */ 517 518#ifdef CONFIG_SMP 519 addis r9,r7,mmu_hash_lock@ha 520 addi r9,r9,mmu_hash_lock@l 521 rlwinm r8,r1,0,0,18 522 add r8,r8,r7 523 lwz r8,TI_CPU(r8) 524 oris r8,r8,9 52510: lwarx r0,0,r9 526 cmpi 0,r0,0 527 bne- 11f 528 stwcx. r8,0,r9 529 beq+ 12f 53011: lwz r0,0(r9) 531 cmpi 0,r0,0 532 beq 10b 533 b 11b 53412: isync 535#endif 536 537 /* 538 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is 539 * already clear, we're done (for this pte). If not, 540 * clear it (atomically) and proceed. -- paulus. 541 */ 54233: lwarx r8,0,r5 /* fetch the pte */ 543 andi. r0,r8,_PAGE_HASHPTE 544 beq 8f /* done if HASHPTE is already clear */ 545 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ 546 stwcx. r8,0,r5 /* update the pte */ 547 bne- 33b 548 549 /* Get the address of the primary PTE group in the hash table (r3) */ 550_GLOBAL(flush_hash_patch_A) 551 addis r8,r7,Hash_base@h /* base address of hash table */ 552 rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ 553 rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ 554 xor r8,r0,r8 /* make primary hash */ 555 556 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ 557 li r0,8 /* PTEs/group */ 558 mtctr r0 559 addi r12,r8,-PTE_SIZE 5601: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */ 561 CMPPTE 0,r0,r11 562 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ 563 beq+ 3f 564 565 /* Search the secondary PTEG for a matching PTE */ 566 ori r11,r11,PTE_H /* set H (secondary hash) bit */ 567 li r0,8 /* PTEs/group */ 568_GLOBAL(flush_hash_patch_B) 569 xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ 570 xori r12,r12,(-PTEG_SIZE & 0xffff) 571 addi r12,r12,-PTE_SIZE 572 mtctr r0 5732: LDPTEu r0,PTE_SIZE(r12) 574 CMPPTE 0,r0,r11 575 bdnzf 2,2b 576 xori r11,r11,PTE_H /* clear H again */ 577 bne- 4f /* should rarely fail to find it */ 578 5793: li r0,0 580 STPTE r0,0(r12) /* invalidate entry */ 5814: sync 582 tlbie r4 /* in hw tlb too */ 583 sync 584 5858: ble cr1,9f /* if all ptes checked */ 58681: addi r6,r6,-1 587 addi r5,r5,4 /* advance to next pte */ 588 addi r4,r4,0x1000 589 lwz r0,0(r5) /* check next pte */ 590 cmpwi cr1,r6,1 591 andi. r0,r0,_PAGE_HASHPTE 592 bne 33b 593 bgt cr1,81b 594 5959: 596#ifdef CONFIG_SMP 597 TLBSYNC 598 li r0,0 599 stw r0,0(r9) /* clear mmu_hash_lock */ 600#endif 601 60219: mtmsr r10 603 SYNC_601 604 isync 605 blr 606