1/* $Id: pci.c,v 1.1.1.1 2007/08/03 18:52:03 Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1997, 1998 Ralf Baechle 8 * Copyright (C) 1999 SuSE GmbH 9 * Copyright (C) 1999-2001 Hewlett-Packard Company 10 * Copyright (C) 1999-2001 Grant Grundler 11 */ 12#include <linux/eisa.h> 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/pci.h> 17#include <linux/slab.h> 18#include <linux/types.h> 19 20#include <asm/io.h> 21#include <asm/system.h> 22#include <asm/cache.h> /* for L1_CACHE_BYTES */ 23#include <asm/superio.h> 24 25#define DEBUG_RESOURCES 0 26#define DEBUG_CONFIG 0 27 28#if DEBUG_CONFIG 29# define DBGC(x...) printk(KERN_DEBUG x) 30#else 31# define DBGC(x...) 32#endif 33 34 35#if DEBUG_RESOURCES 36#define DBG_RES(x...) printk(KERN_DEBUG x) 37#else 38#define DBG_RES(x...) 39#endif 40 41/* To be used as: mdelay(pci_post_reset_delay); 42 * 43 * post_reset is the time the kernel should stall to prevent anyone from 44 * accessing the PCI bus once #RESET is de-asserted. 45 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 46 * this makes the boot time much longer than necessary. 47 * 20ms seems to work for all the HP PCI implementations to date. 48 * 49 * #define pci_post_reset_delay 50 50 */ 51 52struct pci_port_ops *pci_port __read_mostly; 53struct pci_bios_ops *pci_bios __read_mostly; 54 55static int pci_hba_count __read_mostly; 56 57/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */ 58#define PCI_HBA_MAX 32 59static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly; 60 61 62/******************************************************************** 63** 64** I/O port space support 65** 66*********************************************************************/ 67 68/* EISA port numbers and PCI port numbers share the same interface. Some 69 * machines have both EISA and PCI adapters installed. Rather than turn 70 * pci_port into an array, we reserve bus 0 for EISA and call the EISA 71 * routines if the access is to a port on bus 0. We don't want to fix 72 * EISA and ISA drivers which assume port space is <= 0xffff. 73 */ 74 75#ifdef CONFIG_EISA 76#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr) 77#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr) 78#else 79#define EISA_IN(size) 80#define EISA_OUT(size) 81#endif 82 83#define PCI_PORT_IN(type, size) \ 84u##size in##type (int addr) \ 85{ \ 86 int b = PCI_PORT_HBA(addr); \ 87 EISA_IN(size); \ 88 if (!parisc_pci_hba[b]) return (u##size) -1; \ 89 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \ 90} \ 91EXPORT_SYMBOL(in##type); 92 93PCI_PORT_IN(b, 8) 94PCI_PORT_IN(w, 16) 95PCI_PORT_IN(l, 32) 96 97 98#define PCI_PORT_OUT(type, size) \ 99void out##type (u##size d, int addr) \ 100{ \ 101 int b = PCI_PORT_HBA(addr); \ 102 EISA_OUT(size); \ 103 if (!parisc_pci_hba[b]) return; \ 104 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \ 105} \ 106EXPORT_SYMBOL(out##type); 107 108PCI_PORT_OUT(b, 8) 109PCI_PORT_OUT(w, 16) 110PCI_PORT_OUT(l, 32) 111 112 113 114/* 115 * BIOS32 replacement. 116 */ 117static int __init pcibios_init(void) 118{ 119 if (!pci_bios) 120 return -1; 121 122 if (pci_bios->init) { 123 pci_bios->init(); 124 } else { 125 printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); 126 } 127 return 0; 128} 129 130 131/* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */ 132void pcibios_fixup_bus(struct pci_bus *bus) 133{ 134 if (pci_bios->fixup_bus) { 135 pci_bios->fixup_bus(bus); 136 } else { 137 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n"); 138 } 139} 140 141 142char *pcibios_setup(char *str) 143{ 144 return str; 145} 146 147/* 148 * Called by pci_set_master() - a driver interface. 149 * 150 * Legacy PDC guarantees to set: 151 * Map Memory BAR's into PA IO space. 152 * Map Expansion ROM BAR into one common PA IO space per bus. 153 * Map IO BAR's into PCI IO space. 154 * Command (see below) 155 * Cache Line Size 156 * Latency Timer 157 * Interrupt Line 158 * PPB: secondary latency timer, io/mmio base/limit, 159 * bus numbers, bridge control 160 * 161 */ 162void pcibios_set_master(struct pci_dev *dev) 163{ 164 u8 lat; 165 166 /* If someone already mucked with this, don't touch it. */ 167 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 168 if (lat >= 16) return; 169 170 /* 171 ** HP generally has fewer devices on the bus than other architectures. 172 ** upper byte is PCI_LATENCY_TIMER. 173 */ 174 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 175 (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32))); 176} 177 178 179void __init pcibios_init_bus(struct pci_bus *bus) 180{ 181 struct pci_dev *dev = bus->self; 182 unsigned short bridge_ctl; 183 184 /* We deal only with pci controllers and pci-pci bridges. */ 185 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 186 return; 187 188 /* PCI-PCI bridge - set the cache line and default latency 189 (32) for primary and secondary buses. */ 190 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); 191 192 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); 193 bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 194 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); 195} 196 197 198/* KLUGE: Link the child and parent resources - generic PCI didn't */ 199static void 200pcibios_link_hba_resources( struct resource *hba_res, struct resource *r) 201{ 202 if (!r->parent) { 203 printk(KERN_EMERG "PCI: resource not parented! [%p-%p]\n", 204 (void*) r->start, (void*) r->end); 205 r->parent = hba_res; 206 207 /* reverse link is harder *sigh* */ 208 if (r->parent->child) { 209 if (r->parent->sibling) { 210 struct resource *next = r->parent->sibling; 211 while (next->sibling) 212 next = next->sibling; 213 next->sibling = r; 214 } else { 215 r->parent->sibling = r; 216 } 217 } else 218 r->parent->child = r; 219 } 220} 221 222/* called by drivers/pci/setup-bus.c:pci_setup_bridge(). */ 223void __devinit pcibios_resource_to_bus(struct pci_dev *dev, 224 struct pci_bus_region *region, struct resource *res) 225{ 226 struct pci_bus *bus = dev->bus; 227 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data); 228 229 if (res->flags & IORESOURCE_IO) { 230 region->start = PCI_PORT_ADDR(res->start); 231 region->end = PCI_PORT_ADDR(res->end); 232 } else if (res->flags & IORESOURCE_MEM) { 233 /* Convert MMIO addr to PCI addr (undo global virtualization) */ 234 region->start = PCI_BUS_ADDR(hba, res->start); 235 region->end = PCI_BUS_ADDR(hba, res->end); 236 } 237 238 DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n", 239 bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM", 240 region->start, region->end); 241 242 /* KLUGE ALERT 243 ** if this resource isn't linked to a "parent", then it seems 244 ** to be a child of the HBA - lets link it in. 245 */ 246 pcibios_link_hba_resources(&hba->io_space, bus->resource[0]); 247 pcibios_link_hba_resources(&hba->lmmio_space, bus->resource[1]); 248} 249 250void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 251 struct pci_bus_region *region) 252{ 253#ifdef CONFIG_64BIT 254 struct pci_bus *bus = dev->bus; 255 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data); 256#endif 257 258 if (res->flags & IORESOURCE_MEM) { 259 res->start = PCI_HOST_ADDR(hba, region->start); 260 res->end = PCI_HOST_ADDR(hba, region->end); 261 } 262 263 if (res->flags & IORESOURCE_IO) { 264 res->start = region->start; 265 res->end = region->end; 266 } 267} 268 269#ifdef CONFIG_HOTPLUG 270EXPORT_SYMBOL(pcibios_resource_to_bus); 271EXPORT_SYMBOL(pcibios_bus_to_resource); 272#endif 273 274/* 275 * pcibios align resources() is called every time generic PCI code 276 * wants to generate a new address. The process of looking for 277 * an available address, each candidate is first "aligned" and 278 * then checked if the resource is available until a match is found. 279 * 280 * Since we are just checking candidates, don't use any fields other 281 * than res->start. 282 */ 283void pcibios_align_resource(void *data, struct resource *res, 284 resource_size_t size, resource_size_t alignment) 285{ 286 resource_size_t mask, align; 287 288 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n", 289 pci_name(((struct pci_dev *) data)), 290 res->parent, res->start, res->end, 291 (int) res->flags, size, alignment); 292 293 /* If it's not IO, then it's gotta be MEM */ 294 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 295 296 /* Align to largest of MIN or input size */ 297 mask = max(alignment, align) - 1; 298 res->start += mask; 299 res->start &= ~mask; 300 301 /* The caller updates the end field, we don't. */ 302} 303 304 305/* 306 * A driver is enabling the device. We make sure that all the appropriate 307 * bits are set to allow the device to operate as the driver is expecting. 308 * We enable the port IO and memory IO bits if the device has any BARs of 309 * that type, and we enable the PERR and SERR bits unconditionally. 310 * Drivers that do not need parity (eg graphics and possibly networking) 311 * can clear these bits if they want. 312 */ 313int pcibios_enable_device(struct pci_dev *dev, int mask) 314{ 315 u16 cmd; 316 int idx; 317 318 pci_read_config_word(dev, PCI_COMMAND, &cmd); 319 320 for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) { 321 struct resource *r = &dev->resource[idx]; 322 323 /* only setup requested resources */ 324 if (!(mask & (1<<idx))) 325 continue; 326 327 if (r->flags & IORESOURCE_IO) 328 cmd |= PCI_COMMAND_IO; 329 if (r->flags & IORESOURCE_MEM) 330 cmd |= PCI_COMMAND_MEMORY; 331 } 332 333 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 334 335 DBGC("PCIBIOS: Enabling device %s cmd 0x%04x\n", pci_name(dev), cmd); 336 pci_write_config_word(dev, PCI_COMMAND, cmd); 337 return 0; 338} 339 340 341/* PA-RISC specific */ 342void pcibios_register_hba(struct pci_hba_data *hba) 343{ 344 if (pci_hba_count >= PCI_HBA_MAX) { 345 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n"); 346 return; 347 } 348 349 parisc_pci_hba[pci_hba_count] = hba; 350 hba->hba_num = pci_hba_count++; 351} 352 353subsys_initcall(pcibios_init); 354