1/* 2 * Code to handle x86 style IRQs plus some generic interrupt stuff. 3 * 4 * Copyright (C) 1992 Linus Torvalds 5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle 6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) 7 * Copyright (C) 1999-2000 Grant Grundler 8 * Copyright (c) 2005 Matthew Wilcox 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24#include <linux/bitops.h> 25#include <linux/errno.h> 26#include <linux/init.h> 27#include <linux/interrupt.h> 28#include <linux/kernel_stat.h> 29#include <linux/seq_file.h> 30#include <linux/spinlock.h> 31#include <linux/types.h> 32#include <asm/io.h> 33 34#include <asm/smp.h> 35 36#undef PARISC_IRQ_CR16_COUNTS 37 38extern irqreturn_t timer_interrupt(int, void *); 39extern irqreturn_t ipi_interrupt(int, void *); 40 41#define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq)) 42 43/* Bits in EIEM correlate with cpu_irq_action[]. 44** Numbered *Big Endian*! (ie bit 0 is MSB) 45*/ 46static volatile unsigned long cpu_eiem = 0; 47 48/* 49** local ACK bitmap ... habitually set to 1, but reset to zero 50** between ->ack() and ->end() of the interrupt to prevent 51** re-interruption of a processing interrupt. 52*/ 53static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; 54 55static void cpu_disable_irq(unsigned int irq) 56{ 57 unsigned long eirr_bit = EIEM_MASK(irq); 58 59 cpu_eiem &= ~eirr_bit; 60 /* Do nothing on the other CPUs. If they get this interrupt, 61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't 62 * handle it, and the set_eiem() at the bottom will ensure it 63 * then gets disabled */ 64} 65 66static void cpu_enable_irq(unsigned int irq) 67{ 68 unsigned long eirr_bit = EIEM_MASK(irq); 69 70 cpu_eiem |= eirr_bit; 71 72 /* This is just a simple NOP IPI. But what it does is cause 73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end 74 * of the interrupt handler */ 75 smp_send_all_nop(); 76} 77 78static unsigned int cpu_startup_irq(unsigned int irq) 79{ 80 cpu_enable_irq(irq); 81 return 0; 82} 83 84void no_ack_irq(unsigned int irq) { } 85void no_end_irq(unsigned int irq) { } 86 87void cpu_ack_irq(unsigned int irq) 88{ 89 unsigned long mask = EIEM_MASK(irq); 90 int cpu = smp_processor_id(); 91 92 /* Clear in EIEM so we can no longer process */ 93 per_cpu(local_ack_eiem, cpu) &= ~mask; 94 95 /* disable the interrupt */ 96 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 97 98 /* and now ack it */ 99 mtctl(mask, 23); 100} 101 102void cpu_end_irq(unsigned int irq) 103{ 104 unsigned long mask = EIEM_MASK(irq); 105 int cpu = smp_processor_id(); 106 107 /* set it in the eiems---it's no longer in process */ 108 per_cpu(local_ack_eiem, cpu) |= mask; 109 110 /* enable the interrupt */ 111 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 112} 113 114#ifdef CONFIG_SMP 115int cpu_check_affinity(unsigned int irq, cpumask_t *dest) 116{ 117 int cpu_dest; 118 119 /* timer and ipi have to always be received on all CPUs */ 120 if (CHECK_IRQ_PER_CPU(irq)) { 121 /* Bad linux design decision. The mask has already 122 * been set; we must reset it */ 123 irq_desc[irq].affinity = CPU_MASK_ALL; 124 return -EINVAL; 125 } 126 127 /* whatever mask they set, we just allow one CPU */ 128 cpu_dest = first_cpu(*dest); 129 *dest = cpumask_of_cpu(cpu_dest); 130 131 return 0; 132} 133 134static void cpu_set_affinity_irq(unsigned int irq, cpumask_t dest) 135{ 136 if (cpu_check_affinity(irq, &dest)) 137 return; 138 139 irq_desc[irq].affinity = dest; 140} 141#endif 142 143static struct hw_interrupt_type cpu_interrupt_type = { 144 .typename = "CPU", 145 .startup = cpu_startup_irq, 146 .shutdown = cpu_disable_irq, 147 .enable = cpu_enable_irq, 148 .disable = cpu_disable_irq, 149 .ack = cpu_ack_irq, 150 .end = cpu_end_irq, 151#ifdef CONFIG_SMP 152 .set_affinity = cpu_set_affinity_irq, 153#endif 154 .retrigger = NULL, 155}; 156 157int show_interrupts(struct seq_file *p, void *v) 158{ 159 int i = *(loff_t *) v, j; 160 unsigned long flags; 161 162 if (i == 0) { 163 seq_puts(p, " "); 164 for_each_online_cpu(j) 165 seq_printf(p, " CPU%d", j); 166 167#ifdef PARISC_IRQ_CR16_COUNTS 168 seq_printf(p, " [min/avg/max] (CPU cycle counts)"); 169#endif 170 seq_putc(p, '\n'); 171 } 172 173 if (i < NR_IRQS) { 174 struct irqaction *action; 175 176 spin_lock_irqsave(&irq_desc[i].lock, flags); 177 action = irq_desc[i].action; 178 if (!action) 179 goto skip; 180 seq_printf(p, "%3d: ", i); 181#ifdef CONFIG_SMP 182 for_each_online_cpu(j) 183 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 184#else 185 seq_printf(p, "%10u ", kstat_irqs(i)); 186#endif 187 188 seq_printf(p, " %14s", irq_desc[i].chip->typename); 189#ifndef PARISC_IRQ_CR16_COUNTS 190 seq_printf(p, " %s", action->name); 191 192 while ((action = action->next)) 193 seq_printf(p, ", %s", action->name); 194#else 195 for ( ;action; action = action->next) { 196 unsigned int k, avg, min, max; 197 198 min = max = action->cr16_hist[0]; 199 200 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { 201 int hist = action->cr16_hist[k]; 202 203 if (hist) { 204 avg += hist; 205 } else 206 break; 207 208 if (hist > max) max = hist; 209 if (hist < min) min = hist; 210 } 211 212 avg /= k; 213 seq_printf(p, " %s[%d/%d/%d]", action->name, 214 min,avg,max); 215 } 216#endif 217 218 seq_putc(p, '\n'); 219 skip: 220 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 221 } 222 223 return 0; 224} 225 226 227 228/* 229** The following form a "set": Virtual IRQ, Transaction Address, Trans Data. 230** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit. 231** 232** To use txn_XXX() interfaces, get a Virtual IRQ first. 233** Then use that to get the Transaction address and data. 234*/ 235 236int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) 237{ 238 if (irq_desc[irq].action) 239 return -EBUSY; 240 if (irq_desc[irq].chip != &cpu_interrupt_type) 241 return -EBUSY; 242 243 if (type) { 244 irq_desc[irq].chip = type; 245 irq_desc[irq].chip_data = data; 246 cpu_interrupt_type.enable(irq); 247 } 248 return 0; 249} 250 251int txn_claim_irq(int irq) 252{ 253 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq; 254} 255 256/* 257 * The bits_wide parameter accommodates the limitations of the HW/SW which 258 * use these bits: 259 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) 260 * V-class (EPIC): 6 bits 261 * N/L/A-class (iosapic): 8 bits 262 * PCI 2.2 MSI: 16 bits 263 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric) 264 * 265 * On the service provider side: 266 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register) 267 * o PA 2.0 wide mode 6-bits (per processor) 268 * o IA64 8-bits (0-256 total) 269 * 270 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported 271 * by the processor...and the N/L-class I/O subsystem supports more bits than 272 * PA2.0 has. The first case is the problem. 273 */ 274int txn_alloc_irq(unsigned int bits_wide) 275{ 276 int irq; 277 278 /* never return irq 0 cause that's the interval timer */ 279 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) { 280 if (cpu_claim_irq(irq, NULL, NULL) < 0) 281 continue; 282 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide)) 283 continue; 284 return irq; 285 } 286 287 /* unlikely, but be prepared */ 288 return -1; 289} 290 291 292unsigned long txn_affinity_addr(unsigned int irq, int cpu) 293{ 294#ifdef CONFIG_SMP 295 irq_desc[irq].affinity = cpumask_of_cpu(cpu); 296#endif 297 298 return cpu_data[cpu].txn_addr; 299} 300 301 302unsigned long txn_alloc_addr(unsigned int virt_irq) 303{ 304 static int next_cpu = -1; 305 306 next_cpu++; /* assign to "next" CPU we want this bugger on */ 307 308 /* validate entry */ 309 while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr || 310 !cpu_online(next_cpu))) 311 next_cpu++; 312 313 if (next_cpu >= NR_CPUS) 314 next_cpu = 0; /* nothing else, assign monarch */ 315 316 return txn_affinity_addr(virt_irq, next_cpu); 317} 318 319 320unsigned int txn_alloc_data(unsigned int virt_irq) 321{ 322 return virt_irq - CPU_IRQ_BASE; 323} 324 325static inline int eirr_to_irq(unsigned long eirr) 326{ 327 int bit = fls_long(eirr); 328 return (BITS_PER_LONG - bit) + TIMER_IRQ; 329} 330 331/* ONLY called from entry.S:intr_extint() */ 332void do_cpu_irq_mask(struct pt_regs *regs) 333{ 334 struct pt_regs *old_regs; 335 unsigned long eirr_val; 336 int irq, cpu = smp_processor_id(); 337#ifdef CONFIG_SMP 338 cpumask_t dest; 339#endif 340 341 old_regs = set_irq_regs(regs); 342 local_irq_disable(); 343 irq_enter(); 344 345 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu); 346 if (!eirr_val) 347 goto set_out; 348 irq = eirr_to_irq(eirr_val); 349 350#ifdef CONFIG_SMP 351 dest = irq_desc[irq].affinity; 352 if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && 353 !cpu_isset(smp_processor_id(), dest)) { 354 int cpu = first_cpu(dest); 355 356 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", 357 irq, smp_processor_id(), cpu); 358 gsc_writel(irq + CPU_IRQ_BASE, 359 cpu_data[cpu].hpa); 360 goto set_out; 361 } 362#endif 363 __do_IRQ(irq); 364 365 out: 366 irq_exit(); 367 set_irq_regs(old_regs); 368 return; 369 370 set_out: 371 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 372 goto out; 373} 374 375static struct irqaction timer_action = { 376 .handler = timer_interrupt, 377 .name = "timer", 378 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL, 379}; 380 381#ifdef CONFIG_SMP 382static struct irqaction ipi_action = { 383 .handler = ipi_interrupt, 384 .name = "IPI", 385 .flags = IRQF_DISABLED | IRQF_PERCPU, 386}; 387#endif 388 389static void claim_cpu_irqs(void) 390{ 391 int i; 392 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { 393 irq_desc[i].chip = &cpu_interrupt_type; 394 } 395 396 irq_desc[TIMER_IRQ].action = &timer_action; 397 irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU; 398#ifdef CONFIG_SMP 399 irq_desc[IPI_IRQ].action = &ipi_action; 400 irq_desc[IPI_IRQ].status = IRQ_PER_CPU; 401#endif 402} 403 404void __init init_IRQ(void) 405{ 406 local_irq_disable(); /* PARANOID - should already be disabled */ 407 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ 408 claim_cpu_irqs(); 409#ifdef CONFIG_SMP 410 if (!cpu_eiem) 411 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ); 412#else 413 cpu_eiem = EIEM_MASK(TIMER_IRQ); 414#endif 415 set_eiem(cpu_eiem); /* EIEM : enable all external intr */ 416 417} 418 419void ack_bad_irq(unsigned int irq) 420{ 421 printk("unexpected IRQ %d\n", irq); 422} 423