1/* 2 * Copyright (C) 2000, 2001 Broadcom Corporation 3 * 4 * Copyright (C) 2002 MontaVista Software Inc. 5 * Author: jsun@mvista.com or jsun@junsun.net 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 */ 13#include <linux/bcd.h> 14#include <linux/types.h> 15#include <linux/time.h> 16 17#include <asm/time.h> 18#include <asm/addrspace.h> 19#include <asm/io.h> 20 21#include <asm/sibyte/sb1250.h> 22#include <asm/sibyte/sb1250_regs.h> 23#include <asm/sibyte/sb1250_smbus.h> 24 25 26/* M41T81 definitions */ 27 28/* 29 * Register bits 30 */ 31 32#define M41T81REG_SC_ST 0x80 /* stop bit */ 33#define M41T81REG_HR_CB 0x40 /* century bit */ 34#define M41T81REG_HR_CEB 0x80 /* century enable bit */ 35#define M41T81REG_CTL_S 0x20 /* sign bit */ 36#define M41T81REG_CTL_FT 0x40 /* frequency test bit */ 37#define M41T81REG_CTL_OUT 0x80 /* output level */ 38#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */ 39#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */ 40#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */ 41#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */ 42#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */ 43#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */ 44#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */ 45#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */ 46#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */ 47#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */ 48#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */ 49#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */ 50#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */ 51#define M41T81REG_AHR_HT 0x40 /* halt update bit */ 52#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */ 53#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */ 54#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */ 55#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */ 56#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */ 57#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */ 58#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */ 59#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */ 60 61 62/* 63 * Register numbers 64 */ 65 66#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */ 67#define M41T81REG_SC 0x01 /* seconds */ 68#define M41T81REG_MN 0x02 /* minute */ 69#define M41T81REG_HR 0x03 /* hour/century */ 70#define M41T81REG_DY 0x04 /* day of week */ 71#define M41T81REG_DT 0x05 /* date of month */ 72#define M41T81REG_MO 0x06 /* month */ 73#define M41T81REG_YR 0x07 /* year */ 74#define M41T81REG_CTL 0x08 /* control */ 75#define M41T81REG_WD 0x09 /* watchdog */ 76#define M41T81REG_AMO 0x0A /* alarm: month */ 77#define M41T81REG_ADT 0x0B /* alarm: date */ 78#define M41T81REG_AHR 0x0C /* alarm: hour */ 79#define M41T81REG_AMN 0x0D /* alarm: minute */ 80#define M41T81REG_ASC 0x0E /* alarm: second */ 81#define M41T81REG_FLG 0x0F /* flags */ 82#define M41T81REG_SQW 0x13 /* square wave register */ 83 84#define M41T81_CCR_ADDRESS 0x68 85 86#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) 87 88static int m41t81_read(uint8_t addr) 89{ 90 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 91 ; 92 93 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); 94 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, 95 SMB_CSR(R_SMB_START)); 96 97 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 98 ; 99 100 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, 101 SMB_CSR(R_SMB_START)); 102 103 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 104 ; 105 106 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 107 /* Clear error bit by writing a 1 */ 108 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 109 return -1; 110 } 111 112 return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); 113} 114 115static int m41t81_write(uint8_t addr, int b) 116{ 117 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 118 ; 119 120 __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); 121 __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); 122 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, 123 SMB_CSR(R_SMB_START)); 124 125 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 126 ; 127 128 if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { 129 /* Clear error bit by writing a 1 */ 130 __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 131 return -1; 132 } 133 134 /* read the same byte again to make sure it is written */ 135 __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, 136 SMB_CSR(R_SMB_START)); 137 138 while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 139 ; 140 141 return 0; 142} 143 144int m41t81_set_time(unsigned long t) 145{ 146 struct rtc_time tm; 147 unsigned long flags; 148 149 to_tm(t, &tm); 150 151 /* 152 * Note the write order matters as it ensures the correctness. 153 * When we write sec, 10th sec is clear. It is reasonable to 154 * believe we should finish writing min within a second. 155 */ 156 157 spin_lock_irqsave(&rtc_lock, flags); 158 tm.tm_sec = BIN2BCD(tm.tm_sec); 159 m41t81_write(M41T81REG_SC, tm.tm_sec); 160 161 tm.tm_min = BIN2BCD(tm.tm_min); 162 m41t81_write(M41T81REG_MN, tm.tm_min); 163 164 tm.tm_hour = BIN2BCD(tm.tm_hour); 165 tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0); 166 m41t81_write(M41T81REG_HR, tm.tm_hour); 167 168 /* tm_wday starts from 0 to 6 */ 169 if (tm.tm_wday == 0) tm.tm_wday = 7; 170 tm.tm_wday = BIN2BCD(tm.tm_wday); 171 m41t81_write(M41T81REG_DY, tm.tm_wday); 172 173 tm.tm_mday = BIN2BCD(tm.tm_mday); 174 m41t81_write(M41T81REG_DT, tm.tm_mday); 175 176 /* tm_mon starts from 0, *ick* */ 177 tm.tm_mon ++; 178 tm.tm_mon = BIN2BCD(tm.tm_mon); 179 m41t81_write(M41T81REG_MO, tm.tm_mon); 180 181 /* we don't do century, everything is beyond 2000 */ 182 tm.tm_year %= 100; 183 tm.tm_year = BIN2BCD(tm.tm_year); 184 m41t81_write(M41T81REG_YR, tm.tm_year); 185 spin_unlock_irqrestore(&rtc_lock, flags); 186 187 return 0; 188} 189 190unsigned long m41t81_get_time(void) 191{ 192 unsigned int year, mon, day, hour, min, sec; 193 unsigned long flags; 194 195 /* 196 * min is valid if two reads of sec are the same. 197 */ 198 for (;;) { 199 spin_lock_irqsave(&rtc_lock, flags); 200 sec = m41t81_read(M41T81REG_SC); 201 min = m41t81_read(M41T81REG_MN); 202 if (sec == m41t81_read(M41T81REG_SC)) break; 203 spin_unlock_irqrestore(&rtc_lock, flags); 204 } 205 hour = m41t81_read(M41T81REG_HR) & 0x3f; 206 day = m41t81_read(M41T81REG_DT); 207 mon = m41t81_read(M41T81REG_MO); 208 year = m41t81_read(M41T81REG_YR); 209 spin_unlock_irqrestore(&rtc_lock, flags); 210 211 sec = BCD2BIN(sec); 212 min = BCD2BIN(min); 213 hour = BCD2BIN(hour); 214 day = BCD2BIN(day); 215 mon = BCD2BIN(mon); 216 year = BCD2BIN(year); 217 218 year += 2000; 219 220 return mktime(year, mon, day, hour, min, sec); 221} 222 223int m41t81_probe(void) 224{ 225 unsigned int tmp; 226 227 /* enable chip if it is not enabled yet */ 228 tmp = m41t81_read(M41T81REG_SC); 229 m41t81_write(M41T81REG_SC, tmp & 0x7f); 230 231 return (m41t81_read(M41T81REG_SC) != -1); 232} 233