1/*
2 * BRIEF MODULE DESCRIPTION
3 *	Alchemy/AMD Au1x00 pci support.
4 *
5 * Copyright 2001,2002,2003 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 *         	ppopov@mvista.com or source@mvista.com
8 *
9 *  Support for all devices (greater than 16) added by David Gathright.
10 *
11 *  This program is free software; you can redistribute  it and/or modify it
12 *  under  the terms of  the GNU General  Public License as published by the
13 *  Free Software Foundation;  either version 2 of the  License, or (at your
14 *  option) any later version.
15 *
16 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
17 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
18 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
19 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
20 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
22 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
24 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 *  You should have received a copy of the  GNU General Public License along
28 *  with this program; if not, write  to the Free Software Foundation, Inc.,
29 *  675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/vmalloc.h>
36
37#include <asm/mach-au1x00/au1000.h>
38
39#undef DEBUG
40#ifdef DEBUG
41#define DBG(x...) printk(x)
42#else
43#define DBG(x...)
44#endif
45
46#define PCI_ACCESS_READ  0
47#define PCI_ACCESS_WRITE 1
48
49
50int (*board_pci_idsel)(unsigned int devsel, int assert);
51
52void mod_wired_entry(int entry, unsigned long entrylo0,
53		unsigned long entrylo1, unsigned long entryhi,
54		unsigned long pagemask)
55{
56	unsigned long old_pagemask;
57	unsigned long old_ctx;
58
59	/* Save old context and create impossible VPN2 value */
60	old_ctx = read_c0_entryhi() & 0xff;
61	old_pagemask = read_c0_pagemask();
62	write_c0_index(entry);
63	write_c0_pagemask(pagemask);
64	write_c0_entryhi(entryhi);
65	write_c0_entrylo0(entrylo0);
66	write_c0_entrylo1(entrylo1);
67	tlb_write_indexed();
68	write_c0_entryhi(old_ctx);
69	write_c0_pagemask(old_pagemask);
70}
71
72struct vm_struct *pci_cfg_vm;
73static int pci_cfg_wired_entry;
74static int first_cfg = 1;
75unsigned long last_entryLo0, last_entryLo1;
76
77static int config_access(unsigned char access_type, struct pci_bus *bus,
78			 unsigned int dev_fn, unsigned char where,
79			 u32 * data)
80{
81#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
82	unsigned int device = PCI_SLOT(dev_fn);
83	unsigned int function = PCI_FUNC(dev_fn);
84	unsigned long offset, status;
85	unsigned long cfg_base;
86	unsigned long flags;
87	int error = PCIBIOS_SUCCESSFUL;
88	unsigned long entryLo0, entryLo1;
89
90	if (device > 19) {
91		*data = 0xffffffff;
92		return -1;
93	}
94
95	local_irq_save(flags);
96	au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
97			Au1500_PCI_STATCMD);
98	au_sync_udelay(1);
99
100	/*
101	 * We can't ioremap the entire pci config space because it's
102	 * too large. Nor can we call ioremap dynamically because some
103	 * device drivers use the pci config routines from within
104	 * interrupt handlers and that becomes a problem in get_vm_area().
105	 * We use one wired tlb to handle all config accesses for all
106	 * busses. To improve performance, if the current device
107	 * is the same as the last device accessed, we don't touch the
108	 * tlb.
109	 */
110	if (first_cfg) {
111		/* reserve a wired entry for pci config accesses */
112		first_cfg = 0;
113		pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
114		if (!pci_cfg_vm)
115			panic (KERN_ERR "PCI unable to get vm area\n");
116		pci_cfg_wired_entry = read_c0_wired();
117		add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
118		last_entryLo0  = last_entryLo1 = 0xffffffff;
119	}
120
121	/* Allow board vendors to implement their own off-chip idsel.
122	 * If it doesn't succeed, may as well bail out at this point.
123	 */
124	if (board_pci_idsel) {
125		if (board_pci_idsel(device, 1) == 0) {
126			*data = 0xffffffff;
127			local_irq_restore(flags);
128			return -1;
129		}
130	}
131
132        /* setup the config window */
133        if (bus->number == 0) {
134                cfg_base = ((1<<device)<<11);
135        } else {
136                cfg_base = 0x80000000 | (bus->number<<16) | (device<<11);
137        }
138
139        /* setup the lower bits of the 36 bit address */
140        offset = (function << 8) | (where & ~0x3);
141	/* pick up any address that falls below the page mask */
142	offset |= cfg_base & ~PAGE_MASK;
143
144	/* page boundary */
145	cfg_base = cfg_base & PAGE_MASK;
146
147	entryLo0 = (6 << 26)  | (cfg_base >> 6) | (2 << 3) | 7;
148	entryLo1 = (6 << 26)  | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
149
150	if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
151		mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
152				(unsigned long)pci_cfg_vm->addr, PM_4K);
153		last_entryLo0 = entryLo0;
154		last_entryLo1 = entryLo1;
155	}
156
157	if (access_type == PCI_ACCESS_WRITE) {
158		au_writel(*data, (int)(pci_cfg_vm->addr + offset));
159	} else {
160		*data = au_readl((int)(pci_cfg_vm->addr + offset));
161	}
162	au_sync_udelay(2);
163
164	DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n",
165			access_type, bus->number, device, where, *data, offset);
166
167	/* check master abort */
168	status = au_readl(Au1500_PCI_STATCMD);
169
170	if (status & (1<<29)) {
171		*data = 0xffffffff;
172		error = -1;
173		DBG("Au1x Master Abort\n");
174	} else if ((status >> 28) & 0xf) {
175		DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf));
176
177		/* clear errors */
178		au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
179
180		*data = 0xffffffff;
181		error = -1;
182	}
183
184	/* Take away the idsel.
185	*/
186	if (board_pci_idsel) {
187		(void)board_pci_idsel(device, 0);
188	}
189
190	local_irq_restore(flags);
191	return error;
192#endif
193}
194
195static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
196			    int where, u8 * val)
197{
198	u32 data;
199	int ret;
200
201	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
202	if (where & 1)
203		data >>= 8;
204	if (where & 2)
205		data >>= 16;
206	*val = data & 0xff;
207	return ret;
208}
209
210
211static int read_config_word(struct pci_bus *bus, unsigned int devfn,
212			    int where, u16 * val)
213{
214	u32 data;
215	int ret;
216
217	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
218	if (where & 2)
219		data >>= 16;
220	*val = data & 0xffff;
221	return ret;
222}
223
224static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
225			     int where, u32 * val)
226{
227	int ret;
228
229	ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
230	return ret;
231}
232
233static int
234write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
235		  u8 val)
236{
237	u32 data = 0;
238
239	if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
240		return -1;
241
242	data = (data & ~(0xff << ((where & 3) << 3))) |
243	    (val << ((where & 3) << 3));
244
245	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
246		return -1;
247
248	return PCIBIOS_SUCCESSFUL;
249}
250
251static int
252write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
253		  u16 val)
254{
255	u32 data = 0;
256
257	if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
258		return -1;
259
260	data = (data & ~(0xffff << ((where & 3) << 3))) |
261	    (val << ((where & 3) << 3));
262
263	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
264		return -1;
265
266
267	return PCIBIOS_SUCCESSFUL;
268}
269
270static int
271write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
272		   u32 val)
273{
274	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
275		return -1;
276
277	return PCIBIOS_SUCCESSFUL;
278}
279
280static int config_read(struct pci_bus *bus, unsigned int devfn,
281		       int where, int size, u32 * val)
282{
283	switch (size) {
284	case 1: {
285			u8 _val;
286			int rc = read_config_byte(bus, devfn, where, &_val);
287			*val = _val;
288			return rc;
289		}
290       case 2: {
291			u16 _val;
292			int rc = read_config_word(bus, devfn, where, &_val);
293			*val = _val;
294			return rc;
295		}
296	default:
297		return read_config_dword(bus, devfn, where, val);
298	}
299}
300
301static int config_write(struct pci_bus *bus, unsigned int devfn,
302			int where, int size, u32 val)
303{
304	switch (size) {
305	case 1:
306		return write_config_byte(bus, devfn, where, (u8) val);
307	case 2:
308		return write_config_word(bus, devfn, where, (u16) val);
309	default:
310		return write_config_dword(bus, devfn, where, val);
311	}
312}
313
314
315struct pci_ops au1x_pci_ops = {
316	config_read,
317	config_write
318};
319