1/* 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. 3 * All rights reserved. 4 * Authors: Carsten Langgaard <carstenl@mips.com> 5 * Maciej W. Rozycki <macro@mips.com> 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 20 * PROM library initialisation code. 21 */ 22#include <linux/init.h> 23#include <linux/string.h> 24#include <linux/kernel.h> 25 26#include <asm/bootinfo.h> 27#include <asm/gt64120.h> 28#include <asm/io.h> 29#include <asm/system.h> 30#include <asm/cacheflush.h> 31#include <asm/traps.h> 32 33#include <asm/mips-boards/prom.h> 34#include <asm/mips-boards/generic.h> 35#include <asm/mips-boards/bonito64.h> 36#include <asm/mips-boards/msc01_pci.h> 37 38#include <asm/mips-boards/malta.h> 39 40#ifdef CONFIG_KGDB 41extern int rs_kgdb_hook(int, int); 42extern int rs_putDebugChar(char); 43extern char rs_getDebugChar(void); 44extern int saa9730_kgdb_hook(int); 45extern int saa9730_putDebugChar(char); 46extern char saa9730_getDebugChar(void); 47#endif 48 49int prom_argc; 50int *_prom_argv, *_prom_envp; 51 52/* 53 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. 54 * This macro take care of sign extension, if running in 64-bit mode. 55 */ 56#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) 57 58int init_debug = 0; 59 60int mips_revision_corid; 61int mips_revision_sconid; 62 63/* Bonito64 system controller register base. */ 64unsigned long _pcictrl_bonito; 65unsigned long _pcictrl_bonito_pcicfg; 66 67/* GT64120 system controller register base */ 68unsigned long _pcictrl_gt64120; 69 70/* MIPS System controller register base */ 71unsigned long _pcictrl_msc; 72 73char *prom_getenv(char *envname) 74{ 75 /* 76 * Return a pointer to the given environment variable. 77 * In 64-bit mode: we're using 64-bit pointers, but all pointers 78 * in the PROM structures are only 32-bit, so we need some 79 * workarounds, if we are running in 64-bit mode. 80 */ 81 int i, index=0; 82 83 i = strlen(envname); 84 85 while (prom_envp(index)) { 86 if(strncmp(envname, prom_envp(index), i) == 0) { 87 return(prom_envp(index+1)); 88 } 89 index += 2; 90 } 91 92 return NULL; 93} 94 95static inline unsigned char str2hexnum(unsigned char c) 96{ 97 if (c >= '0' && c <= '9') 98 return c - '0'; 99 if (c >= 'a' && c <= 'f') 100 return c - 'a' + 10; 101 return 0; /* foo */ 102} 103 104static inline void str2eaddr(unsigned char *ea, unsigned char *str) 105{ 106 int i; 107 108 for (i = 0; i < 6; i++) { 109 unsigned char num; 110 111 if((*str == '.') || (*str == ':')) 112 str++; 113 num = str2hexnum(*str++) << 4; 114 num |= (str2hexnum(*str++)); 115 ea[i] = num; 116 } 117} 118 119int get_ethernet_addr(char *ethernet_addr) 120{ 121 char *ethaddr_str; 122 123 ethaddr_str = prom_getenv("ethaddr"); 124 if (!ethaddr_str) { 125 printk("ethaddr not set in boot prom\n"); 126 return -1; 127 } 128 str2eaddr(ethernet_addr, ethaddr_str); 129 130 if (init_debug > 1) { 131 int i; 132 printk("get_ethernet_addr: "); 133 for (i=0; i<5; i++) 134 printk("%02x:", (unsigned char)*(ethernet_addr+i)); 135 printk("%02x\n", *(ethernet_addr+i)); 136 } 137 138 return 0; 139} 140 141#ifdef CONFIG_SERIAL_8250_CONSOLE 142static void __init console_config(void) 143{ 144 char console_string[40]; 145 int baud = 0; 146 char parity = '\0', bits = '\0', flow = '\0'; 147 char *s; 148 149 if ((strstr(prom_getcmdline(), "console=")) == NULL) { 150 s = prom_getenv("modetty0"); 151 if (s) { 152 while (*s >= '0' && *s <= '9') 153 baud = baud*10 + *s++ - '0'; 154 if (*s == ',') s++; 155 if (*s) parity = *s++; 156 if (*s == ',') s++; 157 if (*s) bits = *s++; 158 if (*s == ',') s++; 159 if (*s == 'h') flow = 'r'; 160 } 161 if (baud == 0) 162 baud = 38400; 163 if (parity != 'n' && parity != 'o' && parity != 'e') 164 parity = 'n'; 165 if (bits != '7' && bits != '8') 166 bits = '8'; 167 if (flow == '\0') 168 flow = 'r'; 169 sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 170 strcat (prom_getcmdline(), console_string); 171 pr_info("Config serial console:%s\n", console_string); 172 } 173} 174#endif 175 176#ifdef CONFIG_KGDB 177void __init kgdb_config (void) 178{ 179 extern int (*generic_putDebugChar)(char); 180 extern char (*generic_getDebugChar)(void); 181 char *argptr; 182 int line, speed; 183 184 argptr = prom_getcmdline(); 185 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { 186 argptr += strlen("kgdb=ttyS"); 187 if (*argptr != '0' && *argptr != '1') 188 printk("KGDB: Unknown serial line /dev/ttyS%c, " 189 "falling back to /dev/ttyS1\n", *argptr); 190 line = *argptr == '0' ? 0 : 1; 191 printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); 192 193 speed = 0; 194 if (*++argptr == ',') 195 { 196 int c; 197 while ((c = *++argptr) && ('0' <= c && c <= '9')) 198 speed = speed * 10 + c - '0'; 199 } 200#ifdef CONFIG_MIPS_ATLAS 201 if (line == 1) { 202 speed = saa9730_kgdb_hook(speed); 203 generic_putDebugChar = saa9730_putDebugChar; 204 generic_getDebugChar = saa9730_getDebugChar; 205 } 206 else 207#endif 208 { 209 speed = rs_kgdb_hook(line, speed); 210 generic_putDebugChar = rs_putDebugChar; 211 generic_getDebugChar = rs_getDebugChar; 212 } 213 214 pr_info("KGDB: Using serial line /dev/ttyS%d at %d for " 215 "session, please connect your debugger\n", 216 line ? 1 : 0, speed); 217 218 { 219 char *s; 220 for (s = "Please connect GDB to this port\r\n"; *s; ) 221 generic_putDebugChar (*s++); 222 } 223 224 /* Breakpoint is invoked after interrupts are initialised */ 225 } 226} 227#endif 228 229void __init mips_nmi_setup (void) 230{ 231 void *base; 232 extern char except_vec_nmi; 233 234 base = cpu_has_veic ? 235 (void *)(CAC_BASE + 0xa80) : 236 (void *)(CAC_BASE + 0x380); 237 memcpy(base, &except_vec_nmi, 0x80); 238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 239} 240 241void __init mips_ejtag_setup (void) 242{ 243 void *base; 244 extern char except_vec_ejtag_debug; 245 246 base = cpu_has_veic ? 247 (void *)(CAC_BASE + 0xa00) : 248 (void *)(CAC_BASE + 0x300); 249 memcpy(base, &except_vec_ejtag_debug, 0x80); 250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 251} 252 253void __init prom_init(void) 254{ 255 prom_argc = fw_arg0; 256 _prom_argv = (int *) fw_arg1; 257 _prom_envp = (int *) fw_arg2; 258 259 mips_display_message("LINUX"); 260 261#ifdef CONFIG_MIPS_SEAD 262 set_io_port_base(KSEG1); 263#else 264 /* 265 * early setup of _pcictrl_bonito so that we can determine 266 * the system controller on a CORE_EMUL board 267 */ 268 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); 269 270 mips_revision_corid = MIPS_REVISION_CORID; 271 272 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 273 if (BONITO_PCIDID == 0x0001df53 || 274 BONITO_PCIDID == 0x0003df53) 275 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 276 else 277 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; 278 } 279 280 mips_revision_sconid = MIPS_REVISION_SCONID; 281 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { 282 switch (mips_revision_corid) { 283 case MIPS_REVISION_CORID_QED_RM5261: 284 case MIPS_REVISION_CORID_CORE_LV: 285 case MIPS_REVISION_CORID_CORE_FPGA: 286 case MIPS_REVISION_CORID_CORE_FPGAR2: 287 mips_revision_sconid = MIPS_REVISION_SCON_GT64120; 288 break; 289 case MIPS_REVISION_CORID_CORE_EMUL_BON: 290 case MIPS_REVISION_CORID_BONITO64: 291 case MIPS_REVISION_CORID_CORE_20K: 292 mips_revision_sconid = MIPS_REVISION_SCON_BONITO; 293 break; 294 case MIPS_REVISION_CORID_CORE_MSC: 295 case MIPS_REVISION_CORID_CORE_FPGA2: 296 case MIPS_REVISION_CORID_CORE_FPGA3: 297 case MIPS_REVISION_CORID_CORE_24K: 298 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 299 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; 300 break; 301 default: 302 mips_display_message("CC Error"); 303 while (1); /* We die here... */ 304 } 305 } 306 307 switch (mips_revision_sconid) { 308 u32 start, map, mask, data; 309 310 case MIPS_REVISION_SCON_GT64120: 311 /* 312 * Setup the North bridge to do Master byte-lane swapping 313 * when running in bigendian. 314 */ 315 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); 316 317#ifdef CONFIG_CPU_LITTLE_ENDIAN 318 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | 319 GT_PCI0_CMD_SBYTESWAP_BIT); 320#else 321 GT_WRITE(GT_PCI0_CMD_OFS, 0); 322#endif 323 /* Fix up PCI I/O mapping if necessary (for Atlas). */ 324 start = GT_READ(GT_PCI0IOLD_OFS); 325 map = GT_READ(GT_PCI0IOREMAP_OFS); 326 if ((start & map) != 0) { 327 map &= ~start; 328 GT_WRITE(GT_PCI0IOREMAP_OFS, map); 329 } 330 331 set_io_port_base(MALTA_GT_PORT_BASE); 332 break; 333 334 case MIPS_REVISION_SCON_BONITO: 335 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); 336 337 /* 338 * Disable Bonito IOBC. 339 */ 340 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 341 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 342 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 343 344 /* 345 * Setup the North bridge to do Master byte-lane swapping 346 * when running in bigendian. 347 */ 348#ifdef CONFIG_CPU_LITTLE_ENDIAN 349 BONITO_BONGENCFG = BONITO_BONGENCFG & 350 ~(BONITO_BONGENCFG_MSTRBYTESWAP | 351 BONITO_BONGENCFG_BYTESWAP); 352#else 353 BONITO_BONGENCFG = BONITO_BONGENCFG | 354 BONITO_BONGENCFG_MSTRBYTESWAP | 355 BONITO_BONGENCFG_BYTESWAP; 356#endif 357 358 set_io_port_base(MALTA_BONITO_PORT_BASE); 359 break; 360 361 case MIPS_REVISION_SCON_SOCIT: 362 case MIPS_REVISION_SCON_ROCIT: 363 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 364 mips_pci_controller: 365 mb(); 366 MSC_READ(MSC01_PCI_CFG, data); 367 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); 368 wmb(); 369 370 /* Fix up lane swapping. */ 371#ifdef CONFIG_CPU_LITTLE_ENDIAN 372 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 373#else 374 MSC_WRITE(MSC01_PCI_SWAP, 375 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | 376 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 377 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 378#endif 379 /* Fix up target memory mapping. */ 380 MSC_READ(MSC01_PCI_BAR0, mask); 381 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 382 383 /* Don't handle target retries indefinitely. */ 384 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 385 MSC01_PCI_CFG_MAXRTRY_MSK) 386 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << 387 MSC01_PCI_CFG_MAXRTRY_SHF)) | 388 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << 389 MSC01_PCI_CFG_MAXRTRY_SHF); 390 391 wmb(); 392 MSC_WRITE(MSC01_PCI_CFG, data); 393 mb(); 394 395 set_io_port_base(MALTA_MSC_PORT_BASE); 396 break; 397 398 case MIPS_REVISION_SCON_SOCITSC: 399 case MIPS_REVISION_SCON_SOCITSCP: 400 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); 401 goto mips_pci_controller; 402 403 default: 404 /* Unknown system controller */ 405 mips_display_message("SC Error"); 406 while (1); /* We die here... */ 407 } 408#endif 409 board_nmi_handler_setup = mips_nmi_setup; 410 board_ejtag_handler_setup = mips_ejtag_setup; 411 412 pr_info("\nLINUX started...\n"); 413 prom_init_cmdline(); 414 prom_meminit(); 415#ifdef CONFIG_SERIAL_8250_CONSOLE 416 console_config(); 417#endif 418} 419