1/*
2 * This program is free software; you can redistribute  it and/or modify it
3 * under  the terms of  the GNU General  Public License as published by the
4 * Free Software Foundation;  either version 2 of the  License, or (at your
5 * option) any later version.
6 *
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com
9 *
10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
11 */
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/sched.h>
16#include <linux/kernel_stat.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/msc01_ic.h>
20
21static unsigned long _icctrl_msc;
22#define MSC01_IC_REG_BASE	_icctrl_msc
23
24#define MSCIC_WRITE(reg, data)	do { *(volatile u32 *)(reg) = data; } while (0)
25#define MSCIC_READ(reg, data)	do { data = *(volatile u32 *)(reg); } while (0)
26
27static unsigned int irq_base;
28
29/* mask off an interrupt */
30static inline void mask_msc_irq(unsigned int irq)
31{
32	if (irq < (irq_base + 32))
33		MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
34	else
35		MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
36}
37
38/* unmask an interrupt */
39static inline void unmask_msc_irq(unsigned int irq)
40{
41	if (irq < (irq_base + 32))
42		MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
43	else
44		MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
45}
46
47/*
48 * Masks and ACKs an IRQ
49 */
50static void level_mask_and_ack_msc_irq(unsigned int irq)
51{
52	mask_msc_irq(irq);
53	if (!cpu_has_veic)
54		MSCIC_WRITE(MSC01_IC_EOI, 0);
55#ifdef CONFIG_MIPS_MT_SMTC
56	/* This actually needs to be a call into platform code */
57	if (irq_hwmask[irq] & ST0_IM)
58		set_c0_status(irq_hwmask[irq] & ST0_IM);
59#endif /* CONFIG_MIPS_MT_SMTC */
60}
61
62/*
63 * Masks and ACKs an IRQ
64 */
65static void edge_mask_and_ack_msc_irq(unsigned int irq)
66{
67	mask_msc_irq(irq);
68	if (!cpu_has_veic)
69		MSCIC_WRITE(MSC01_IC_EOI, 0);
70	else {
71		u32 r;
72		MSCIC_READ(MSC01_IC_SUP+irq*8, r);
73		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
74		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
75	}
76#ifdef CONFIG_MIPS_MT_SMTC
77	if (irq_hwmask[irq] & ST0_IM)
78		set_c0_status(irq_hwmask[irq] & ST0_IM);
79#endif /* CONFIG_MIPS_MT_SMTC */
80}
81
82/*
83 * End IRQ processing
84 */
85static void end_msc_irq(unsigned int irq)
86{
87	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
88		unmask_msc_irq(irq);
89}
90
91/*
92 * Interrupt handler for interrupts coming from SOC-it.
93 */
94void ll_msc_irq(void)
95{
96 	unsigned int irq;
97
98	/* read the interrupt vector register */
99	MSCIC_READ(MSC01_IC_VEC, irq);
100	if (irq < 64)
101		do_IRQ(irq + irq_base);
102	else {
103		/* Ignore spurious interrupt */
104	}
105}
106
107void
108msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
109{
110	MSCIC_WRITE(MSC01_IC_RAMW,
111		    (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
112}
113
114struct irq_chip msc_levelirq_type = {
115	.name = "SOC-it-Level",
116	.ack = level_mask_and_ack_msc_irq,
117	.mask = mask_msc_irq,
118	.mask_ack = level_mask_and_ack_msc_irq,
119	.unmask = unmask_msc_irq,
120	.eoi = unmask_msc_irq,
121	.end = end_msc_irq,
122};
123
124struct irq_chip msc_edgeirq_type = {
125	.name = "SOC-it-Edge",
126	.ack = edge_mask_and_ack_msc_irq,
127	.mask = mask_msc_irq,
128	.mask_ack = edge_mask_and_ack_msc_irq,
129	.unmask = unmask_msc_irq,
130	.eoi = unmask_msc_irq,
131	.end = end_msc_irq,
132};
133
134
135void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
136{
137	extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
138
139	_icctrl_msc = (unsigned long) ioremap (icubase, 0x40000);
140
141	/* Reset interrupt controller - initialises all registers to 0 */
142	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
143
144	board_bind_eic_interrupt = &msc_bind_eic_interrupt;
145
146	for (; nirq >= 0; nirq--, imp++) {
147		int n = imp->im_irq;
148
149		switch (imp->im_type) {
150		case MSC01_IRQ_EDGE:
151			set_irq_chip(irqbase+n, &msc_edgeirq_type);
152			if (cpu_has_veic)
153				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
154			else
155				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
156			break;
157		case MSC01_IRQ_LEVEL:
158			set_irq_chip(irqbase+n, &msc_levelirq_type);
159			if (cpu_has_veic)
160				MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
161			else
162				MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
163		}
164	}
165
166	irq_base = irqbase;
167
168	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);	/* Enable interrupt generation */
169
170}
171