1/*********************************************************************** 2 * 3 * Copyright 2001 MontaVista Software Inc. 4 * Author: jsun@mvista.com or jsun@junsun.net 5 * 6 * arch/mips/ddb5xxx/ddb5477/debug.c 7 * vrc5477 specific debug routines. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 *********************************************************************** 15 */ 16 17#include <linux/kernel.h> 18 19#include <asm/mipsregs.h> 20#include <asm/ddb5xxx/ddb5xxx.h> 21 22typedef struct { 23 const char *regname; 24 unsigned regaddr; 25} Register; 26 27void jsun_show_regs(char *name, Register *regs) 28{ 29 int i; 30 31 printk("\nshow regs: %s\n", name); 32 for(i=0;regs[i].regname!= NULL; i++) { 33 printk("%-16s= %08x\t\t(@%08x)\n", 34 regs[i].regname, 35 *(unsigned *)(regs[i].regaddr), 36 regs[i].regaddr); 37 } 38} 39 40static Register int_regs[] = { 41 {"DDB_INTCTRL0", DDB_BASE + DDB_INTCTRL0}, 42 {"DDB_INTCTRL1", DDB_BASE + DDB_INTCTRL1}, 43 {"DDB_INTCTRL2", DDB_BASE + DDB_INTCTRL2}, 44 {"DDB_INTCTRL3", DDB_BASE + DDB_INTCTRL3}, 45 {"DDB_INT0STAT", DDB_BASE + DDB_INT0STAT}, 46 {"DDB_INT1STAT", DDB_BASE + DDB_INT1STAT}, 47 {"DDB_INT2STAT", DDB_BASE + DDB_INT2STAT}, 48 {"DDB_INT3STAT", DDB_BASE + DDB_INT3STAT}, 49 {"DDB_INT4STAT", DDB_BASE + DDB_INT4STAT}, 50 {"DDB_NMISTAT", DDB_BASE + DDB_NMISTAT}, 51 {"DDB_INTPPES0", DDB_BASE + DDB_INTPPES0}, 52 {"DDB_INTPPES1", DDB_BASE + DDB_INTPPES1}, 53 {NULL, 0x0} 54}; 55 56void vrc5477_show_int_regs() 57{ 58 jsun_show_regs("interrupt registers", int_regs); 59 printk("CPU CAUSE = %08x\n", read_c0_cause()); 60 printk("CPU STATUS = %08x\n", read_c0_status()); 61} 62static Register pdar_regs[] = { 63 {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0}, 64 {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1}, 65 {"DDB_LCS0", DDB_BASE + DDB_LCS0}, 66 {"DDB_LCS1", DDB_BASE + DDB_LCS1}, 67 {"DDB_LCS2", DDB_BASE + DDB_LCS2}, 68 {"DDB_INTCS", DDB_BASE + DDB_INTCS}, 69 {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS}, 70 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0}, 71 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1}, 72 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0}, 73 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1}, 74 {NULL, 0x0} 75}; 76void vrc5477_show_pdar_regs(void) 77{ 78 jsun_show_regs("PDAR regs", pdar_regs); 79} 80 81static Register bar_regs[] = { 82 {"DDB_BARC0", DDB_BASE + DDB_BARC0}, 83 {"DDB_BARM010", DDB_BASE + DDB_BARM010}, 84 {"DDB_BARM230", DDB_BASE + DDB_BARM230}, 85 {"DDB_BAR00", DDB_BASE + DDB_BAR00}, 86 {"DDB_BAR10", DDB_BASE + DDB_BAR10}, 87 {"DDB_BAR20", DDB_BASE + DDB_BAR20}, 88 {"DDB_BAR30", DDB_BASE + DDB_BAR30}, 89 {"DDB_BAR40", DDB_BASE + DDB_BAR40}, 90 {"DDB_BAR50", DDB_BASE + DDB_BAR50}, 91 {"DDB_BARB0", DDB_BASE + DDB_BARB0}, 92 {"DDB_BARC1", DDB_BASE + DDB_BARC1}, 93 {"DDB_BARM011", DDB_BASE + DDB_BARM011}, 94 {"DDB_BARM231", DDB_BASE + DDB_BARM231}, 95 {"DDB_BAR01", DDB_BASE + DDB_BAR01}, 96 {"DDB_BAR11", DDB_BASE + DDB_BAR11}, 97 {"DDB_BAR21", DDB_BASE + DDB_BAR21}, 98 {"DDB_BAR31", DDB_BASE + DDB_BAR31}, 99 {"DDB_BAR41", DDB_BASE + DDB_BAR41}, 100 {"DDB_BAR51", DDB_BASE + DDB_BAR51}, 101 {"DDB_BARB1", DDB_BASE + DDB_BARB1}, 102 {NULL, 0x0} 103}; 104void vrc5477_show_bar_regs(void) 105{ 106 jsun_show_regs("BAR regs", bar_regs); 107} 108 109static Register pci_regs[] = { 110 {"DDB_PCIW0", DDB_BASE + DDB_PCIW0}, 111 {"DDB_PCIW1", DDB_BASE + DDB_PCIW1}, 112 {"DDB_PCIINIT00", DDB_BASE + DDB_PCIINIT00}, 113 {"DDB_PCIINIT10", DDB_BASE + DDB_PCIINIT10}, 114 {"DDB_PCICTL0_L", DDB_BASE + DDB_PCICTL0_L}, 115 {"DDB_PCICTL0_H", DDB_BASE + DDB_PCICTL0_H}, 116 {"DDB_PCIARB0_L", DDB_BASE + DDB_PCIARB0_L}, 117 {"DDB_PCIARB0_H", DDB_BASE + DDB_PCIARB0_H}, 118 {"DDB_PCISWP0", DDB_BASE + DDB_PCISWP0}, 119 {"DDB_PCIERR0", DDB_BASE + DDB_PCIERR0}, 120 {"DDB_IOPCIW0", DDB_BASE + DDB_IOPCIW0}, 121 {"DDB_IOPCIW1", DDB_BASE + DDB_IOPCIW1}, 122 {"DDB_PCIINIT01", DDB_BASE + DDB_PCIINIT01}, 123 {"DDB_PCIINIT11", DDB_BASE + DDB_PCIINIT11}, 124 {"DDB_PCICTL1_L", DDB_BASE + DDB_PCICTL1_L}, 125 {"DDB_PCICTL1_H", DDB_BASE + DDB_PCICTL1_H}, 126 {"DDB_PCIARB1_L", DDB_BASE + DDB_PCIARB1_L}, 127 {"DDB_PCIARB1_H", DDB_BASE + DDB_PCIARB1_H}, 128 {"DDB_PCISWP1", DDB_BASE + DDB_PCISWP1}, 129 {"DDB_PCIERR1", DDB_BASE + DDB_PCIERR1}, 130 {NULL, 0x0} 131}; 132void vrc5477_show_pci_regs(void) 133{ 134 jsun_show_regs("PCI regs", pci_regs); 135} 136 137static Register lb_regs[] = { 138 {"DDB_LCNFG", DDB_BASE + DDB_LCNFG}, 139 {"DDB_LCST0", DDB_BASE + DDB_LCST0}, 140 {"DDB_LCST1", DDB_BASE + DDB_LCST1}, 141 {"DDB_LCST2", DDB_BASE + DDB_LCST2}, 142 {"DDB_ERRADR", DDB_BASE + DDB_ERRADR}, 143 {"DDB_ERRCS", DDB_BASE + DDB_ERRCS}, 144 {"DDB_BTM", DDB_BASE + DDB_BTM}, 145 {"DDB_BCST", DDB_BASE + DDB_BCST}, 146 {NULL, 0x0} 147}; 148void vrc5477_show_lb_regs(void) 149{ 150 jsun_show_regs("Local Bus regs", lb_regs); 151} 152 153void vrc5477_show_all_regs(void) 154{ 155 vrc5477_show_pdar_regs(); 156 vrc5477_show_pci_regs(); 157 vrc5477_show_bar_regs(); 158 vrc5477_show_int_regs(); 159 vrc5477_show_lb_regs(); 160} 161