1/* 2 * Copyright 2002 MontaVista Software Inc. 3 * Author: MontaVista Software, Inc. 4 * ppopov@mvista.com or source@mvista.com 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 * 22 * You should have received a copy of the GNU General Public License along 23 * with this program; if not, write to the Free Software Foundation, Inc., 24 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 */ 26#include <linux/init.h> 27#include <linux/sched.h> 28#include <linux/ioport.h> 29#include <linux/mm.h> 30#include <linux/console.h> 31#include <linux/delay.h> 32 33#include <asm/cpu.h> 34#include <asm/bootinfo.h> 35#include <asm/irq.h> 36#include <asm/mipsregs.h> 37#include <asm/reboot.h> 38#include <asm/pgtable.h> 39#include <asm/mach-au1x00/au1000.h> 40#include <asm/mach-pb1x00/pb1100.h> 41 42void board_reset (void) 43{ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 45 au_writel(0x00000000, 0xAE00001C); 46} 47 48void __init board_setup(void) 49{ 50 volatile void __iomem * base = (volatile void __iomem *) 0xac000000UL; 51 52 // set AUX clock to 12MHz * 8 = 96 MHz 53 au_writel(8, SYS_AUXPLL); 54 au_writel(0, SYS_PININPUTEN); 55 udelay(100); 56 57#ifdef CONFIG_USB_OHCI 58 { 59 u32 pin_func, sys_freqctrl, sys_clksrc; 60 61 // configure pins GPIO[14:9] as GPIO 62 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80); 63 64 /* zero and disable FREQ2 */ 65 sys_freqctrl = au_readl(SYS_FREQCTRL0); 66 sys_freqctrl &= ~0xFFF00000; 67 au_writel(sys_freqctrl, SYS_FREQCTRL0); 68 69 /* zero and disable USBH/USBD/IrDA clock */ 70 sys_clksrc = au_readl(SYS_CLKSRC); 71 sys_clksrc &= ~0x0000001F; 72 au_writel(sys_clksrc, SYS_CLKSRC); 73 74 sys_freqctrl = au_readl(SYS_FREQCTRL0); 75 sys_freqctrl &= ~0xFFF00000; 76 77 sys_clksrc = au_readl(SYS_CLKSRC); 78 sys_clksrc &= ~0x0000001F; 79 80 // FREQ2 = aux/2 = 48 MHz 81 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); 82 au_writel(sys_freqctrl, SYS_FREQCTRL0); 83 84 /* 85 * Route 48MHz FREQ2 into USBH/USBD/IrDA 86 */ 87 sys_clksrc |= ((4<<2) | (0<<1) | 0 ); 88 au_writel(sys_clksrc, SYS_CLKSRC); 89 90 /* setup the static bus controller */ 91 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ 92 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ 93 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ 94 95 // get USB Functionality pin state (device vs host drive pins) 96 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000); 97 // 2nd USB port is USB host 98 pin_func |= 0x8000; 99 au_writel(pin_func, SYS_PINFUNC); 100 } 101#endif // defined (CONFIG_USB_OHCI) 102 103 /* Enable sys bus clock divider when IDLE state or no bus activity. */ 104 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); 105 106 // Enable the RTC if not already enabled 107 if (!(readb(base + 0x28) & 0x20)) { 108 writeb(readb(base + 0x28) | 0x20, base + 0x28); 109 au_sync(); 110 } 111 // Put the clock in BCD mode 112 if (readb(base + 0x2C) & 0x4) { /* reg B */ 113 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c); 114 au_sync(); 115 } 116} 117