1/* 2 * BRIEF MODULE DESCRIPTION 3 * Au1000 interrupt routines. 4 * 5 * Copyright 2001 MontaVista Software Inc. 6 * Author: MontaVista Software, Inc. 7 * ppopov@mvista.com or source@mvista.com 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 */ 29#include <linux/errno.h> 30#include <linux/init.h> 31#include <linux/irq.h> 32#include <linux/kernel_stat.h> 33#include <linux/module.h> 34#include <linux/signal.h> 35#include <linux/sched.h> 36#include <linux/types.h> 37#include <linux/interrupt.h> 38#include <linux/ioport.h> 39#include <linux/timex.h> 40#include <linux/slab.h> 41#include <linux/random.h> 42#include <linux/delay.h> 43#include <linux/bitops.h> 44 45#include <asm/bootinfo.h> 46#include <asm/io.h> 47#include <asm/mipsregs.h> 48#include <asm/system.h> 49#include <asm/mach-au1x00/au1000.h> 50#ifdef CONFIG_MIPS_PB1000 51#include <asm/mach-pb1x00/pb1000.h> 52#endif 53 54#undef DEBUG_IRQ 55#ifdef DEBUG_IRQ 56/* note: prints function name for you */ 57#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) 58#else 59#define DPRINTK(fmt, args...) 60#endif 61 62#define EXT_INTC0_REQ0 2 /* IP 2 */ 63#define EXT_INTC0_REQ1 3 /* IP 3 */ 64#define EXT_INTC1_REQ0 4 /* IP 4 */ 65#define EXT_INTC1_REQ1 5 /* IP 5 */ 66#define MIPS_TIMER_IP 7 /* IP 7 */ 67 68extern void set_debug_traps(void); 69extern irq_cpustat_t irq_stat [NR_CPUS]; 70extern void mips_timer_interrupt(void); 71 72static void setup_local_irq(unsigned int irq, int type, int int_req); 73static void end_irq(unsigned int irq_nr); 74static inline void mask_and_ack_level_irq(unsigned int irq_nr); 75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); 76static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr); 77static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr); 78inline void local_enable_irq(unsigned int irq_nr); 79inline void local_disable_irq(unsigned int irq_nr); 80 81void (*board_init_irq)(void); 82 83static DEFINE_SPINLOCK(irq_lock); 84 85 86inline void local_enable_irq(unsigned int irq_nr) 87{ 88 if (irq_nr > AU1000_LAST_INTC0_INT) { 89 au_writel(1<<(irq_nr-32), IC1_MASKSET); 90 au_writel(1<<(irq_nr-32), IC1_WAKESET); 91 } 92 else { 93 au_writel(1<<irq_nr, IC0_MASKSET); 94 au_writel(1<<irq_nr, IC0_WAKESET); 95 } 96 au_sync(); 97} 98 99 100inline void local_disable_irq(unsigned int irq_nr) 101{ 102 if (irq_nr > AU1000_LAST_INTC0_INT) { 103 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 104 au_writel(1<<(irq_nr-32), IC1_WAKECLR); 105 } 106 else { 107 au_writel(1<<irq_nr, IC0_MASKCLR); 108 au_writel(1<<irq_nr, IC0_WAKECLR); 109 } 110 au_sync(); 111} 112 113 114static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) 115{ 116 if (irq_nr > AU1000_LAST_INTC0_INT) { 117 au_writel(1<<(irq_nr-32), IC1_RISINGCLR); 118 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 119 } 120 else { 121 au_writel(1<<irq_nr, IC0_RISINGCLR); 122 au_writel(1<<irq_nr, IC0_MASKCLR); 123 } 124 au_sync(); 125} 126 127 128static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) 129{ 130 if (irq_nr > AU1000_LAST_INTC0_INT) { 131 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); 132 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 133 } 134 else { 135 au_writel(1<<irq_nr, IC0_FALLINGCLR); 136 au_writel(1<<irq_nr, IC0_MASKCLR); 137 } 138 au_sync(); 139} 140 141 142static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) 143{ 144 /* This may assume that we don't get interrupts from 145 * both edges at once, or if we do, that we don't care. 146 */ 147 if (irq_nr > AU1000_LAST_INTC0_INT) { 148 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); 149 au_writel(1<<(irq_nr-32), IC1_RISINGCLR); 150 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 151 } 152 else { 153 au_writel(1<<irq_nr, IC0_FALLINGCLR); 154 au_writel(1<<irq_nr, IC0_RISINGCLR); 155 au_writel(1<<irq_nr, IC0_MASKCLR); 156 } 157 au_sync(); 158} 159 160 161static inline void mask_and_ack_level_irq(unsigned int irq_nr) 162{ 163 164 local_disable_irq(irq_nr); 165 au_sync(); 166#if defined(CONFIG_MIPS_PB1000) 167 if (irq_nr == AU1000_GPIO_15) { 168 au_writel(0x8000, PB1000_MDR); /* ack int */ 169 au_sync(); 170 } 171#endif 172 return; 173} 174 175 176static void end_irq(unsigned int irq_nr) 177{ 178 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { 179 local_enable_irq(irq_nr); 180 } 181#if defined(CONFIG_MIPS_PB1000) 182 if (irq_nr == AU1000_GPIO_15) { 183 au_writel(0x4000, PB1000_MDR); /* enable int */ 184 au_sync(); 185 } 186#endif 187} 188 189unsigned long save_local_and_disable(int controller) 190{ 191 int i; 192 unsigned long flags, mask; 193 194 spin_lock_irqsave(&irq_lock, flags); 195 if (controller) { 196 mask = au_readl(IC1_MASKSET); 197 for (i=32; i<64; i++) { 198 local_disable_irq(i); 199 } 200 } 201 else { 202 mask = au_readl(IC0_MASKSET); 203 for (i=0; i<32; i++) { 204 local_disable_irq(i); 205 } 206 } 207 spin_unlock_irqrestore(&irq_lock, flags); 208 209 return mask; 210} 211 212void restore_local_and_enable(int controller, unsigned long mask) 213{ 214 int i; 215 unsigned long flags, new_mask; 216 217 spin_lock_irqsave(&irq_lock, flags); 218 for (i=0; i<32; i++) { 219 if (mask & (1<<i)) { 220 if (controller) 221 local_enable_irq(i+32); 222 else 223 local_enable_irq(i); 224 } 225 } 226 if (controller) 227 new_mask = au_readl(IC1_MASKSET); 228 else 229 new_mask = au_readl(IC0_MASKSET); 230 231 spin_unlock_irqrestore(&irq_lock, flags); 232} 233 234 235static struct irq_chip rise_edge_irq_type = { 236 .name = "Au1000 Rise Edge", 237 .ack = mask_and_ack_rise_edge_irq, 238 .mask = local_disable_irq, 239 .mask_ack = mask_and_ack_rise_edge_irq, 240 .unmask = local_enable_irq, 241 .end = end_irq, 242}; 243 244static struct irq_chip fall_edge_irq_type = { 245 .name = "Au1000 Fall Edge", 246 .ack = mask_and_ack_fall_edge_irq, 247 .mask = local_disable_irq, 248 .mask_ack = mask_and_ack_fall_edge_irq, 249 .unmask = local_enable_irq, 250 .end = end_irq, 251}; 252 253static struct irq_chip either_edge_irq_type = { 254 .name = "Au1000 Rise or Fall Edge", 255 .ack = mask_and_ack_either_edge_irq, 256 .mask = local_disable_irq, 257 .mask_ack = mask_and_ack_either_edge_irq, 258 .unmask = local_enable_irq, 259 .end = end_irq, 260}; 261 262static struct irq_chip level_irq_type = { 263 .name = "Au1000 Level", 264 .ack = mask_and_ack_level_irq, 265 .mask = local_disable_irq, 266 .mask_ack = mask_and_ack_level_irq, 267 .unmask = local_enable_irq, 268 .end = end_irq, 269}; 270 271#ifdef CONFIG_PM 272void startup_match20_interrupt(irq_handler_t handler) 273{ 274 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT]; 275 276 static struct irqaction action; 277 memset(&action, 0, sizeof(struct irqaction)); 278 279 /* This is a big problem.... since we didn't use request_irq 280 * when kernel/irq.c calls probe_irq_xxx this interrupt will 281 * be probed for usage. This will end up disabling the device :( 282 * Give it a bogus "action" pointer -- this will keep it from 283 * getting auto-probed! 284 * 285 * By setting the status to match that of request_irq() we 286 * can avoid it. --cgray 287 */ 288 action.dev_id = handler; 289 action.flags = IRQF_DISABLED; 290 cpus_clear(action.mask); 291 action.name = "Au1xxx TOY"; 292 action.handler = handler; 293 action.next = NULL; 294 295 desc->action = &action; 296 desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS); 297 298 local_enable_irq(AU1000_TOY_MATCH2_INT); 299} 300#endif 301 302static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 303{ 304 if (irq_nr > AU1000_MAX_INTR) return; 305 /* Config2[n], Config1[n], Config0[n] */ 306 if (irq_nr > AU1000_LAST_INTC0_INT) { 307 switch (type) { 308 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 309 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 310 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 311 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 312 set_irq_chip(irq_nr, &rise_edge_irq_type); 313 break; 314 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 315 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 316 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 317 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 318 set_irq_chip(irq_nr, &fall_edge_irq_type); 319 break; 320 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 321 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 322 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 323 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 324 set_irq_chip(irq_nr, &either_edge_irq_type); 325 break; 326 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 327 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 328 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 329 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 330 set_irq_chip(irq_nr, &level_irq_type); 331 break; 332 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 333 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 334 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 335 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 336 set_irq_chip(irq_nr, &level_irq_type); 337 break; 338 case INTC_INT_DISABLED: /* 0:0:0 */ 339 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 340 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 341 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 342 break; 343 default: /* disable the interrupt */ 344 printk("unexpected int type %d (irq %d)\n", type, irq_nr); 345 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 346 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 347 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 348 return; 349 } 350 if (int_req) /* assign to interrupt request 1 */ 351 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR); 352 else /* assign to interrupt request 0 */ 353 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET); 354 au_writel(1<<(irq_nr-32), IC1_SRCSET); 355 au_writel(1<<(irq_nr-32), IC1_MASKCLR); 356 au_writel(1<<(irq_nr-32), IC1_WAKECLR); 357 } 358 else { 359 switch (type) { 360 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 361 au_writel(1<<irq_nr, IC0_CFG2CLR); 362 au_writel(1<<irq_nr, IC0_CFG1CLR); 363 au_writel(1<<irq_nr, IC0_CFG0SET); 364 set_irq_chip(irq_nr, &rise_edge_irq_type); 365 break; 366 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 367 au_writel(1<<irq_nr, IC0_CFG2CLR); 368 au_writel(1<<irq_nr, IC0_CFG1SET); 369 au_writel(1<<irq_nr, IC0_CFG0CLR); 370 set_irq_chip(irq_nr, &fall_edge_irq_type); 371 break; 372 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 373 au_writel(1<<irq_nr, IC0_CFG2CLR); 374 au_writel(1<<irq_nr, IC0_CFG1SET); 375 au_writel(1<<irq_nr, IC0_CFG0SET); 376 set_irq_chip(irq_nr, &either_edge_irq_type); 377 break; 378 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 379 au_writel(1<<irq_nr, IC0_CFG2SET); 380 au_writel(1<<irq_nr, IC0_CFG1CLR); 381 au_writel(1<<irq_nr, IC0_CFG0SET); 382 set_irq_chip(irq_nr, &level_irq_type); 383 break; 384 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 385 au_writel(1<<irq_nr, IC0_CFG2SET); 386 au_writel(1<<irq_nr, IC0_CFG1SET); 387 au_writel(1<<irq_nr, IC0_CFG0CLR); 388 set_irq_chip(irq_nr, &level_irq_type); 389 break; 390 case INTC_INT_DISABLED: /* 0:0:0 */ 391 au_writel(1<<irq_nr, IC0_CFG0CLR); 392 au_writel(1<<irq_nr, IC0_CFG1CLR); 393 au_writel(1<<irq_nr, IC0_CFG2CLR); 394 break; 395 default: /* disable the interrupt */ 396 printk("unexpected int type %d (irq %d)\n", type, irq_nr); 397 au_writel(1<<irq_nr, IC0_CFG0CLR); 398 au_writel(1<<irq_nr, IC0_CFG1CLR); 399 au_writel(1<<irq_nr, IC0_CFG2CLR); 400 return; 401 } 402 if (int_req) /* assign to interrupt request 1 */ 403 au_writel(1<<irq_nr, IC0_ASSIGNCLR); 404 else /* assign to interrupt request 0 */ 405 au_writel(1<<irq_nr, IC0_ASSIGNSET); 406 au_writel(1<<irq_nr, IC0_SRCSET); 407 au_writel(1<<irq_nr, IC0_MASKCLR); 408 au_writel(1<<irq_nr, IC0_WAKECLR); 409 } 410 au_sync(); 411} 412 413 414void __init arch_init_irq(void) 415{ 416 int i; 417 unsigned long cp0_status; 418 au1xxx_irq_map_t *imp; 419 extern au1xxx_irq_map_t au1xxx_irq_map[]; 420 extern au1xxx_irq_map_t au1xxx_ic0_map[]; 421 extern int au1xxx_nr_irqs; 422 extern int au1xxx_ic0_nr_irqs; 423 424 cp0_status = read_c0_status(); 425 426 /* Initialize interrupt controllers to a safe state. 427 */ 428 au_writel(0xffffffff, IC0_CFG0CLR); 429 au_writel(0xffffffff, IC0_CFG1CLR); 430 au_writel(0xffffffff, IC0_CFG2CLR); 431 au_writel(0xffffffff, IC0_MASKCLR); 432 au_writel(0xffffffff, IC0_ASSIGNSET); 433 au_writel(0xffffffff, IC0_WAKECLR); 434 au_writel(0xffffffff, IC0_SRCSET); 435 au_writel(0xffffffff, IC0_FALLINGCLR); 436 au_writel(0xffffffff, IC0_RISINGCLR); 437 au_writel(0x00000000, IC0_TESTBIT); 438 439 au_writel(0xffffffff, IC1_CFG0CLR); 440 au_writel(0xffffffff, IC1_CFG1CLR); 441 au_writel(0xffffffff, IC1_CFG2CLR); 442 au_writel(0xffffffff, IC1_MASKCLR); 443 au_writel(0xffffffff, IC1_ASSIGNSET); 444 au_writel(0xffffffff, IC1_WAKECLR); 445 au_writel(0xffffffff, IC1_SRCSET); 446 au_writel(0xffffffff, IC1_FALLINGCLR); 447 au_writel(0xffffffff, IC1_RISINGCLR); 448 au_writel(0x00000000, IC1_TESTBIT); 449 450 /* Initialize IC0, which is fixed per processor. 451 */ 452 imp = au1xxx_ic0_map; 453 for (i=0; i<au1xxx_ic0_nr_irqs; i++) { 454 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); 455 imp++; 456 } 457 458 /* Now set up the irq mapping for the board. 459 */ 460 imp = au1xxx_irq_map; 461 for (i=0; i<au1xxx_nr_irqs; i++) { 462 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); 463 imp++; 464 } 465 466 set_c0_status(ALLINTS); 467 468 /* Board specific IRQ initialization. 469 */ 470 if (board_init_irq) 471 (*board_init_irq)(); 472} 473 474 475/* 476 * Interrupts are nested. Even if an interrupt handler is registered 477 * as "fast", we might get another interrupt before we return from 478 * intcX_reqX_irqdispatch(). 479 */ 480 481static void intc0_req0_irqdispatch(void) 482{ 483 int irq = 0; 484 static unsigned long intc0_req0 = 0; 485 486 intc0_req0 |= au_readl(IC0_REQ0INT); 487 488 if (!intc0_req0) 489 return; 490#ifdef AU1000_USB_DEV_REQ_INT 491 /* 492 * Because of the tight timing of SETUP token to reply 493 * transactions, the USB devices-side packet complete 494 * interrupt needs the highest priority. 495 */ 496 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) { 497 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT); 498 do_IRQ(AU1000_USB_DEV_REQ_INT); 499 return; 500 } 501#endif 502 irq = au_ffs(intc0_req0) - 1; 503 intc0_req0 &= ~(1<<irq); 504 do_IRQ(irq); 505} 506 507 508static void intc0_req1_irqdispatch(void) 509{ 510 int irq = 0; 511 static unsigned long intc0_req1 = 0; 512 513 intc0_req1 |= au_readl(IC0_REQ1INT); 514 515 if (!intc0_req1) 516 return; 517 518 irq = au_ffs(intc0_req1) - 1; 519 intc0_req1 &= ~(1<<irq); 520 do_IRQ(irq); 521} 522 523 524/* 525 * Interrupt Controller 1: 526 * interrupts 32 - 63 527 */ 528static void intc1_req0_irqdispatch(void) 529{ 530 int irq = 0; 531 static unsigned long intc1_req0 = 0; 532 533 intc1_req0 |= au_readl(IC1_REQ0INT); 534 535 if (!intc1_req0) 536 return; 537 538 irq = au_ffs(intc1_req0) - 1; 539 intc1_req0 &= ~(1<<irq); 540 irq += 32; 541 do_IRQ(irq); 542} 543 544 545static void intc1_req1_irqdispatch(void) 546{ 547 int irq = 0; 548 static unsigned long intc1_req1 = 0; 549 550 intc1_req1 |= au_readl(IC1_REQ1INT); 551 552 if (!intc1_req1) 553 return; 554 555 irq = au_ffs(intc1_req1) - 1; 556 intc1_req1 &= ~(1<<irq); 557 irq += 32; 558 do_IRQ(irq); 559} 560 561#ifdef CONFIG_PM 562 563/* Save/restore the interrupt controller state. 564 * Called from the save/restore core registers as part of the 565 * au_sleep function in power.c.....maybe I should just pm_register() 566 * them instead? 567 */ 568static unsigned int sleep_intctl_config0[2]; 569static unsigned int sleep_intctl_config1[2]; 570static unsigned int sleep_intctl_config2[2]; 571static unsigned int sleep_intctl_src[2]; 572static unsigned int sleep_intctl_assign[2]; 573static unsigned int sleep_intctl_wake[2]; 574static unsigned int sleep_intctl_mask[2]; 575 576void 577save_au1xxx_intctl(void) 578{ 579 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD); 580 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD); 581 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD); 582 sleep_intctl_src[0] = au_readl(IC0_SRCRD); 583 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD); 584 sleep_intctl_wake[0] = au_readl(IC0_WAKERD); 585 sleep_intctl_mask[0] = au_readl(IC0_MASKRD); 586 587 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD); 588 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD); 589 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD); 590 sleep_intctl_src[1] = au_readl(IC1_SRCRD); 591 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD); 592 sleep_intctl_wake[1] = au_readl(IC1_WAKERD); 593 sleep_intctl_mask[1] = au_readl(IC1_MASKRD); 594} 595 596/* For most restore operations, we clear the entire register and 597 * then set the bits we found during the save. 598 */ 599void 600restore_au1xxx_intctl(void) 601{ 602 au_writel(0xffffffff, IC0_MASKCLR); au_sync(); 603 604 au_writel(0xffffffff, IC0_CFG0CLR); au_sync(); 605 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync(); 606 au_writel(0xffffffff, IC0_CFG1CLR); au_sync(); 607 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync(); 608 au_writel(0xffffffff, IC0_CFG2CLR); au_sync(); 609 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync(); 610 au_writel(0xffffffff, IC0_SRCCLR); au_sync(); 611 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync(); 612 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync(); 613 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync(); 614 au_writel(0xffffffff, IC0_WAKECLR); au_sync(); 615 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync(); 616 au_writel(0xffffffff, IC0_RISINGCLR); au_sync(); 617 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync(); 618 au_writel(0x00000000, IC0_TESTBIT); au_sync(); 619 620 au_writel(0xffffffff, IC1_MASKCLR); au_sync(); 621 622 au_writel(0xffffffff, IC1_CFG0CLR); au_sync(); 623 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync(); 624 au_writel(0xffffffff, IC1_CFG1CLR); au_sync(); 625 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync(); 626 au_writel(0xffffffff, IC1_CFG2CLR); au_sync(); 627 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync(); 628 au_writel(0xffffffff, IC1_SRCCLR); au_sync(); 629 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync(); 630 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync(); 631 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync(); 632 au_writel(0xffffffff, IC1_WAKECLR); au_sync(); 633 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync(); 634 au_writel(0xffffffff, IC1_RISINGCLR); au_sync(); 635 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync(); 636 au_writel(0x00000000, IC1_TESTBIT); au_sync(); 637 638 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync(); 639 640 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync(); 641} 642#endif /* CONFIG_PM */ 643 644asmlinkage void plat_irq_dispatch(void) 645{ 646 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 647 648 if (pending & CAUSEF_IP7) 649 mips_timer_interrupt(); 650 else if (pending & CAUSEF_IP2) 651 intc0_req0_irqdispatch(); 652 else if (pending & CAUSEF_IP3) 653 intc0_req1_irqdispatch(); 654 else if (pending & CAUSEF_IP4) 655 intc1_req0_irqdispatch(); 656 else if (pending & CAUSEF_IP5) 657 intc1_req1_irqdispatch(); 658 else 659 spurious_interrupt(); 660} 661