1/* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17#include <linux/init.h> 18 19#include <linux/mm.h> 20#include <linux/delay.h> 21#include <linux/bootmem.h> 22#include <linux/interrupt.h> 23#include <linux/mc146818rtc.h> 24#include <linux/kernel_stat.h> 25#include <linux/sysdev.h> 26#include <linux/cpu.h> 27#include <linux/clockchips.h> 28#include <linux/acpi_pmtmr.h> 29#include <linux/module.h> 30#include <linux/dmi.h> 31 32#include <asm/atomic.h> 33#include <asm/smp.h> 34#include <asm/mtrr.h> 35#include <asm/mpspec.h> 36#include <asm/desc.h> 37#include <asm/arch_hooks.h> 38#include <asm/hpet.h> 39#include <asm/i8253.h> 40#include <asm/nmi.h> 41 42#include <mach_apic.h> 43#include <mach_apicdef.h> 44#include <mach_ipi.h> 45 46#include "io_ports.h" 47 48/* 49 * Sanity check 50 */ 51#if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F 52# error SPURIOUS_APIC_VECTOR definition error 53#endif 54 55/* 56 * Knob to control our willingness to enable the local APIC. 57 * 58 * -1=force-disable, +1=force-enable 59 */ 60static int enable_local_apic __initdata = 0; 61 62/* Local APIC timer verification ok */ 63static int local_apic_timer_verify_ok; 64/* Disable local APIC timer from the kernel commandline or via dmi quirk */ 65static int local_apic_timer_disabled; 66/* Local APIC timer works in C2 */ 67int local_apic_timer_c2_ok; 68EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 69 70/* 71 * Debug level, exported for io_apic.c 72 */ 73int apic_verbosity; 74 75static unsigned int calibration_result; 76 77static int lapic_next_event(unsigned long delta, 78 struct clock_event_device *evt); 79static void lapic_timer_setup(enum clock_event_mode mode, 80 struct clock_event_device *evt); 81static void lapic_timer_broadcast(cpumask_t mask); 82static void apic_pm_activate(void); 83 84/* 85 * The local apic timer can be used for any function which is CPU local. 86 */ 87static struct clock_event_device lapic_clockevent = { 88 .name = "lapic", 89 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 90 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 91 .shift = 32, 92 .set_mode = lapic_timer_setup, 93 .set_next_event = lapic_next_event, 94 .broadcast = lapic_timer_broadcast, 95 .rating = 100, 96 .irq = -1, 97}; 98static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 99 100/* Local APIC was disabled by the BIOS and enabled by the kernel */ 101static int enabled_via_apicbase; 102 103/* 104 * Get the LAPIC version 105 */ 106static inline int lapic_get_version(void) 107{ 108 return GET_APIC_VERSION(apic_read(APIC_LVR)); 109} 110 111/* 112 * Check, if the APIC is integrated or a seperate chip 113 */ 114static inline int lapic_is_integrated(void) 115{ 116 return APIC_INTEGRATED(lapic_get_version()); 117} 118 119/* 120 * Check, whether this is a modern or a first generation APIC 121 */ 122static int modern_apic(void) 123{ 124 /* AMD systems use old APIC versions, so check the CPU */ 125 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 126 boot_cpu_data.x86 >= 0xf) 127 return 1; 128 return lapic_get_version() >= 0x14; 129} 130 131void apic_wait_icr_idle(void) 132{ 133 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 134 cpu_relax(); 135} 136 137unsigned long safe_apic_wait_icr_idle(void) 138{ 139 unsigned long send_status; 140 int timeout; 141 142 timeout = 0; 143 do { 144 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 145 if (!send_status) 146 break; 147 udelay(100); 148 } while (timeout++ < 1000); 149 150 return send_status; 151} 152 153/** 154 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 155 */ 156void enable_NMI_through_LVT0 (void * dummy) 157{ 158 unsigned int v = APIC_DM_NMI; 159 160 /* Level triggered for 82489DX */ 161 if (!lapic_is_integrated()) 162 v |= APIC_LVT_LEVEL_TRIGGER; 163 apic_write_around(APIC_LVT0, v); 164} 165 166/** 167 * get_physical_broadcast - Get number of physical broadcast IDs 168 */ 169int get_physical_broadcast(void) 170{ 171 return modern_apic() ? 0xff : 0xf; 172} 173 174/** 175 * lapic_get_maxlvt - get the maximum number of local vector table entries 176 */ 177int lapic_get_maxlvt(void) 178{ 179 unsigned int v = apic_read(APIC_LVR); 180 181 /* 82489DXs do not report # of LVT entries. */ 182 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 183} 184 185/* 186 * Local APIC timer 187 */ 188 189/* Clock divisor is set to 16 */ 190#define APIC_DIVISOR 16 191 192/* 193 * This function sets up the local APIC timer, with a timeout of 194 * 'clocks' APIC bus clock. During calibration we actually call 195 * this function twice on the boot CPU, once with a bogus timeout 196 * value, second time for real. The other (noncalibrating) CPUs 197 * call this function only once, with the real, calibrated value. 198 * 199 * We do reads before writes even if unnecessary, to get around the 200 * P5 APIC double write bug. 201 */ 202static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 203{ 204 unsigned int lvtt_value, tmp_value; 205 206 lvtt_value = LOCAL_TIMER_VECTOR; 207 if (!oneshot) 208 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 209 if (!lapic_is_integrated()) 210 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 211 212 if (!irqen) 213 lvtt_value |= APIC_LVT_MASKED; 214 215 apic_write_around(APIC_LVTT, lvtt_value); 216 217 /* 218 * Divide PICLK by 16 219 */ 220 tmp_value = apic_read(APIC_TDCR); 221 apic_write_around(APIC_TDCR, (tmp_value 222 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) 223 | APIC_TDR_DIV_16); 224 225 if (!oneshot) 226 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); 227} 228 229/* 230 * Program the next event, relative to now 231 */ 232static int lapic_next_event(unsigned long delta, 233 struct clock_event_device *evt) 234{ 235 apic_write_around(APIC_TMICT, delta); 236 return 0; 237} 238 239/* 240 * Setup the lapic timer in periodic or oneshot mode 241 */ 242static void lapic_timer_setup(enum clock_event_mode mode, 243 struct clock_event_device *evt) 244{ 245 unsigned long flags; 246 unsigned int v; 247 248 /* Lapic used for broadcast ? */ 249 if (!local_apic_timer_verify_ok) 250 return; 251 252 local_irq_save(flags); 253 254 switch (mode) { 255 case CLOCK_EVT_MODE_PERIODIC: 256 case CLOCK_EVT_MODE_ONESHOT: 257 __setup_APIC_LVTT(calibration_result, 258 mode != CLOCK_EVT_MODE_PERIODIC, 1); 259 break; 260 case CLOCK_EVT_MODE_UNUSED: 261 case CLOCK_EVT_MODE_SHUTDOWN: 262 v = apic_read(APIC_LVTT); 263 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 264 apic_write_around(APIC_LVTT, v); 265 break; 266 } 267 268 local_irq_restore(flags); 269} 270 271/* 272 * Local APIC timer broadcast function 273 */ 274static void lapic_timer_broadcast(cpumask_t mask) 275{ 276#ifdef CONFIG_SMP 277 send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 278#endif 279} 280 281/* 282 * Setup the local APIC timer for this CPU. Copy the initilized values 283 * of the boot CPU and register the clock event in the framework. 284 */ 285static void __devinit setup_APIC_timer(void) 286{ 287 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 288 289 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 290 levt->cpumask = cpumask_of_cpu(smp_processor_id()); 291 292 clockevents_register_device(levt); 293} 294 295/* 296 * In this functions we calibrate APIC bus clocks to the external timer. 297 * 298 * We want to do the calibration only once since we want to have local timer 299 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 300 * frequency. 301 * 302 * This was previously done by reading the PIT/HPET and waiting for a wrap 303 * around to find out, that a tick has elapsed. I have a box, where the PIT 304 * readout is broken, so it never gets out of the wait loop again. This was 305 * also reported by others. 306 * 307 * Monitoring the jiffies value is inaccurate and the clockevents 308 * infrastructure allows us to do a simple substitution of the interrupt 309 * handler. 310 * 311 * The calibration routine also uses the pm_timer when possible, as the PIT 312 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 313 * back to normal later in the boot process). 314 */ 315 316#define LAPIC_CAL_LOOPS (HZ/10) 317 318static __initdata volatile int lapic_cal_loops = -1; 319static __initdata long lapic_cal_t1, lapic_cal_t2; 320static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 321static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 322static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 323 324/* 325 * Temporary interrupt handler. 326 */ 327static void __init lapic_cal_handler(struct clock_event_device *dev) 328{ 329 unsigned long long tsc = 0; 330 long tapic = apic_read(APIC_TMCCT); 331 unsigned long pm = acpi_pm_read_early(); 332 333 if (cpu_has_tsc) 334 rdtscll(tsc); 335 336 switch (lapic_cal_loops++) { 337 case 0: 338 lapic_cal_t1 = tapic; 339 lapic_cal_tsc1 = tsc; 340 lapic_cal_pm1 = pm; 341 lapic_cal_j1 = jiffies; 342 break; 343 344 case LAPIC_CAL_LOOPS: 345 lapic_cal_t2 = tapic; 346 lapic_cal_tsc2 = tsc; 347 if (pm < lapic_cal_pm1) 348 pm += ACPI_PM_OVRRUN; 349 lapic_cal_pm2 = pm; 350 lapic_cal_j2 = jiffies; 351 break; 352 } 353} 354 355/* 356 * Setup the boot APIC 357 * 358 * Calibrate and verify the result. 359 */ 360void __init setup_boot_APIC_clock(void) 361{ 362 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 363 const long pm_100ms = PMTMR_TICKS_PER_SEC/10; 364 const long pm_thresh = pm_100ms/100; 365 void (*real_handler)(struct clock_event_device *dev); 366 unsigned long deltaj; 367 long delta, deltapm; 368 int pm_referenced = 0; 369 370 if (boot_cpu_has(X86_FEATURE_LAPIC_TIMER_BROKEN)) 371 local_apic_timer_disabled = 1; 372 373 /* 374 * The local apic timer can be disabled via the kernel 375 * commandline or from the test above. Register the lapic 376 * timer as a dummy clock event source on SMP systems, so the 377 * broadcast mechanism is used. On UP systems simply ignore it. 378 */ 379 if (local_apic_timer_disabled) { 380 /* No broadcast on UP ! */ 381 if (num_possible_cpus() > 1) 382 setup_APIC_timer(); 383 return; 384 } 385 386 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 387 "calibrating APIC timer ...\n"); 388 389 local_irq_disable(); 390 391 /* Replace the global interrupt handler */ 392 real_handler = global_clock_event->event_handler; 393 global_clock_event->event_handler = lapic_cal_handler; 394 395 /* 396 * Setup the APIC counter to 1e9. There is no way the lapic 397 * can underflow in the 100ms detection time frame 398 */ 399 __setup_APIC_LVTT(1000000000, 0, 0); 400 401 /* Let the interrupts run */ 402 local_irq_enable(); 403 404 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 405 cpu_relax(); 406 407 local_irq_disable(); 408 409 /* Restore the real event handler */ 410 global_clock_event->event_handler = real_handler; 411 412 /* Build delta t1-t2 as apic timer counts down */ 413 delta = lapic_cal_t1 - lapic_cal_t2; 414 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 415 416 /* Check, if the PM timer is available */ 417 deltapm = lapic_cal_pm2 - lapic_cal_pm1; 418 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); 419 420 if (deltapm) { 421 unsigned long mult; 422 u64 res; 423 424 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 425 426 if (deltapm > (pm_100ms - pm_thresh) && 427 deltapm < (pm_100ms + pm_thresh)) { 428 apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); 429 } else { 430 res = (((u64) deltapm) * mult) >> 22; 431 do_div(res, 1000000); 432 printk(KERN_WARNING "APIC calibration not consistent " 433 "with PM Timer: %ldms instead of 100ms\n", 434 (long)res); 435 /* Correct the lapic counter value */ 436 res = (((u64) delta ) * pm_100ms); 437 do_div(res, deltapm); 438 printk(KERN_INFO "APIC delta adjusted to PM-Timer: " 439 "%lu (%ld)\n", (unsigned long) res, delta); 440 delta = (long) res; 441 } 442 pm_referenced = 1; 443 } 444 445 /* Calculate the scaled math multiplication factor */ 446 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32); 447 lapic_clockevent.max_delta_ns = 448 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 449 lapic_clockevent.min_delta_ns = 450 clockevent_delta2ns(0xF, &lapic_clockevent); 451 452 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 453 454 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 455 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); 456 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 457 calibration_result); 458 459 if (cpu_has_tsc) { 460 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 461 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 462 "%ld.%04ld MHz.\n", 463 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), 464 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 465 } 466 467 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 468 "%u.%04u MHz.\n", 469 calibration_result / (1000000 / HZ), 470 calibration_result % (1000000 / HZ)); 471 472 local_apic_timer_verify_ok = 1; 473 474 /* We trust the pm timer based calibration */ 475 if (!pm_referenced) { 476 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 477 478 /* 479 * Setup the apic timer manually 480 */ 481 levt->event_handler = lapic_cal_handler; 482 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 483 lapic_cal_loops = -1; 484 485 /* Let the interrupts run */ 486 local_irq_enable(); 487 488 while(lapic_cal_loops <= LAPIC_CAL_LOOPS) 489 cpu_relax(); 490 491 local_irq_disable(); 492 493 /* Stop the lapic timer */ 494 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 495 496 local_irq_enable(); 497 498 /* Jiffies delta */ 499 deltaj = lapic_cal_j2 - lapic_cal_j1; 500 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 501 502 /* Check, if the jiffies result is consistent */ 503 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 504 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 505 else 506 local_apic_timer_verify_ok = 0; 507 } else 508 local_irq_enable(); 509 510 if (!local_apic_timer_verify_ok) { 511 printk(KERN_WARNING 512 "APIC timer disabled due to verification failure.\n"); 513 /* No broadcast on UP ! */ 514 if (num_possible_cpus() == 1) 515 return; 516 } else { 517 /* 518 * If nmi_watchdog is set to IO_APIC, we need the 519 * PIT/HPET going. Otherwise register lapic as a dummy 520 * device. 521 */ 522 if (nmi_watchdog != NMI_IO_APIC) 523 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 524 } 525 526 /* Setup the lapic or request the broadcast */ 527 setup_APIC_timer(); 528} 529 530void __devinit setup_secondary_APIC_clock(void) 531{ 532 setup_APIC_timer(); 533} 534 535/* 536 * The guts of the apic timer interrupt 537 */ 538static void local_apic_timer_interrupt(void) 539{ 540 int cpu = smp_processor_id(); 541 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 542 543 /* 544 * Normally we should not be here till LAPIC has been initialized but 545 * in some cases like kdump, its possible that there is a pending LAPIC 546 * timer interrupt from previous kernel's context and is delivered in 547 * new kernel the moment interrupts are enabled. 548 * 549 * Interrupts are enabled early and LAPIC is setup much later, hence 550 * its possible that when we get here evt->event_handler is NULL. 551 * Check for event_handler being NULL and discard the interrupt as 552 * spurious. 553 */ 554 if (!evt->event_handler) { 555 printk(KERN_WARNING 556 "Spurious LAPIC timer interrupt on cpu %d\n", cpu); 557 /* Switch it off */ 558 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 559 return; 560 } 561 562 per_cpu(irq_stat, cpu).apic_timer_irqs++; 563 564 evt->event_handler(evt); 565} 566 567/* 568 * Local APIC timer interrupt. This is the most natural way for doing 569 * local interrupts, but local timer interrupts can be emulated by 570 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 571 * 572 * [ if a single-CPU system runs an SMP kernel then we call the local 573 * interrupt as well. Thus we cannot inline the local irq ... ] 574 */ 575 576void fastcall smp_apic_timer_interrupt(struct pt_regs *regs) 577{ 578 struct pt_regs *old_regs = set_irq_regs(regs); 579 580 /* 581 * NOTE! We'd better ACK the irq immediately, 582 * because timer handling can be slow. 583 */ 584 ack_APIC_irq(); 585 /* 586 * update_process_times() expects us to have done irq_enter(). 587 * Besides, if we don't timer interrupts ignore the global 588 * interrupt lock, which is the WrongThing (tm) to do. 589 */ 590 irq_enter(); 591 local_apic_timer_interrupt(); 592 irq_exit(); 593 594 set_irq_regs(old_regs); 595} 596 597int setup_profiling_timer(unsigned int multiplier) 598{ 599 return -EINVAL; 600} 601 602/* 603 * Local APIC start and shutdown 604 */ 605 606/** 607 * clear_local_APIC - shutdown the local APIC 608 * 609 * This is called, when a CPU is disabled and before rebooting, so the state of 610 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 611 * leftovers during boot. 612 */ 613void clear_local_APIC(void) 614{ 615 int maxlvt = lapic_get_maxlvt(); 616 unsigned long v; 617 618 /* 619 * Masking an LVT entry can trigger a local APIC error 620 * if the vector is zero. Mask LVTERR first to prevent this. 621 */ 622 if (maxlvt >= 3) { 623 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 624 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); 625 } 626 /* 627 * Careful: we have to set masks only first to deassert 628 * any level-triggered sources. 629 */ 630 v = apic_read(APIC_LVTT); 631 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); 632 v = apic_read(APIC_LVT0); 633 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); 634 v = apic_read(APIC_LVT1); 635 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); 636 if (maxlvt >= 4) { 637 v = apic_read(APIC_LVTPC); 638 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); 639 } 640 641 /* lets not touch this if we didn't frob it */ 642#ifdef CONFIG_X86_MCE_P4THERMAL 643 if (maxlvt >= 5) { 644 v = apic_read(APIC_LVTTHMR); 645 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); 646 } 647#endif 648 /* 649 * Clean APIC state for other OSs: 650 */ 651 apic_write_around(APIC_LVTT, APIC_LVT_MASKED); 652 apic_write_around(APIC_LVT0, APIC_LVT_MASKED); 653 apic_write_around(APIC_LVT1, APIC_LVT_MASKED); 654 if (maxlvt >= 3) 655 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); 656 if (maxlvt >= 4) 657 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); 658 659#ifdef CONFIG_X86_MCE_P4THERMAL 660 if (maxlvt >= 5) 661 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); 662#endif 663 /* Integrated APIC (!82489DX) ? */ 664 if (lapic_is_integrated()) { 665 if (maxlvt > 3) 666 /* Clear ESR due to Pentium errata 3AP and 11AP */ 667 apic_write(APIC_ESR, 0); 668 apic_read(APIC_ESR); 669 } 670} 671 672/** 673 * disable_local_APIC - clear and disable the local APIC 674 */ 675void disable_local_APIC(void) 676{ 677 unsigned long value; 678 679 clear_local_APIC(); 680 681 /* 682 * Disable APIC (implies clearing of registers 683 * for 82489DX!). 684 */ 685 value = apic_read(APIC_SPIV); 686 value &= ~APIC_SPIV_APIC_ENABLED; 687 apic_write_around(APIC_SPIV, value); 688 689 /* 690 * When LAPIC was disabled by the BIOS and enabled by the kernel, 691 * restore the disabled state. 692 */ 693 if (enabled_via_apicbase) { 694 unsigned int l, h; 695 696 rdmsr(MSR_IA32_APICBASE, l, h); 697 l &= ~MSR_IA32_APICBASE_ENABLE; 698 wrmsr(MSR_IA32_APICBASE, l, h); 699 } 700} 701 702/* 703 * If Linux enabled the LAPIC against the BIOS default disable it down before 704 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 705 * not power-off. Additionally clear all LVT entries before disable_local_APIC 706 * for the case where Linux didn't enable the LAPIC. 707 */ 708void lapic_shutdown(void) 709{ 710 unsigned long flags; 711 712 if (!cpu_has_apic) 713 return; 714 715 local_irq_save(flags); 716 clear_local_APIC(); 717 718 if (enabled_via_apicbase) 719 disable_local_APIC(); 720 721 local_irq_restore(flags); 722} 723 724/* 725 * This is to verify that we're looking at a real local APIC. 726 * Check these against your board if the CPUs aren't getting 727 * started for no apparent reason. 728 */ 729int __init verify_local_APIC(void) 730{ 731 unsigned int reg0, reg1; 732 733 /* 734 * The version register is read-only in a real APIC. 735 */ 736 reg0 = apic_read(APIC_LVR); 737 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 738 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 739 reg1 = apic_read(APIC_LVR); 740 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 741 742 /* 743 * The two version reads above should print the same 744 * numbers. If the second one is different, then we 745 * poke at a non-APIC. 746 */ 747 if (reg1 != reg0) 748 return 0; 749 750 /* 751 * Check if the version looks reasonably. 752 */ 753 reg1 = GET_APIC_VERSION(reg0); 754 if (reg1 == 0x00 || reg1 == 0xff) 755 return 0; 756 reg1 = lapic_get_maxlvt(); 757 if (reg1 < 0x02 || reg1 == 0xff) 758 return 0; 759 760 /* 761 * The ID register is read/write in a real APIC. 762 */ 763 reg0 = apic_read(APIC_ID); 764 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 765 766 /* 767 * The next two are just to see if we have sane values. 768 * They're only really relevant if we're in Virtual Wire 769 * compatibility mode, but most boxes are anymore. 770 */ 771 reg0 = apic_read(APIC_LVT0); 772 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 773 reg1 = apic_read(APIC_LVT1); 774 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 775 776 return 1; 777} 778 779/** 780 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 781 */ 782void __init sync_Arb_IDs(void) 783{ 784 /* 785 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 786 * needed on AMD. 787 */ 788 if (modern_apic()) 789 return; 790 /* 791 * Wait for idle. 792 */ 793 apic_wait_icr_idle(); 794 795 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 796 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG 797 | APIC_DM_INIT); 798} 799 800/* 801 * An initial setup of the virtual wire mode. 802 */ 803void __init init_bsp_APIC(void) 804{ 805 unsigned long value; 806 807 /* 808 * Don't do the setup now if we have a SMP BIOS as the 809 * through-I/O-APIC virtual wire mode might be active. 810 */ 811 if (smp_found_config || !cpu_has_apic) 812 return; 813 814 /* 815 * Do not trust the local APIC being empty at bootup. 816 */ 817 clear_local_APIC(); 818 819 /* 820 * Enable APIC. 821 */ 822 value = apic_read(APIC_SPIV); 823 value &= ~APIC_VECTOR_MASK; 824 value |= APIC_SPIV_APIC_ENABLED; 825 826 /* This bit is reserved on P4/Xeon and should be cleared */ 827 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 828 (boot_cpu_data.x86 == 15)) 829 value &= ~APIC_SPIV_FOCUS_DISABLED; 830 else 831 value |= APIC_SPIV_FOCUS_DISABLED; 832 value |= SPURIOUS_APIC_VECTOR; 833 apic_write_around(APIC_SPIV, value); 834 835 /* 836 * Set up the virtual wire mode. 837 */ 838 apic_write_around(APIC_LVT0, APIC_DM_EXTINT); 839 value = APIC_DM_NMI; 840 if (!lapic_is_integrated()) /* 82489DX */ 841 value |= APIC_LVT_LEVEL_TRIGGER; 842 apic_write_around(APIC_LVT1, value); 843} 844 845/** 846 * setup_local_APIC - setup the local APIC 847 */ 848void __devinit setup_local_APIC(void) 849{ 850 unsigned long oldvalue, value, maxlvt, integrated; 851 int i, j; 852 853 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 854 if (esr_disable) { 855 apic_write(APIC_ESR, 0); 856 apic_write(APIC_ESR, 0); 857 apic_write(APIC_ESR, 0); 858 apic_write(APIC_ESR, 0); 859 } 860 861 integrated = lapic_is_integrated(); 862 863 /* 864 * Double-check whether this APIC is really registered. 865 */ 866 if (!apic_id_registered()) 867 BUG(); 868 869 /* 870 * Intel recommends to set DFR, LDR and TPR before enabling 871 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 872 * document number 292116). So here it goes... 873 */ 874 init_apic_ldr(); 875 876 /* 877 * Set Task Priority to 'accept all'. We never change this 878 * later on. 879 */ 880 value = apic_read(APIC_TASKPRI); 881 value &= ~APIC_TPRI_MASK; 882 apic_write_around(APIC_TASKPRI, value); 883 884 /* 885 * After a crash, we no longer service the interrupts and a pending 886 * interrupt from previous kernel might still have ISR bit set. 887 * 888 * Most probably by now CPU has serviced that pending interrupt and 889 * it might not have done the ack_APIC_irq() because it thought, 890 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 891 * does not clear the ISR bit and cpu thinks it has already serivced 892 * the interrupt. Hence a vector might get locked. It was noticed 893 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 894 */ 895 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 896 value = apic_read(APIC_ISR + i*0x10); 897 for (j = 31; j >= 0; j--) { 898 if (value & (1<<j)) 899 ack_APIC_irq(); 900 } 901 } 902 903 /* 904 * Now that we are all set up, enable the APIC 905 */ 906 value = apic_read(APIC_SPIV); 907 value &= ~APIC_VECTOR_MASK; 908 /* 909 * Enable APIC 910 */ 911 value |= APIC_SPIV_APIC_ENABLED; 912 913 /* 914 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 915 * certain networking cards. If high frequency interrupts are 916 * happening on a particular IOAPIC pin, plus the IOAPIC routing 917 * entry is masked/unmasked at a high rate as well then sooner or 918 * later IOAPIC line gets 'stuck', no more interrupts are received 919 * from the device. If focus CPU is disabled then the hang goes 920 * away, oh well :-( 921 * 922 * [ This bug can be reproduced easily with a level-triggered 923 * PCI Ne2000 networking cards and PII/PIII processors, dual 924 * BX chipset. ] 925 */ 926 /* 927 * Actually disabling the focus CPU check just makes the hang less 928 * frequent as it makes the interrupt distributon model be more 929 * like LRU than MRU (the short-term load is more even across CPUs). 930 * See also the comment in end_level_ioapic_irq(). --macro 931 */ 932 933 /* Enable focus processor (bit==0) */ 934 value &= ~APIC_SPIV_FOCUS_DISABLED; 935 936 /* 937 * Set spurious IRQ vector 938 */ 939 value |= SPURIOUS_APIC_VECTOR; 940 apic_write_around(APIC_SPIV, value); 941 942 /* 943 * Set up LVT0, LVT1: 944 * 945 * set up through-local-APIC on the BP's LINT0. This is not 946 * strictly necessery in pure symmetric-IO mode, but sometimes 947 * we delegate interrupts to the 8259A. 948 */ 949 /* 950 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 951 */ 952 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 953 if (!smp_processor_id() && (pic_mode || !value)) { 954 value = APIC_DM_EXTINT; 955 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 956 smp_processor_id()); 957 } else { 958 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 959 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 960 smp_processor_id()); 961 } 962 apic_write_around(APIC_LVT0, value); 963 964 /* 965 * only the BP should see the LINT1 NMI signal, obviously. 966 */ 967 if (!smp_processor_id()) 968 value = APIC_DM_NMI; 969 else 970 value = APIC_DM_NMI | APIC_LVT_MASKED; 971 if (!integrated) /* 82489DX */ 972 value |= APIC_LVT_LEVEL_TRIGGER; 973 apic_write_around(APIC_LVT1, value); 974 975 if (integrated && !esr_disable) { /* !82489DX */ 976 maxlvt = lapic_get_maxlvt(); 977 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 978 apic_write(APIC_ESR, 0); 979 oldvalue = apic_read(APIC_ESR); 980 981 /* enables sending errors */ 982 value = ERROR_APIC_VECTOR; 983 apic_write_around(APIC_LVTERR, value); 984 /* 985 * spec says clear errors after enabling vector. 986 */ 987 if (maxlvt > 3) 988 apic_write(APIC_ESR, 0); 989 value = apic_read(APIC_ESR); 990 if (value != oldvalue) 991 apic_printk(APIC_VERBOSE, "ESR value before enabling " 992 "vector: 0x%08lx after: 0x%08lx\n", 993 oldvalue, value); 994 } else { 995 if (esr_disable) 996 /* 997 * Something untraceble is creating bad interrupts on 998 * secondary quads ... for the moment, just leave the 999 * ESR disabled - we can't do anything useful with the 1000 * errors anyway - mbligh 1001 */ 1002 printk(KERN_INFO "Leaving ESR disabled.\n"); 1003 else 1004 printk(KERN_INFO "No ESR for 82489DX.\n"); 1005 } 1006 1007 /* Disable the local apic timer */ 1008 value = apic_read(APIC_LVTT); 1009 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1010 apic_write_around(APIC_LVTT, value); 1011 1012 setup_apic_nmi_watchdog(NULL); 1013 apic_pm_activate(); 1014} 1015 1016/* 1017 * Detect and initialize APIC 1018 */ 1019static int __init detect_init_APIC (void) 1020{ 1021 u32 h, l, features; 1022 1023 /* Disabled by kernel option? */ 1024 if (enable_local_apic < 0) 1025 return -1; 1026 1027 switch (boot_cpu_data.x86_vendor) { 1028 case X86_VENDOR_AMD: 1029 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1030 (boot_cpu_data.x86 == 15)) 1031 break; 1032 goto no_apic; 1033 case X86_VENDOR_INTEL: 1034 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1035 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1036 break; 1037 goto no_apic; 1038 default: 1039 goto no_apic; 1040 } 1041 1042 if (!cpu_has_apic) { 1043 /* 1044 * Over-ride BIOS and try to enable the local APIC only if 1045 * "lapic" specified. 1046 */ 1047 if (enable_local_apic <= 0) { 1048 printk(KERN_INFO "Local APIC disabled by BIOS -- " 1049 "you can enable it with \"lapic\"\n"); 1050 return -1; 1051 } 1052 /* 1053 * Some BIOSes disable the local APIC in the APIC_BASE 1054 * MSR. This can only be done in software for Intel P6 or later 1055 * and AMD K7 (Model > 1) or later. 1056 */ 1057 rdmsr(MSR_IA32_APICBASE, l, h); 1058 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1059 printk(KERN_INFO 1060 "Local APIC disabled by BIOS -- reenabling.\n"); 1061 l &= ~MSR_IA32_APICBASE_BASE; 1062 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1063 wrmsr(MSR_IA32_APICBASE, l, h); 1064 enabled_via_apicbase = 1; 1065 } 1066 } 1067 /* 1068 * The APIC feature bit should now be enabled 1069 * in `cpuid' 1070 */ 1071 features = cpuid_edx(1); 1072 if (!(features & (1 << X86_FEATURE_APIC))) { 1073 printk(KERN_WARNING "Could not enable APIC!\n"); 1074 return -1; 1075 } 1076 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); 1077 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1078 1079 /* The BIOS may have set up the APIC at some other address */ 1080 rdmsr(MSR_IA32_APICBASE, l, h); 1081 if (l & MSR_IA32_APICBASE_ENABLE) 1082 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1083 1084 if (nmi_watchdog != NMI_NONE) 1085 nmi_watchdog = NMI_LOCAL_APIC; 1086 1087 printk(KERN_INFO "Found and enabled local APIC!\n"); 1088 1089 apic_pm_activate(); 1090 1091 return 0; 1092 1093no_apic: 1094 printk(KERN_INFO "No local APIC present or hardware disabled\n"); 1095 return -1; 1096} 1097 1098/** 1099 * init_apic_mappings - initialize APIC mappings 1100 */ 1101void __init init_apic_mappings(void) 1102{ 1103 unsigned long apic_phys; 1104 1105 /* 1106 * If no local APIC can be found then set up a fake all 1107 * zeroes page to simulate the local APIC and another 1108 * one for the IO-APIC. 1109 */ 1110 if (!smp_found_config && detect_init_APIC()) { 1111 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); 1112 apic_phys = __pa(apic_phys); 1113 } else 1114 apic_phys = mp_lapic_addr; 1115 1116 set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 1117 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, 1118 apic_phys); 1119 1120 /* 1121 * Fetch the APIC ID of the BSP in case we have a 1122 * default configuration (or the MP table is broken). 1123 */ 1124 if (boot_cpu_physical_apicid == -1U) 1125 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); 1126 1127#ifdef CONFIG_X86_IO_APIC 1128 { 1129 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; 1130 int i; 1131 1132 for (i = 0; i < nr_ioapics; i++) { 1133 if (smp_found_config) { 1134 ioapic_phys = mp_ioapics[i].mpc_apicaddr; 1135 if (!ioapic_phys) { 1136 printk(KERN_ERR 1137 "WARNING: bogus zero IO-APIC " 1138 "address found in MPTABLE, " 1139 "disabling IO/APIC support!\n"); 1140 smp_found_config = 0; 1141 skip_ioapic_setup = 1; 1142 goto fake_ioapic_page; 1143 } 1144 } else { 1145fake_ioapic_page: 1146 ioapic_phys = (unsigned long) 1147 alloc_bootmem_pages(PAGE_SIZE); 1148 ioapic_phys = __pa(ioapic_phys); 1149 } 1150 set_fixmap_nocache(idx, ioapic_phys); 1151 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", 1152 __fix_to_virt(idx), ioapic_phys); 1153 idx++; 1154 } 1155 } 1156#endif 1157} 1158 1159/* 1160 * This initializes the IO-APIC and APIC hardware if this is 1161 * a UP kernel. 1162 */ 1163int __init APIC_init_uniprocessor (void) 1164{ 1165 if (enable_local_apic < 0) 1166 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); 1167 1168 if (!smp_found_config && !cpu_has_apic) 1169 return -1; 1170 1171 /* 1172 * Complain if the BIOS pretends there is one. 1173 */ 1174 if (!cpu_has_apic && 1175 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1176 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", 1177 boot_cpu_physical_apicid); 1178 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); 1179 return -1; 1180 } 1181 1182 verify_local_APIC(); 1183 1184 connect_bsp_APIC(); 1185 1186 /* 1187 * Hack: In case of kdump, after a crash, kernel might be booting 1188 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1189 * might be zero if read from MP tables. Get it from LAPIC. 1190 */ 1191#ifdef CONFIG_CRASH_DUMP 1192 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); 1193#endif 1194 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); 1195 1196 setup_local_APIC(); 1197 1198#ifdef CONFIG_X86_IO_APIC 1199 if (smp_found_config) 1200 if (!skip_ioapic_setup && nr_ioapics) 1201 setup_IO_APIC(); 1202#endif 1203 setup_boot_clock(); 1204 1205 return 0; 1206} 1207 1208/* 1209 * APIC command line parameters 1210 */ 1211static int __init parse_lapic(char *arg) 1212{ 1213 enable_local_apic = 1; 1214 return 0; 1215} 1216early_param("lapic", parse_lapic); 1217 1218static int __init parse_nolapic(char *arg) 1219{ 1220 enable_local_apic = -1; 1221 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); 1222 return 0; 1223} 1224early_param("nolapic", parse_nolapic); 1225 1226static int __init parse_disable_lapic_timer(char *arg) 1227{ 1228 local_apic_timer_disabled = 1; 1229 return 0; 1230} 1231early_param("nolapic_timer", parse_disable_lapic_timer); 1232 1233static int __init parse_lapic_timer_c2_ok(char *arg) 1234{ 1235 local_apic_timer_c2_ok = 1; 1236 return 0; 1237} 1238early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 1239 1240static int __init apic_set_verbosity(char *str) 1241{ 1242 if (strcmp("debug", str) == 0) 1243 apic_verbosity = APIC_DEBUG; 1244 else if (strcmp("verbose", str) == 0) 1245 apic_verbosity = APIC_VERBOSE; 1246 return 1; 1247} 1248 1249__setup("apic=", apic_set_verbosity); 1250 1251 1252/* 1253 * Local APIC interrupts 1254 */ 1255 1256/* 1257 * This interrupt should _never_ happen with our APIC/SMP architecture 1258 */ 1259void smp_spurious_interrupt(struct pt_regs *regs) 1260{ 1261 unsigned long v; 1262 1263 irq_enter(); 1264 /* 1265 * Check if this really is a spurious interrupt and ACK it 1266 * if it is a vectored one. Just in case... 1267 * Spurious interrupts should not be ACKed. 1268 */ 1269 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1270 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1271 ack_APIC_irq(); 1272 1273 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1274 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " 1275 "should never happen.\n", smp_processor_id()); 1276 irq_exit(); 1277} 1278 1279/* 1280 * This interrupt should never happen with our APIC/SMP architecture 1281 */ 1282void smp_error_interrupt(struct pt_regs *regs) 1283{ 1284 unsigned long v, v1; 1285 1286 irq_enter(); 1287 /* First tickle the hardware, only then report what went on. -- REW */ 1288 v = apic_read(APIC_ESR); 1289 apic_write(APIC_ESR, 0); 1290 v1 = apic_read(APIC_ESR); 1291 ack_APIC_irq(); 1292 atomic_inc(&irq_err_count); 1293 1294 /* Here is what the APIC error bits mean: 1295 0: Send CS error 1296 1: Receive CS error 1297 2: Send accept error 1298 3: Receive accept error 1299 4: Reserved 1300 5: Send illegal vector 1301 6: Received illegal vector 1302 7: Illegal register address 1303 */ 1304 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", 1305 smp_processor_id(), v , v1); 1306 irq_exit(); 1307} 1308 1309/* 1310 * Initialize APIC interrupts 1311 */ 1312void __init apic_intr_init(void) 1313{ 1314#ifdef CONFIG_SMP 1315 smp_intr_init(); 1316#endif 1317 /* self generated IPI for local APIC timer */ 1318 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); 1319 1320 /* IPI vectors for APIC spurious and error interrupts */ 1321 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); 1322 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); 1323 1324 /* thermal monitor LVT interrupt */ 1325#ifdef CONFIG_X86_MCE_P4THERMAL 1326 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); 1327#endif 1328} 1329 1330/** 1331 * connect_bsp_APIC - attach the APIC to the interrupt system 1332 */ 1333void __init connect_bsp_APIC(void) 1334{ 1335 if (pic_mode) { 1336 /* 1337 * Do not trust the local APIC being empty at bootup. 1338 */ 1339 clear_local_APIC(); 1340 /* 1341 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1342 * local APIC to INT and NMI lines. 1343 */ 1344 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1345 "enabling APIC mode.\n"); 1346 outb(0x70, 0x22); 1347 outb(0x01, 0x23); 1348 } 1349 enable_apic_mode(); 1350} 1351 1352/** 1353 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1354 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1355 * 1356 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1357 * APIC is disabled. 1358 */ 1359void disconnect_bsp_APIC(int virt_wire_setup) 1360{ 1361 if (pic_mode) { 1362 /* 1363 * Put the board back into PIC mode (has an effect only on 1364 * certain older boards). Note that APIC interrupts, including 1365 * IPIs, won't work beyond this point! The only exception are 1366 * INIT IPIs. 1367 */ 1368 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1369 "entering PIC mode.\n"); 1370 outb(0x70, 0x22); 1371 outb(0x00, 0x23); 1372 } else { 1373 /* Go back to Virtual Wire compatibility mode */ 1374 unsigned long value; 1375 1376 /* For the spurious interrupt use vector F, and enable it */ 1377 value = apic_read(APIC_SPIV); 1378 value &= ~APIC_VECTOR_MASK; 1379 value |= APIC_SPIV_APIC_ENABLED; 1380 value |= 0xf; 1381 apic_write_around(APIC_SPIV, value); 1382 1383 if (!virt_wire_setup) { 1384 /* 1385 * For LVT0 make it edge triggered, active high, 1386 * external and enabled 1387 */ 1388 value = apic_read(APIC_LVT0); 1389 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1390 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1391 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); 1392 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1393 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1394 apic_write_around(APIC_LVT0, value); 1395 } else { 1396 /* Disable LVT0 */ 1397 apic_write_around(APIC_LVT0, APIC_LVT_MASKED); 1398 } 1399 1400 /* 1401 * For LVT1 make it edge triggered, active high, nmi and 1402 * enabled 1403 */ 1404 value = apic_read(APIC_LVT1); 1405 value &= ~( 1406 APIC_MODE_MASK | APIC_SEND_PENDING | 1407 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1408 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1409 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1410 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1411 apic_write_around(APIC_LVT1, value); 1412 } 1413} 1414 1415/* 1416 * Power management 1417 */ 1418#ifdef CONFIG_PM 1419 1420static struct { 1421 int active; 1422 /* r/w apic fields */ 1423 unsigned int apic_id; 1424 unsigned int apic_taskpri; 1425 unsigned int apic_ldr; 1426 unsigned int apic_dfr; 1427 unsigned int apic_spiv; 1428 unsigned int apic_lvtt; 1429 unsigned int apic_lvtpc; 1430 unsigned int apic_lvt0; 1431 unsigned int apic_lvt1; 1432 unsigned int apic_lvterr; 1433 unsigned int apic_tmict; 1434 unsigned int apic_tdcr; 1435 unsigned int apic_thmr; 1436} apic_pm_state; 1437 1438static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1439{ 1440 unsigned long flags; 1441 int maxlvt; 1442 1443 if (!apic_pm_state.active) 1444 return 0; 1445 1446 maxlvt = lapic_get_maxlvt(); 1447 1448 apic_pm_state.apic_id = apic_read(APIC_ID); 1449 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 1450 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 1451 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 1452 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 1453 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 1454 if (maxlvt >= 4) 1455 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 1456 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 1457 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 1458 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 1459 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 1460 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 1461#ifdef CONFIG_X86_MCE_P4THERMAL 1462 if (maxlvt >= 5) 1463 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 1464#endif 1465 1466 local_irq_save(flags); 1467 disable_local_APIC(); 1468 local_irq_restore(flags); 1469 return 0; 1470} 1471 1472static int lapic_resume(struct sys_device *dev) 1473{ 1474 unsigned int l, h; 1475 unsigned long flags; 1476 int maxlvt; 1477 1478 if (!apic_pm_state.active) 1479 return 0; 1480 1481 maxlvt = lapic_get_maxlvt(); 1482 1483 local_irq_save(flags); 1484 1485 rdmsr(MSR_IA32_APICBASE, l, h); 1486 l &= ~MSR_IA32_APICBASE_BASE; 1487 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 1488 wrmsr(MSR_IA32_APICBASE, l, h); 1489 1490 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 1491 apic_write(APIC_ID, apic_pm_state.apic_id); 1492 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 1493 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 1494 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 1495 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 1496 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 1497 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 1498#ifdef CONFIG_X86_MCE_P4THERMAL 1499 if (maxlvt >= 5) 1500 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 1501#endif 1502 if (maxlvt >= 4) 1503 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 1504 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 1505 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 1506 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 1507 apic_write(APIC_ESR, 0); 1508 apic_read(APIC_ESR); 1509 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 1510 apic_write(APIC_ESR, 0); 1511 apic_read(APIC_ESR); 1512 local_irq_restore(flags); 1513 return 0; 1514} 1515 1516/* 1517 * This device has no shutdown method - fully functioning local APICs 1518 * are needed on every CPU up until machine_halt/restart/poweroff. 1519 */ 1520 1521static struct sysdev_class lapic_sysclass = { 1522 set_kset_name("lapic"), 1523 .resume = lapic_resume, 1524 .suspend = lapic_suspend, 1525}; 1526 1527static struct sys_device device_lapic = { 1528 .id = 0, 1529 .cls = &lapic_sysclass, 1530}; 1531 1532static void __devinit apic_pm_activate(void) 1533{ 1534 apic_pm_state.active = 1; 1535} 1536 1537static int __init init_lapic_sysfs(void) 1538{ 1539 int error; 1540 1541 if (!cpu_has_apic) 1542 return 0; 1543 1544 error = sysdev_class_register(&lapic_sysclass); 1545 if (!error) 1546 error = sysdev_register(&device_lapic); 1547 return error; 1548} 1549device_initcall(init_lapic_sysfs); 1550 1551#else /* CONFIG_PM */ 1552 1553static void apic_pm_activate(void) { } 1554 1555#endif /* CONFIG_PM */ 1556