1 2 3/* Just to be certain the config file is included, we include it here 4 * explicitely instead of depending on it being included in the file that 5 * uses this code. 6 */ 7 8 9 ;; WARNING! The registers r8 and r9 are used as parameters carrying 10 ;; information from the decompressor (if the kernel was compressed). 11 ;; They should not be used in the code below. 12 13#ifndef CONFIG_SVINTO_SIM 14 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0 15 move.d $r0, [R_WAITSTATES] 16 17 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0 18 move.d $r0, [R_BUS_CONFIG] 19 20#ifndef CONFIG_ETRAX_SDRAM 21 move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0 22 move.d $r0, [R_DRAM_CONFIG] 23 24 move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0 25 move.d $r0, [R_DRAM_TIMING] 26#else 27 ;; Samsung SDRAMs seem to require to be initialized twice to work properly. 28 moveq 2, $r6 29_sdram_init: 30 31 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization 32 33 ; Bank configuration 34 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0 35 move.d $r0, [R_SDRAM_CONFIG] 36 37 ; Calculate value of mrs_data 38 ; CAS latency = 2 && bus_width = 32 => 0x40 39 ; CAS latency = 3 && bus_width = 32 => 0x60 40 ; CAS latency = 2 && bus_width = 16 => 0x20 41 ; CAS latency = 3 && bus_width = 16 => 0x30 42 43 ; Check if value is already supplied in kernel config 44 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2 45 and.d 0x00ff0000, $r2 46 bne _set_timing 47 lsrq 16, $r2 48 49 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2 50 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 51 move.d $r1, $r3 52 and.d 0x03, $r1 ; Get CAS latency 53 and.d 0x1000, $r3 ; 50 or 100 MHz? 54 beq _speed_50 55 nop 56_speed_100: 57 cmp.d 0x00, $r1 ; CAS latency = 2? 58 beq _bw_check 59 nop 60 or.d 0x20, $r2 ; CAS latency = 3 61 ba _bw_check 62 nop 63_speed_50: 64 cmp.d 0x01, $r1 ; CAS latency = 2? 65 beq _bw_check 66 nop 67 or.d 0x20, $r2 ; CAS latency = 3 68_bw_check: 69 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1 70 and.d 0x800000, $r1 ; DRAM width is bit 23 71 bne _set_timing 72 nop 73 lsrq 1, $r2 ; 16 bits. Shift down value. 74 75 ; Set timing parameters. Starts master clock 76_set_timing: 77 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 78 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0 79 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set 80 move.d $r1, $r5 81 or.d 0x0000c000, $r1 ; ref = disable 82 lslq 16, $r2 ; mrs data starts at bit 16 83 or.d $r2, $r1 84 move.d $r1, [R_SDRAM_TIMING] 85 86 ; Wait 200us 87 move.d 10000, $r2 881: bne 1b 89 subq 1, $r2 90 91 ; Issue initialization command sequence 92 move.d _sdram_commands_start, $r2 93 and.d 0x000fffff, $r2 ; Make sure commands are read from flash 94 move.d _sdram_commands_end, $r3 95 and.d 0x000fffff, $r3 961: clear.d $r4 97 move.b [$r2+], $r4 98 lslq 9, $r4 ; Command starts at bit 9 99 or.d $r1, $r4 100 move.d $r4, [R_SDRAM_TIMING] 101 nop ; Wait five nop cycles between each command 102 nop 103 nop 104 nop 105 nop 106 cmp.d $r2, $r3 107 bne 1b 108 nop 109 move.d $r5, [R_SDRAM_TIMING] 110 subq 1, $r6 111 bne _sdram_init 112 nop 113 ba _sdram_commands_end 114 nop 115 116_sdram_commands_start: 117 .byte 3 ; Precharge 118 .byte 0 ; nop 119 .byte 2 ; refresh 120 .byte 0 ; nop 121 .byte 2 ; refresh 122 .byte 0 ; nop 123 .byte 2 ; refresh 124 .byte 0 ; nop 125 .byte 2 ; refresh 126 .byte 0 ; nop 127 .byte 2 ; refresh 128 .byte 0 ; nop 129 .byte 2 ; refresh 130 .byte 0 ; nop 131 .byte 2 ; refresh 132 .byte 0 ; nop 133 .byte 2 ; refresh 134 .byte 0 ; nop 135 .byte 1 ; mrs 136 .byte 0 ; nop 137_sdram_commands_end: 138#endif 139#endif 140