1/*
2 * File:         arch/blackfin/mach-common/ints-priority-sc.c
3 * Based on:
4 * Author:
5 *
6 * Created:      ?
7 * Description:  Set up the interrupt priorities
8 *
9 * Modified:
10 *               1996 Roman Zippel
11 *               1999 D. Jeff Dionne <jeff@uclinux.org>
12 *               2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 *               2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 *               2003 Metrowerks/Motorola
15 *               2003 Bas Vermeulen <bas@buyways.nl>
16 *               Copyright 2004-2006 Analog Devices Inc.
17 *
18 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
61unsigned long irq_flags = 0;
62
63/* The number of spurious interrupts */
64atomic_t num_spurious;
65
66struct ivgx {
67	/* irq number for request_irq, available in mach-bf533/irq.h */
68	int irqno;
69	/* corresponding bit in the SIC_ISR register */
70	int isrflag;
71} ivg_table[NR_PERI_INTS];
72
73struct ivg_slice {
74	/* position of first irq in ivg_table for given ivg */
75	struct ivgx *ifirst;
76	struct ivgx *istop;
77} ivg7_13[IVG13 - IVG7 + 1];
78
79static void search_IAR(void);
80
81/*
82 * Search SIC_IAR and fill tables with the irqvalues
83 * and their positions in the SIC_ISR register.
84 */
85static void __init search_IAR(void)
86{
87	unsigned ivg, irq_pos = 0;
88	for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
89		int irqn;
90
91		ivg7_13[ivg].istop = ivg7_13[ivg].ifirst =
92		    &ivg_table[irq_pos];
93
94		for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
95			int iar_shift = (irqn & 7) * 4;
96			if (ivg ==
97			    (0xf &
98			     bfin_read32((unsigned long *) SIC_IAR0 +
99					 (irqn >> 3)) >> iar_shift)) {
100				ivg_table[irq_pos].irqno = IVG7 + irqn;
101				ivg_table[irq_pos].isrflag = 1 << irqn;
102				ivg7_13[ivg].istop++;
103				irq_pos++;
104			}
105		}
106	}
107}
108
109/*
110 * This is for BF533 internal IRQs
111 */
112
113static void ack_noop(unsigned int irq)
114{
115	/* Dummy function.  */
116}
117
118static void bfin_core_mask_irq(unsigned int irq)
119{
120	irq_flags &= ~(1 << irq);
121	if (!irqs_disabled())
122		local_irq_enable();
123}
124
125static void bfin_core_unmask_irq(unsigned int irq)
126{
127	irq_flags |= 1 << irq;
128	/*
129	 * If interrupts are enabled, IMASK must contain the same value
130	 * as irq_flags.  Make sure that invariant holds.  If interrupts
131	 * are currently disabled we need not do anything; one of the
132	 * callers will take care of setting IMASK to the proper value
133	 * when reenabling interrupts.
134	 * local_irq_enable just does "STI irq_flags", so it's exactly
135	 * what we need.
136	 */
137	if (!irqs_disabled())
138		local_irq_enable();
139	return;
140}
141
142static void bfin_internal_mask_irq(unsigned int irq)
143{
144	bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145			     ~(1 << (irq - (IRQ_CORETMR + 1))));
146	SSYNC();
147}
148
149static void bfin_internal_unmask_irq(unsigned int irq)
150{
151	bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
152			     (1 << (irq - (IRQ_CORETMR + 1))));
153	SSYNC();
154}
155
156static struct irq_chip bfin_core_irqchip = {
157	.ack = ack_noop,
158	.mask = bfin_core_mask_irq,
159	.unmask = bfin_core_unmask_irq,
160};
161
162static struct irq_chip bfin_internal_irqchip = {
163	.ack = ack_noop,
164	.mask = bfin_internal_mask_irq,
165	.unmask = bfin_internal_unmask_irq,
166};
167
168#ifdef BF537_GENERIC_ERROR_INT_DEMUX
169static int error_int_mask;
170
171static void bfin_generic_error_ack_irq(unsigned int irq)
172{
173
174}
175
176static void bfin_generic_error_mask_irq(unsigned int irq)
177{
178	error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
179
180	if (!error_int_mask) {
181		local_irq_disable();
182		bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
183				     ~(1 <<
184				       (IRQ_GENERIC_ERROR -
185					(IRQ_CORETMR + 1))));
186		SSYNC();
187		local_irq_enable();
188	}
189}
190
191static void bfin_generic_error_unmask_irq(unsigned int irq)
192{
193	local_irq_disable();
194	bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
195			     (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
196	SSYNC();
197	local_irq_enable();
198
199	error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
200}
201
202static struct irq_chip bfin_generic_error_irqchip = {
203	.ack = bfin_generic_error_ack_irq,
204	.mask = bfin_generic_error_mask_irq,
205	.unmask = bfin_generic_error_unmask_irq,
206};
207
208static void bfin_demux_error_irq(unsigned int int_err_irq,
209				  struct irq_desc *intb_desc)
210{
211	int irq = 0;
212
213	SSYNC();
214
215#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
216	if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
217		irq = IRQ_MAC_ERROR;
218	else
219#endif
220	if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
221		irq = IRQ_SPORT0_ERROR;
222	else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
223		irq = IRQ_SPORT1_ERROR;
224	else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
225		irq = IRQ_PPI_ERROR;
226	else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
227		irq = IRQ_CAN_ERROR;
228	else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
229		irq = IRQ_SPI_ERROR;
230	else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
231		 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
232		irq = IRQ_UART0_ERROR;
233	else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
234		 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
235		irq = IRQ_UART1_ERROR;
236
237	if (irq) {
238		if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
239			struct irq_desc *desc = irq_desc + irq;
240			desc->handle_irq(irq, desc);
241		} else {
242
243			switch (irq) {
244			case IRQ_PPI_ERROR:
245				bfin_write_PPI_STATUS(PPI_ERR_MASK);
246				break;
247#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
248			case IRQ_MAC_ERROR:
249				bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
250				break;
251#endif
252			case IRQ_SPORT0_ERROR:
253				bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
254				break;
255
256			case IRQ_SPORT1_ERROR:
257				bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
258				break;
259
260			case IRQ_CAN_ERROR:
261				bfin_write_CAN_GIS(CAN_ERR_MASK);
262				break;
263
264			case IRQ_SPI_ERROR:
265				bfin_write_SPI_STAT(SPI_ERR_MASK);
266				break;
267
268			default:
269				break;
270			}
271
272			pr_debug("IRQ %d:"
273				" MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
274				irq);
275		}
276	} else
277		printk(KERN_ERR
278		       "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
279		       " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
280		       __FUNCTION__, __FILE__, __LINE__);
281
282
283}
284#endif				/* BF537_GENERIC_ERROR_INT_DEMUX */
285
286#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
287
288static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
289static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
290
291static void bfin_gpio_ack_irq(unsigned int irq)
292{
293	u16 gpionr = irq - IRQ_PF0;
294
295	if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
296		set_gpio_data(gpionr, 0);
297		SSYNC();
298	}
299}
300
301static void bfin_gpio_mask_ack_irq(unsigned int irq)
302{
303	u16 gpionr = irq - IRQ_PF0;
304
305	if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
306		set_gpio_data(gpionr, 0);
307		SSYNC();
308	}
309
310	set_gpio_maska(gpionr, 0);
311	SSYNC();
312}
313
314static void bfin_gpio_mask_irq(unsigned int irq)
315{
316	set_gpio_maska(irq - IRQ_PF0, 0);
317	SSYNC();
318}
319
320static void bfin_gpio_unmask_irq(unsigned int irq)
321{
322	set_gpio_maska(irq - IRQ_PF0, 1);
323	SSYNC();
324}
325
326static unsigned int bfin_gpio_irq_startup(unsigned int irq)
327{
328	unsigned int ret;
329	u16 gpionr = irq - IRQ_PF0;
330
331	if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
332		ret = gpio_request(gpionr, NULL);
333		if (ret)
334			return ret;
335	}
336
337	gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
338	bfin_gpio_unmask_irq(irq);
339
340	return ret;
341}
342
343static void bfin_gpio_irq_shutdown(unsigned int irq)
344{
345	bfin_gpio_mask_irq(irq);
346	gpio_free(irq - IRQ_PF0);
347	gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
348}
349
350static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
351{
352
353	unsigned int ret;
354	u16 gpionr = irq - IRQ_PF0;
355
356	if (type == IRQ_TYPE_PROBE) {
357		/* only probe unenabled GPIO interrupt lines */
358		if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
359			return 0;
360		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
361	}
362
363	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
364	            IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
365	{
366		if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
367			ret = gpio_request(gpionr, NULL);
368			if (ret)
369				return ret;
370		}
371
372		gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
373	} else {
374		gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
375		return 0;
376	}
377
378	set_gpio_dir(gpionr, 0);
379	set_gpio_inen(gpionr, 1);
380
381	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
382		gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
383		set_gpio_edge(gpionr, 1);
384	} else {
385		set_gpio_edge(gpionr, 0);
386		gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
387	}
388
389	if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
390	    == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
391		set_gpio_both(gpionr, 1);
392	else
393		set_gpio_both(gpionr, 0);
394
395	if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
396		set_gpio_polar(gpionr, 1);	/* low or falling edge denoted by one */
397	else
398		set_gpio_polar(gpionr, 0);	/* high or rising edge denoted by zero */
399
400	SSYNC();
401
402	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
403		set_irq_handler(irq, handle_edge_irq);
404	else
405		set_irq_handler(irq, handle_level_irq);
406
407	return 0;
408}
409
410
411static struct irq_chip bfin_gpio_irqchip = {
412	.ack = bfin_gpio_ack_irq,
413	.mask = bfin_gpio_mask_irq,
414	.mask_ack = bfin_gpio_mask_ack_irq,
415	.unmask = bfin_gpio_unmask_irq,
416	.set_type = bfin_gpio_irq_type,
417	.startup = bfin_gpio_irq_startup,
418	.shutdown = bfin_gpio_irq_shutdown
419};
420
421static void bfin_demux_gpio_irq(unsigned int intb_irq,
422				 struct irq_desc *intb_desc)
423{
424	u16 i;
425
426	for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=16) {
427		int irq = IRQ_PF0 + i;
428		int flag_d = get_gpiop_data(i);
429		int mask =
430			flag_d & (gpio_enabled[gpio_bank(i)] &
431			      get_gpiop_maska(i));
432
433		while (mask) {
434			if (mask & 1) {
435				struct irq_desc *desc = irq_desc + irq;
436				desc->handle_irq(irq, desc);
437			}
438			irq++;
439			mask >>= 1;
440		}
441	}
442}
443
444#endif				/* CONFIG_IRQCHIP_DEMUX_GPIO */
445
446/*
447 * This function should be called during kernel startup to initialize
448 * the BFin IRQ handling routines.
449 */
450int __init init_arch_irq(void)
451{
452	int irq;
453	unsigned long ilat = 0;
454	/*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
455	bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
456	SSYNC();
457
458	local_irq_disable();
459
460#ifndef CONFIG_KGDB
461	bfin_write_EVT0(evt_emulation);
462#endif
463	bfin_write_EVT2(evt_evt2);
464	bfin_write_EVT3(trap);
465	bfin_write_EVT5(evt_ivhw);
466	bfin_write_EVT6(evt_timer);
467	bfin_write_EVT7(evt_evt7);
468	bfin_write_EVT8(evt_evt8);
469	bfin_write_EVT9(evt_evt9);
470	bfin_write_EVT10(evt_evt10);
471	bfin_write_EVT11(evt_evt11);
472	bfin_write_EVT12(evt_evt12);
473	bfin_write_EVT13(evt_evt13);
474	bfin_write_EVT14(evt14_softirq);
475	bfin_write_EVT15(evt_system_call);
476	CSYNC();
477
478	for (irq = 0; irq < SYS_IRQS; irq++) {
479		if (irq <= IRQ_CORETMR)
480			set_irq_chip(irq, &bfin_core_irqchip);
481		else
482			set_irq_chip(irq, &bfin_internal_irqchip);
483#ifdef BF537_GENERIC_ERROR_INT_DEMUX
484		if (irq != IRQ_GENERIC_ERROR) {
485#endif
486
487#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
488			if ((irq != IRQ_PROG_INTA) /*PORT F & G MASK_A Interrupt*/
489# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || \
490	defined(CONFIG_BFIN_MAC_MODULE))
491				&& (irq != IRQ_MAC_RX) /*PORT H MASK_A Interrupt*/
492# endif
493			    ) {
494#endif
495				set_irq_handler(irq, handle_simple_irq);
496#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
497			} else {
498				set_irq_chained_handler(irq,
499							bfin_demux_gpio_irq);
500			}
501#endif
502
503#ifdef BF537_GENERIC_ERROR_INT_DEMUX
504		} else {
505			set_irq_handler(irq, bfin_demux_error_irq);
506		}
507#endif
508	}
509#ifdef BF537_GENERIC_ERROR_INT_DEMUX
510	for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
511		set_irq_chip(irq, &bfin_generic_error_irqchip);
512		set_irq_handler(irq, handle_level_irq);
513	}
514#endif
515
516#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
517	for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
518		set_irq_chip(irq, &bfin_gpio_irqchip);
519		/* if configured as edge, then will be changed to do_edge_IRQ */
520		set_irq_handler(irq, handle_level_irq);
521	}
522#endif
523	bfin_write_IMASK(0);
524	CSYNC();
525	ilat = bfin_read_ILAT();
526	CSYNC();
527	bfin_write_ILAT(ilat);
528	CSYNC();
529
530	printk(KERN_INFO
531	       "Configuring Blackfin Priority Driven Interrupts\n");
532	program_IAR();
533	/* Therefore it's better to setup IARs before interrupts enabled */
534	search_IAR();
535
536	/* Enable interrupts IVG7-15 */
537	irq_flags = irq_flags | IMASK_IVG15 |
538	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
539	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 |
540	    IMASK_IVGHW;
541
542	return 0;
543}
544
545#ifdef CONFIG_DO_IRQ_L1
546void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text));
547#endif
548
549void do_irq(int vec, struct pt_regs *fp)
550{
551	if (vec == EVT_IVTMR_P) {
552		vec = IRQ_CORETMR;
553	} else {
554		struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
555		struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
556		unsigned long sic_status;
557
558		SSYNC();
559		sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
560
561		for (;; ivg++) {
562			if (ivg >= ivg_stop) {
563				atomic_inc(&num_spurious);
564				return;
565			} else if (sic_status & ivg->isrflag)
566				break;
567		}
568		vec = ivg->irqno;
569	}
570	asm_do_IRQ(vec, fp);
571
572#ifdef CONFIG_KGDB
573	kgdb_process_breakpoint();
574#endif
575}
576