1/* 2 * linux/arch/arm/mm/mmu.c 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#include <linux/module.h> 11#include <linux/kernel.h> 12#include <linux/errno.h> 13#include <linux/init.h> 14#include <linux/bootmem.h> 15#include <linux/mman.h> 16#include <linux/nodemask.h> 17 18#include <asm/mach-types.h> 19#include <asm/setup.h> 20#include <asm/sizes.h> 21#include <asm/tlb.h> 22 23#include <asm/mach/arch.h> 24#include <asm/mach/map.h> 25 26#include "mm.h" 27 28DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 29 30extern void _stext, _etext, __data_start, _end; 31extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 32 33/* 34 * empty_zero_page is a special page that is used for 35 * zero-initialized data and COW. 36 */ 37struct page *empty_zero_page; 38 39/* 40 * The pmd table for the upper-most set of pages. 41 */ 42pmd_t *top_pmd; 43 44#define CPOLICY_UNCACHED 0 45#define CPOLICY_BUFFERED 1 46#define CPOLICY_WRITETHROUGH 2 47#define CPOLICY_WRITEBACK 3 48#define CPOLICY_WRITEALLOC 4 49 50static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 51static unsigned int ecc_mask __initdata = 0; 52pgprot_t pgprot_user; 53pgprot_t pgprot_kernel; 54 55EXPORT_SYMBOL(pgprot_user); 56EXPORT_SYMBOL(pgprot_kernel); 57 58struct cachepolicy { 59 const char policy[16]; 60 unsigned int cr_mask; 61 unsigned int pmd; 62 unsigned int pte; 63}; 64 65static struct cachepolicy cache_policies[] __initdata = { 66 { 67 .policy = "uncached", 68 .cr_mask = CR_W|CR_C, 69 .pmd = PMD_SECT_UNCACHED, 70 .pte = 0, 71 }, { 72 .policy = "buffered", 73 .cr_mask = CR_C, 74 .pmd = PMD_SECT_BUFFERED, 75 .pte = PTE_BUFFERABLE, 76 }, { 77 .policy = "writethrough", 78 .cr_mask = 0, 79 .pmd = PMD_SECT_WT, 80 .pte = PTE_CACHEABLE, 81 }, { 82 .policy = "writeback", 83 .cr_mask = 0, 84 .pmd = PMD_SECT_WB, 85 .pte = PTE_BUFFERABLE|PTE_CACHEABLE, 86 }, { 87 .policy = "writealloc", 88 .cr_mask = 0, 89 .pmd = PMD_SECT_WBWA, 90 .pte = PTE_BUFFERABLE|PTE_CACHEABLE, 91 } 92}; 93 94/* 95 * These are useful for identifying cache coherency 96 * problems by allowing the cache or the cache and 97 * writebuffer to be turned off. (Note: the write 98 * buffer should not be on and the cache off). 99 */ 100static void __init early_cachepolicy(char **p) 101{ 102 int i; 103 104 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 105 int len = strlen(cache_policies[i].policy); 106 107 if (memcmp(*p, cache_policies[i].policy, len) == 0) { 108 cachepolicy = i; 109 cr_alignment &= ~cache_policies[i].cr_mask; 110 cr_no_alignment &= ~cache_policies[i].cr_mask; 111 *p += len; 112 break; 113 } 114 } 115 if (i == ARRAY_SIZE(cache_policies)) 116 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 117 flush_cache_all(); 118 set_cr(cr_alignment); 119} 120__early_param("cachepolicy=", early_cachepolicy); 121 122static void __init early_nocache(char **__unused) 123{ 124 char *p = "buffered"; 125 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); 126 early_cachepolicy(&p); 127} 128__early_param("nocache", early_nocache); 129 130static void __init early_nowrite(char **__unused) 131{ 132 char *p = "uncached"; 133 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); 134 early_cachepolicy(&p); 135} 136__early_param("nowb", early_nowrite); 137 138static void __init early_ecc(char **p) 139{ 140 if (memcmp(*p, "on", 2) == 0) { 141 ecc_mask = PMD_PROTECTION; 142 *p += 2; 143 } else if (memcmp(*p, "off", 3) == 0) { 144 ecc_mask = 0; 145 *p += 3; 146 } 147} 148__early_param("ecc=", early_ecc); 149 150static int __init noalign_setup(char *__unused) 151{ 152 cr_alignment &= ~CR_A; 153 cr_no_alignment &= ~CR_A; 154 set_cr(cr_alignment); 155 return 1; 156} 157__setup("noalign", noalign_setup); 158 159#ifndef CONFIG_SMP 160void adjust_cr(unsigned long mask, unsigned long set) 161{ 162 unsigned long flags; 163 164 mask &= ~CR_A; 165 166 set &= mask; 167 168 local_irq_save(flags); 169 170 cr_no_alignment = (cr_no_alignment & ~mask) | set; 171 cr_alignment = (cr_alignment & ~mask) | set; 172 173 set_cr((get_cr() & ~mask) | set); 174 175 local_irq_restore(flags); 176} 177#endif 178 179#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE 180#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE 181 182static struct mem_type mem_types[] = { 183 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 184 .prot_pte = PROT_PTE_DEVICE, 185 .prot_l1 = PMD_TYPE_TABLE, 186 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED, 187 .domain = DOMAIN_IO, 188 }, 189 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 190 .prot_pte = PROT_PTE_DEVICE, 191 .prot_pte_ext = PTE_EXT_TEX(2), 192 .prot_l1 = PMD_TYPE_TABLE, 193 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2), 194 .domain = DOMAIN_IO, 195 }, 196 [MT_DEVICE_CACHED] = { /* ioremap_cached */ 197 .prot_pte = PROT_PTE_DEVICE | L_PTE_CACHEABLE | L_PTE_BUFFERABLE, 198 .prot_l1 = PMD_TYPE_TABLE, 199 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 200 .domain = DOMAIN_IO, 201 }, 202 [MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */ 203 .prot_pte = PROT_PTE_DEVICE, 204 .prot_l1 = PMD_TYPE_TABLE, 205 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE | 206 PMD_SECT_TEX(1), 207 .domain = DOMAIN_IO, 208 }, 209 [MT_CACHECLEAN] = { 210 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 211 .domain = DOMAIN_KERNEL, 212 }, 213 [MT_MINICLEAN] = { 214 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 215 .domain = DOMAIN_KERNEL, 216 }, 217 [MT_LOW_VECTORS] = { 218 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 219 L_PTE_EXEC, 220 .prot_l1 = PMD_TYPE_TABLE, 221 .domain = DOMAIN_USER, 222 }, 223 [MT_HIGH_VECTORS] = { 224 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 225 L_PTE_USER | L_PTE_EXEC, 226 .prot_l1 = PMD_TYPE_TABLE, 227 .domain = DOMAIN_USER, 228 }, 229 [MT_MEMORY] = { 230 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 231 .domain = DOMAIN_KERNEL, 232 }, 233 [MT_ROM] = { 234 .prot_sect = PMD_TYPE_SECT, 235 .domain = DOMAIN_KERNEL, 236 }, 237}; 238 239const struct mem_type *get_mem_type(unsigned int type) 240{ 241 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 242} 243 244/* 245 * Adjust the PMD section entries according to the CPU in use. 246 */ 247static void __init build_mem_type_table(void) 248{ 249 struct cachepolicy *cp; 250 unsigned int cr = get_cr(); 251 unsigned int user_pgprot, kern_pgprot; 252 int cpu_arch = cpu_architecture(); 253 int i; 254 255#if defined(CONFIG_CPU_DCACHE_DISABLE) 256 if (cachepolicy > CPOLICY_BUFFERED) 257 cachepolicy = CPOLICY_BUFFERED; 258#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 259 if (cachepolicy > CPOLICY_WRITETHROUGH) 260 cachepolicy = CPOLICY_WRITETHROUGH; 261#endif 262 if (cpu_arch < CPU_ARCH_ARMv5) { 263 if (cachepolicy >= CPOLICY_WRITEALLOC) 264 cachepolicy = CPOLICY_WRITEBACK; 265 ecc_mask = 0; 266 } 267 268 /* 269 * ARMv5 and lower, bit 4 must be set for page tables. 270 * (was: cache "update-able on write" bit on ARM610) 271 * However, Xscale cores require this bit to be cleared. 272 */ 273 if (cpu_is_xscale()) { 274 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 275 mem_types[i].prot_sect &= ~PMD_BIT4; 276 mem_types[i].prot_l1 &= ~PMD_BIT4; 277 } 278 } else if (cpu_arch < CPU_ARCH_ARMv6) { 279 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 280 if (mem_types[i].prot_l1) 281 mem_types[i].prot_l1 |= PMD_BIT4; 282 if (mem_types[i].prot_sect) 283 mem_types[i].prot_sect |= PMD_BIT4; 284 } 285 } 286 287 cp = &cache_policies[cachepolicy]; 288 kern_pgprot = user_pgprot = cp->pte; 289 290 /* 291 * Enable CPU-specific coherency if supported. 292 * (Only available on XSC3 at the moment.) 293 */ 294 if (arch_is_coherent()) { 295 if (cpu_is_xsc3()) { 296 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 297 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 298 } 299 } 300 301 /* 302 * ARMv6 and above have extended page tables. 303 */ 304 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 305 /* 306 * Mark cache clean areas and XIP ROM read only 307 * from SVC mode and no access from userspace. 308 */ 309 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 310 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 311 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 312 313 /* 314 * Mark the device area as "shared device" 315 */ 316 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE; 317 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 318 319#ifdef CONFIG_SMP 320 /* 321 * Mark memory with the "shared" attribute for SMP systems 322 */ 323 user_pgprot |= L_PTE_SHARED; 324 kern_pgprot |= L_PTE_SHARED; 325 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 326#endif 327 } 328 329 for (i = 0; i < 16; i++) { 330 unsigned long v = pgprot_val(protection_map[i]); 331 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot; 332 protection_map[i] = __pgprot(v); 333 } 334 335 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot; 336 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot; 337 338 if (cpu_arch >= CPU_ARCH_ARMv5) { 339#ifndef CONFIG_SMP 340 /* 341 * Only use write-through for non-SMP systems 342 */ 343 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE; 344 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE; 345#endif 346 } else { 347 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); 348 } 349 350 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 351 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 352 L_PTE_DIRTY | L_PTE_WRITE | 353 L_PTE_EXEC | kern_pgprot); 354 355 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 356 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 357 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 358 mem_types[MT_ROM].prot_sect |= cp->pmd; 359 360 switch (cp->pmd) { 361 case PMD_SECT_WT: 362 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 363 break; 364 case PMD_SECT_WB: 365 case PMD_SECT_WBWA: 366 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 367 break; 368 } 369 printk("Memory policy: ECC %sabled, Data cache %s\n", 370 ecc_mask ? "en" : "dis", cp->policy); 371 372 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 373 struct mem_type *t = &mem_types[i]; 374 if (t->prot_l1) 375 t->prot_l1 |= PMD_DOMAIN(t->domain); 376 if (t->prot_sect) 377 t->prot_sect |= PMD_DOMAIN(t->domain); 378 } 379} 380 381#define vectors_base() (vectors_high() ? 0xffff0000 : 0) 382 383static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 384 unsigned long end, unsigned long pfn, 385 const struct mem_type *type) 386{ 387 pte_t *pte; 388 389 if (pmd_none(*pmd)) { 390 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); 391 __pmd_populate(pmd, __pa(pte) | type->prot_l1); 392 } 393 394 pte = pte_offset_kernel(pmd, addr); 395 do { 396 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 397 type->prot_pte_ext); 398 pfn++; 399 } while (pte++, addr += PAGE_SIZE, addr != end); 400} 401 402static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, 403 unsigned long end, unsigned long phys, 404 const struct mem_type *type) 405{ 406 pmd_t *pmd = pmd_offset(pgd, addr); 407 408 /* 409 * Try a section mapping - end, addr and phys must all be aligned 410 * to a section boundary. Note that PMDs refer to the individual 411 * L1 entries, whereas PGDs refer to a group of L1 entries making 412 * up one logical pointer to an L2 table. 413 */ 414 if (((addr | end | phys) & ~SECTION_MASK) == 0) { 415 pmd_t *p = pmd; 416 417 if (addr & SECTION_SIZE) 418 pmd++; 419 420 do { 421 *pmd = __pmd(phys | type->prot_sect); 422 phys += SECTION_SIZE; 423 } while (pmd++, addr += SECTION_SIZE, addr != end); 424 425 flush_pmd_entry(p); 426 } else { 427 /* 428 * No need to loop; pte's aren't interested in the 429 * individual L1 entries. 430 */ 431 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); 432 } 433} 434 435static void __init create_36bit_mapping(struct map_desc *md, 436 const struct mem_type *type) 437{ 438 unsigned long phys, addr, length, end; 439 pgd_t *pgd; 440 441 addr = md->virtual; 442 phys = (unsigned long)__pfn_to_phys(md->pfn); 443 length = PAGE_ALIGN(md->length); 444 445 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 446 printk(KERN_ERR "MM: CPU does not support supersection " 447 "mapping for 0x%08llx at 0x%08lx\n", 448 __pfn_to_phys((u64)md->pfn), addr); 449 return; 450 } 451 452 /* N.B. ARMv6 supersections are only defined to work with domain 0. 453 * Since domain assignments can in fact be arbitrary, the 454 * 'domain == 0' check below is required to insure that ARMv6 455 * supersections are only allocated for domain 0 regardless 456 * of the actual domain assignments in use. 457 */ 458 if (type->domain) { 459 printk(KERN_ERR "MM: invalid domain in supersection " 460 "mapping for 0x%08llx at 0x%08lx\n", 461 __pfn_to_phys((u64)md->pfn), addr); 462 return; 463 } 464 465 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 466 printk(KERN_ERR "MM: cannot create mapping for " 467 "0x%08llx at 0x%08lx invalid alignment\n", 468 __pfn_to_phys((u64)md->pfn), addr); 469 return; 470 } 471 472 /* 473 * Shift bits [35:32] of address into bits [23:20] of PMD 474 * (See ARMv6 spec). 475 */ 476 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 477 478 pgd = pgd_offset_k(addr); 479 end = addr + length; 480 do { 481 pmd_t *pmd = pmd_offset(pgd, addr); 482 int i; 483 484 for (i = 0; i < 16; i++) 485 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); 486 487 addr += SUPERSECTION_SIZE; 488 phys += SUPERSECTION_SIZE; 489 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 490 } while (addr != end); 491} 492 493/* 494 * Create the page directory entries and any necessary 495 * page tables for the mapping specified by `md'. We 496 * are able to cope here with varying sizes and address 497 * offsets, and we take full advantage of sections and 498 * supersections. 499 */ 500void __init create_mapping(struct map_desc *md) 501{ 502 unsigned long phys, addr, length, end; 503 const struct mem_type *type; 504 pgd_t *pgd; 505 506 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 507 printk(KERN_WARNING "BUG: not creating mapping for " 508 "0x%08llx at 0x%08lx in user region\n", 509 __pfn_to_phys((u64)md->pfn), md->virtual); 510 return; 511 } 512 513 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 514 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { 515 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " 516 "overlaps vmalloc space\n", 517 __pfn_to_phys((u64)md->pfn), md->virtual); 518 } 519 520 type = &mem_types[md->type]; 521 522 /* 523 * Catch 36-bit addresses 524 */ 525 if (md->pfn >= 0x100000) { 526 create_36bit_mapping(md, type); 527 return; 528 } 529 530 addr = md->virtual & PAGE_MASK; 531 phys = (unsigned long)__pfn_to_phys(md->pfn); 532 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 533 534 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 535 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " 536 "be mapped using pages, ignoring.\n", 537 __pfn_to_phys(md->pfn), addr); 538 return; 539 } 540 541 pgd = pgd_offset_k(addr); 542 end = addr + length; 543 do { 544 unsigned long next = pgd_addr_end(addr, end); 545 546 alloc_init_section(pgd, addr, next, phys, type); 547 548 phys += next - addr; 549 addr = next; 550 } while (pgd++, addr != end); 551} 552 553/* 554 * Create the architecture specific mappings 555 */ 556void __init iotable_init(struct map_desc *io_desc, int nr) 557{ 558 int i; 559 560 for (i = 0; i < nr; i++) 561 create_mapping(io_desc + i); 562} 563 564static inline void prepare_page_table(struct meminfo *mi) 565{ 566 unsigned long addr; 567 568 /* 569 * Clear out all the mappings below the kernel image. 570 */ 571 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) 572 pmd_clear(pmd_off_k(addr)); 573 574#ifdef CONFIG_XIP_KERNEL 575 /* The XIP kernel is mapped in the module area -- skip over it */ 576 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; 577#endif 578 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) 579 pmd_clear(pmd_off_k(addr)); 580 581 /* 582 * Clear out all the kernel space mappings, except for the first 583 * memory bank, up to the end of the vmalloc region. 584 */ 585 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); 586 addr < VMALLOC_END; addr += PGDIR_SIZE) 587 pmd_clear(pmd_off_k(addr)); 588} 589 590/* 591 * Reserve the various regions of node 0 592 */ 593void __init reserve_node_zero(pg_data_t *pgdat) 594{ 595 unsigned long res_size = 0; 596 597 /* 598 * Register the kernel text and data with bootmem. 599 * Note that this can only be in node 0. 600 */ 601#ifdef CONFIG_XIP_KERNEL 602 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start); 603#else 604 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext); 605#endif 606 607 /* 608 * Reserve the page tables. These are already in use, 609 * and can only be in node 0. 610 */ 611 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), 612 PTRS_PER_PGD * sizeof(pgd_t)); 613 614 /* 615 * Hmm... This should go elsewhere, but we really really need to 616 * stop things allocating the low memory; ideally we need a better 617 * implementation of GFP_DMA which does not assume that DMA-able 618 * memory starts at zero. 619 */ 620 if (machine_is_integrator() || machine_is_cintegrator()) 621 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; 622 623 /* 624 * These should likewise go elsewhere. They pre-reserve the 625 * screen memory region at the start of main system memory. 626 */ 627 if (machine_is_edb7211()) 628 res_size = 0x00020000; 629 if (machine_is_p720t()) 630 res_size = 0x00014000; 631 632 /* H1940 and RX3715 need to reserve this for suspend */ 633 634 if (machine_is_h1940() || machine_is_rx3715()) { 635 reserve_bootmem_node(pgdat, 0x30003000, 0x1000); 636 reserve_bootmem_node(pgdat, 0x30081000, 0x1000); 637 } 638 639#ifdef CONFIG_SA1111 640 /* 641 * Because of the SA1111 DMA bug, we want to preserve our 642 * precious DMA-able memory... 643 */ 644 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; 645#endif 646 if (res_size) 647 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size); 648} 649 650/* 651 * Set up device the mappings. Since we clear out the page tables for all 652 * mappings above VMALLOC_END, we will remove any debug device mappings. 653 * This means you have to be careful how you debug this function, or any 654 * called function. This means you can't use any function or debugging 655 * method which may touch any device, otherwise the kernel _will_ crash. 656 */ 657static void __init devicemaps_init(struct machine_desc *mdesc) 658{ 659 struct map_desc map; 660 unsigned long addr; 661 void *vectors; 662 663 /* 664 * Allocate the vector page early. 665 */ 666 vectors = alloc_bootmem_low_pages(PAGE_SIZE); 667 BUG_ON(!vectors); 668 669 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) 670 pmd_clear(pmd_off_k(addr)); 671 672 /* 673 * Map the kernel if it is XIP. 674 * It is always first in the modulearea. 675 */ 676#ifdef CONFIG_XIP_KERNEL 677 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 678 map.virtual = MODULE_START; 679 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; 680 map.type = MT_ROM; 681 create_mapping(&map); 682#endif 683 684 /* 685 * Map the cache flushing regions. 686 */ 687#ifdef FLUSH_BASE 688 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 689 map.virtual = FLUSH_BASE; 690 map.length = SZ_1M; 691 map.type = MT_CACHECLEAN; 692 create_mapping(&map); 693#endif 694#ifdef FLUSH_BASE_MINICACHE 695 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 696 map.virtual = FLUSH_BASE_MINICACHE; 697 map.length = SZ_1M; 698 map.type = MT_MINICLEAN; 699 create_mapping(&map); 700#endif 701 702 /* 703 * Create a mapping for the machine vectors at the high-vectors 704 * location (0xffff0000). If we aren't using high-vectors, also 705 * create a mapping at the low-vectors virtual address. 706 */ 707 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 708 map.virtual = 0xffff0000; 709 map.length = PAGE_SIZE; 710 map.type = MT_HIGH_VECTORS; 711 create_mapping(&map); 712 713 if (!vectors_high()) { 714 map.virtual = 0; 715 map.type = MT_LOW_VECTORS; 716 create_mapping(&map); 717 } 718 719 /* 720 * Ask the machine support to map in the statically mapped devices. 721 */ 722 if (mdesc->map_io) 723 mdesc->map_io(); 724 725 /* 726 * Finally flush the caches and tlb to ensure that we're in a 727 * consistent state wrt the writebuffer. This also ensures that 728 * any write-allocated cache lines in the vector page are written 729 * back. After this point, we can start to touch devices again. 730 */ 731 local_flush_tlb_all(); 732 flush_cache_all(); 733} 734 735/* 736 * paging_init() sets up the page tables, initialises the zone memory 737 * maps, and sets up the zero page, bad page and bad page tables. 738 */ 739void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) 740{ 741 void *zero_page; 742 743 build_mem_type_table(); 744 prepare_page_table(mi); 745 bootmem_init(mi); 746 devicemaps_init(mdesc); 747 748 top_pmd = pmd_off_k(0xffff0000); 749 750 /* 751 * allocate the zero page. Note that we count on this going ok. 752 */ 753 zero_page = alloc_bootmem_low_pages(PAGE_SIZE); 754 memzero(zero_page, PAGE_SIZE); 755 empty_zero_page = virt_to_page(zero_page); 756 flush_dcache_page(empty_zero_page); 757} 758 759/* 760 * In order to soft-boot, we need to insert a 1:1 mapping in place of 761 * the user-mode pages. This will then ensure that we have predictable 762 * results when turning the mmu off 763 */ 764void setup_mm_for_reboot(char mode) 765{ 766 unsigned long base_pmdval; 767 pgd_t *pgd; 768 int i; 769 770 if (current->mm && current->mm->pgd) 771 pgd = current->mm->pgd; 772 else 773 pgd = init_mm.pgd; 774 775 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; 776 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) 777 base_pmdval |= PMD_BIT4; 778 779 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { 780 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; 781 pmd_t *pmd; 782 783 pmd = pmd_off(pgd, i << PGDIR_SHIFT); 784 pmd[0] = __pmd(pmdval); 785 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); 786 flush_pmd_entry(pmd); 787 } 788} 789