1/*
2 *  linux/arch/arm/mach-sa1100/cpu-sa1110.c
3 *
4 *  Copyright (C) 2001 Russell King
5 *
6 *  $Id: cpu-sa1110.c,v 1.1.1.1 2007/08/03 18:51:38 Exp $
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Note: there are two erratas that apply to the SA1110 here:
13 *  7 - SDRAM auto-power-up failure (rev A0)
14 * 13 - Corruption of internal register reads/writes following
15 *      SDRAM reads (rev A0, B0, B1)
16 *
17 * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
18 *
19 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
20 */
21#include <linux/moduleparam.h>
22#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/cpufreq.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28
29#include <asm/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/io.h>
32#include <asm/system.h>
33
34#include "generic.h"
35
36#undef DEBUG
37
38static struct cpufreq_driver sa1110_driver;
39
40struct sdram_params {
41	const char name[16];
42	u_char  rows;		/* bits				 */
43	u_char  cas_latency;	/* cycles			 */
44	u_char  tck;		/* clock cycle time (ns)	 */
45	u_char  trcd;		/* activate to r/w (ns)		 */
46	u_char  trp;		/* precharge to activate (ns)	 */
47	u_char  twr;		/* write recovery time (ns)	 */
48	u_short refresh;	/* refresh time for array (us)	 */
49};
50
51struct sdram_info {
52	u_int	mdcnfg;
53	u_int	mdrefr;
54	u_int	mdcas[3];
55};
56
57static struct sdram_params sdram_tbl[] __initdata = {
58	{	/* Toshiba TC59SM716 CL2 */
59		.name		= "TC59SM716-CL2",
60		.rows		= 12,
61		.tck		= 10,
62		.trcd		= 20,
63		.trp		= 20,
64		.twr		= 10,
65		.refresh	= 64000,
66		.cas_latency	= 2,
67	}, {	/* Toshiba TC59SM716 CL3 */
68		.name		= "TC59SM716-CL3",
69		.rows		= 12,
70		.tck		= 8,
71		.trcd		= 20,
72		.trp		= 20,
73		.twr		= 8,
74		.refresh	= 64000,
75		.cas_latency	= 3,
76	}, {	/* Samsung K4S641632D TC75 */
77		.name		= "K4S641632D",
78		.rows		= 14,
79		.tck		= 9,
80		.trcd		= 27,
81		.trp		= 20,
82		.twr		= 9,
83		.refresh	= 64000,
84		.cas_latency	= 3,
85	}, {    /* Samsung K4S281632B-1H */
86	        .name           = "K4S281632B-1H",
87		.rows           = 12,
88		.tck            = 10,
89		.trp            = 20,
90		.twr            = 10,
91		.refresh        = 64000,
92		.cas_latency    = 3,
93	}, {	/* Samsung KM416S4030CT */
94		.name		= "KM416S4030CT",
95		.rows		= 13,
96		.tck		= 8,
97		.trcd		= 24,	/* 3 CLKs */
98		.trp		= 24,	/* 3 CLKs */
99		.twr		= 16,	/* Trdl: 2 CLKs */
100		.refresh	= 64000,
101		.cas_latency	= 3,
102	}, {	/* Winbond W982516AH75L CL3 */
103		.name		= "W982516AH75L",
104		.rows		= 16,
105		.tck		= 8,
106		.trcd		= 20,
107		.trp		= 20,
108		.twr		= 8,
109		.refresh	= 64000,
110		.cas_latency	= 3,
111	},
112};
113
114static struct sdram_params sdram_params;
115
116/*
117 * Given a period in ns and frequency in khz, calculate the number of
118 * cycles of frequency in period.  Note that we round up to the next
119 * cycle, even if we are only slightly over.
120 */
121static inline u_int ns_to_cycles(u_int ns, u_int khz)
122{
123	return (ns * khz + 999999) / 1000000;
124}
125
126/*
127 * Create the MDCAS register bit pattern.
128 */
129static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
130{
131	u_int shift;
132
133	rcd = 2 * rcd - 1;
134	shift = delayed + 1 + rcd;
135
136	mdcas[0]  = (1 << rcd) - 1;
137	mdcas[0] |= 0x55555555 << shift;
138	mdcas[1]  = mdcas[2] = 0x55555555 << (shift & 1);
139}
140
141static void
142sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
143		       struct sdram_params *sdram)
144{
145	u_int mem_khz, sd_khz, trp, twr;
146
147	mem_khz = cpu_khz / 2;
148	sd_khz = mem_khz;
149
150	/*
151	 * If SDCLK would invalidate the SDRAM timings,
152	 * run SDCLK at half speed.
153	 *
154	 * CPU steppings prior to B2 must either run the memory at
155	 * half speed or use delayed read latching (errata 13).
156	 */
157	if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
158	    (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
159		sd_khz /= 2;
160
161	sd->mdcnfg = MDCNFG & 0x007f007f;
162
163	twr = ns_to_cycles(sdram->twr, mem_khz);
164
165	/* trp should always be >1 */
166	trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
167	if (trp < 1)
168		trp = 1;
169
170	sd->mdcnfg |= trp << 8;
171	sd->mdcnfg |= trp << 24;
172	sd->mdcnfg |= sdram->cas_latency << 12;
173	sd->mdcnfg |= sdram->cas_latency << 28;
174	sd->mdcnfg |= twr << 14;
175	sd->mdcnfg |= twr << 30;
176
177	sd->mdrefr = MDREFR & 0xffbffff0;
178	sd->mdrefr |= 7;
179
180	if (sd_khz != mem_khz)
181		sd->mdrefr |= MDREFR_K1DB2;
182
183	/* initial number of '1's in MDCAS + 1 */
184	set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
185
186#ifdef DEBUG
187	printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
188		sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
189#endif
190}
191
192/*
193 * Set the SDRAM refresh rate.
194 */
195static inline void sdram_set_refresh(u_int dri)
196{
197	MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
198	(void) MDREFR;
199}
200
201static void
202sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
203{
204	u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
205	u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
206
207#ifdef DEBUG
208	mdelay(250);
209	printk("new dri value = %d\n", dri);
210#endif
211
212	sdram_set_refresh(dri);
213}
214
215/*
216 * Ok, set the CPU frequency.
217 */
218static int sa1110_target(struct cpufreq_policy *policy,
219			 unsigned int target_freq,
220			 unsigned int relation)
221{
222	struct sdram_params *sdram = &sdram_params;
223	struct cpufreq_freqs freqs;
224	struct sdram_info sd;
225	unsigned long flags;
226	unsigned int ppcr, unused;
227
228	switch(relation){
229	case CPUFREQ_RELATION_L:
230		ppcr = sa11x0_freq_to_ppcr(target_freq);
231		if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
232			ppcr--;
233		break;
234	case CPUFREQ_RELATION_H:
235		ppcr = sa11x0_freq_to_ppcr(target_freq);
236		if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
237		    (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
238			ppcr--;
239		break;
240	default:
241		return -EINVAL;
242	}
243
244	freqs.old = sa11x0_getspeed(0);
245	freqs.new = sa11x0_ppcr_to_freq(ppcr);
246	freqs.cpu = 0;
247
248	sdram_calculate_timing(&sd, freqs.new, sdram);
249
250
251	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
252
253	/*
254	 * The clock could be going away for some time.  Set the SDRAMs
255	 * to refresh rapidly (every 64 memory clock cycles).  To get
256	 * through the whole array, we need to wait 262144 mclk cycles.
257	 * We wait 20ms to be safe.
258	 */
259	sdram_set_refresh(2);
260	if (!irqs_disabled()) {
261		msleep(20);
262	} else {
263		mdelay(20);
264	}
265
266	/*
267	 * Reprogram the DRAM timings with interrupts disabled, and
268	 * ensure that we are doing this within a complete cache line.
269	 * This means that we won't access SDRAM for the duration of
270	 * the programming.
271	 */
272	local_irq_save(flags);
273	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
274	udelay(10);
275	__asm__ __volatile__("					\n\
276		b	2f					\n\
277		.align	5					\n\
2781:		str	%3, [%1, #0]		@ MDCNFG	\n\
279		str	%4, [%1, #28]		@ MDREFR	\n\
280		str	%5, [%1, #4]		@ MDCAS0	\n\
281		str	%6, [%1, #8]		@ MDCAS1	\n\
282		str	%7, [%1, #12]		@ MDCAS2	\n\
283		str	%8, [%2, #0]		@ PPCR		\n\
284		ldr	%0, [%1, #0]				\n\
285		b	3f					\n\
2862:		b	1b					\n\
2873:		nop						\n\
288		nop"
289		: "=&r" (unused)
290		: "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
291		  "r" (sd.mdrefr), "r" (sd.mdcas[0]),
292		  "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
293	local_irq_restore(flags);
294
295	/*
296	 * Now, return the SDRAM refresh back to normal.
297	 */
298	sdram_update_refresh(freqs.new, sdram);
299
300	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
301
302	return 0;
303}
304
305static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
306{
307	if (policy->cpu != 0)
308		return -EINVAL;
309	policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
310	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
311	policy->cpuinfo.min_freq = 59000;
312	policy->cpuinfo.max_freq = 287000;
313	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
314	return 0;
315}
316
317static struct cpufreq_driver sa1110_driver = {
318	.flags		= CPUFREQ_STICKY,
319	.verify		= sa11x0_verify_speed,
320	.target		= sa1110_target,
321	.get		= sa11x0_getspeed,
322	.init		= sa1110_cpu_init,
323	.name		= "sa1110",
324};
325
326static struct sdram_params *sa1110_find_sdram(const char *name)
327{
328	struct sdram_params *sdram;
329
330	for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
331		if (strcmp(name, sdram->name) == 0)
332			return sdram;
333
334	return NULL;
335}
336
337static char sdram_name[16];
338
339static int __init sa1110_clk_init(void)
340{
341	struct sdram_params *sdram;
342	const char *name = sdram_name;
343
344	if (!name[0]) {
345		if (machine_is_assabet())
346			name = "TC59SM716-CL3";
347
348		if (machine_is_pt_system3())
349			name = "K4S641632D";
350
351		if (machine_is_h3100())
352			name = "KM416S4030CT";
353		if (machine_is_jornada720())
354		        name = "K4S281632B-1H";
355	}
356
357	sdram = sa1110_find_sdram(name);
358	if (sdram) {
359		printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
360			" twr: %d refresh: %d cas_latency: %d\n",
361			sdram->tck, sdram->trcd, sdram->trp,
362			sdram->twr, sdram->refresh, sdram->cas_latency);
363
364		memcpy(&sdram_params, sdram, sizeof(sdram_params));
365
366		return cpufreq_register_driver(&sa1110_driver);
367	}
368
369	return 0;
370}
371
372module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
373arch_initcall(sa1110_clk_init);
374