1/* 2 * linux/arch/arm/mach-omap2/memory.c 3 * 4 * Memory timing related functions for OMAP24XX 5 * 6 * Copyright (C) 2005 Texas Instruments Inc. 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * 9 * Copyright (C) 2005 Nokia Corporation 10 * Tony Lindgren <tony@atomide.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#include <linux/module.h> 18#include <linux/kernel.h> 19#include <linux/device.h> 20#include <linux/list.h> 21#include <linux/errno.h> 22#include <linux/delay.h> 23#include <linux/clk.h> 24 25#include <asm/io.h> 26 27#include <asm/arch/clock.h> 28#include <asm/arch/sram.h> 29 30#include "prcm-regs.h" 31#include "memory.h" 32 33static struct memory_timings mem_timings; 34 35u32 omap2_memory_get_slow_dll_ctrl(void) 36{ 37 return mem_timings.slow_dll_ctrl; 38} 39 40u32 omap2_memory_get_fast_dll_ctrl(void) 41{ 42 return mem_timings.fast_dll_ctrl; 43} 44 45u32 omap2_memory_get_type(void) 46{ 47 return mem_timings.m_type; 48} 49 50void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 51{ 52 unsigned long dll_cnt; 53 u32 fast_dll = 0; 54 55 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ 56 57 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. 58 * In the case of 2422, its ok to use CS1 instead of CS0. 59 */ 60 if (cpu_is_omap2422()) 61 mem_timings.base_cs = 1; 62 else 63 mem_timings.base_cs = 0; 64 65 if (mem_timings.m_type != M_DDR) 66 return; 67 68 /* With DDR we need to determine the low frequency DLL value */ 69 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL)) 70 mem_timings.dll_mode = M_UNLOCK; 71 else 72 mem_timings.dll_mode = M_LOCK; 73 74 if (mem_timings.base_cs == 0) { 75 fast_dll = SDRC_DLLA_CTRL; 76 dll_cnt = SDRC_DLLA_STATUS & 0xff00; 77 } else { 78 fast_dll = SDRC_DLLB_CTRL; 79 dll_cnt = SDRC_DLLB_STATUS & 0xff00; 80 } 81 if (force_lock_to_unlock_mode) { 82 fast_dll &= ~0xff00; 83 fast_dll |= dll_cnt; /* Current lock mode */ 84 } 85 /* set fast timings with DLL filter disabled */ 86 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8)); 87 88 /* No disruptions, DDR will be offline & C-ABI not followed */ 89 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl, 90 mem_timings.fast_dll_ctrl, 91 mem_timings.base_cs, 92 force_lock_to_unlock_mode); 93 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */ 94 95 /* Turn status into unlock ctrl */ 96 mem_timings.slow_dll_ctrl |= 97 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); 98 99 /* 90 degree phase for anything below 133Mhz + disable DLL filter */ 100 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); 101} 102