1/* 2 * arch/arm/mach-ixp4xx/common-pci.c 3 * 4 * IXP4XX PCI routines for all platforms 5 * 6 * Maintainer: Deepak Saxena <dsaxena@plexity.net> 7 * 8 * Copyright (C) 2002 Intel Corporation. 9 * Copyright (C) 2003 Greg Ungerer <gerg@snapgear.com> 10 * Copyright (C) 2003-2004 MontaVista Software, Inc. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 * 16 */ 17 18#include <linux/sched.h> 19#include <linux/kernel.h> 20#include <linux/pci.h> 21#include <linux/interrupt.h> 22#include <linux/mm.h> 23#include <linux/init.h> 24#include <linux/ioport.h> 25#include <linux/slab.h> 26#include <linux/delay.h> 27#include <linux/device.h> 28#include <asm/dma-mapping.h> 29 30#include <asm/io.h> 31#include <asm/irq.h> 32#include <asm/sizes.h> 33#include <asm/system.h> 34#include <asm/mach/pci.h> 35#include <asm/hardware.h> 36 37 38/* 39 * IXP4xx PCI read function is dependent on whether we are 40 * running A0 or B0 (AppleGate) silicon. 41 */ 42int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); 43 44/* 45 * Base address for PCI regsiter region 46 */ 47unsigned long ixp4xx_pci_reg_base = 0; 48 49/* 50 * PCI cfg an I/O routines are done by programming a 51 * command/byte enable register, and then read/writing 52 * the data from a data regsiter. We need to ensure 53 * these transactions are atomic or we will end up 54 * with corrupt data on the bus or in a driver. 55 */ 56static DEFINE_SPINLOCK(ixp4xx_pci_lock); 57 58/* 59 * Read from PCI config space 60 */ 61static void crp_read(u32 ad_cbe, u32 *data) 62{ 63 unsigned long flags; 64 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 65 *PCI_CRP_AD_CBE = ad_cbe; 66 *data = *PCI_CRP_RDATA; 67 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 68} 69 70/* 71 * Write to PCI config space 72 */ 73static void crp_write(u32 ad_cbe, u32 data) 74{ 75 unsigned long flags; 76 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 77 *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe; 78 *PCI_CRP_WDATA = data; 79 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 80} 81 82static inline int check_master_abort(void) 83{ 84 /* check Master Abort bit after access */ 85 unsigned long isr = *PCI_ISR; 86 87 if (isr & PCI_ISR_PFE) { 88 /* make sure the Master Abort bit is reset */ 89 *PCI_ISR = PCI_ISR_PFE; 90 pr_debug("%s failed\n", __FUNCTION__); 91 return 1; 92 } 93 94 return 0; 95} 96 97int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) 98{ 99 unsigned long flags; 100 int retval = 0; 101 int i; 102 103 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 104 105 *PCI_NP_AD = addr; 106 107 for (i = 0; i < 8; i++) { 108 *PCI_NP_CBE = cmd; 109 *data = *PCI_NP_RDATA; 110 *data = *PCI_NP_RDATA; 111 } 112 113 if(check_master_abort()) 114 retval = 1; 115 116 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 117 return retval; 118} 119 120int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) 121{ 122 unsigned long flags; 123 int retval = 0; 124 125 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 126 127 *PCI_NP_AD = addr; 128 129 /* set up and execute the read */ 130 *PCI_NP_CBE = cmd; 131 132 /* the result of the read is now in NP_RDATA */ 133 *data = *PCI_NP_RDATA; 134 135 if(check_master_abort()) 136 retval = 1; 137 138 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 139 return retval; 140} 141 142int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) 143{ 144 unsigned long flags; 145 int retval = 0; 146 147 spin_lock_irqsave(&ixp4xx_pci_lock, flags); 148 149 *PCI_NP_AD = addr; 150 151 /* set up the write */ 152 *PCI_NP_CBE = cmd; 153 154 /* execute the write by writing to NP_WDATA */ 155 *PCI_NP_WDATA = data; 156 157 if(check_master_abort()) 158 retval = 1; 159 160 spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); 161 return retval; 162} 163 164static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) 165{ 166 u32 addr; 167 if (!bus_num) { 168 /* type 0 */ 169 addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | 170 (where & ~3); 171 } else { 172 /* type 1 */ 173 addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | 174 ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1; 175 } 176 return addr; 177} 178 179/* 180 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. 181 * 0 and 3 are not valid indexes... 182 */ 183static u32 bytemask[] = { 184 /*0*/ 0, 185 /*1*/ 0xff, 186 /*2*/ 0xffff, 187 /*3*/ 0, 188 /*4*/ 0xffffffff, 189}; 190 191static u32 local_byte_lane_enable_bits(u32 n, int size) 192{ 193 if (size == 1) 194 return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; 195 if (size == 2) 196 return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; 197 if (size == 4) 198 return 0; 199 return 0xffffffff; 200} 201 202static int local_read_config(int where, int size, u32 *value) 203{ 204 u32 n, data; 205 pr_debug("local_read_config from %d size %d\n", where, size); 206 n = where % 4; 207 crp_read(where & ~3, &data); 208 *value = (data >> (8*n)) & bytemask[size]; 209 pr_debug("local_read_config read %#x\n", *value); 210 return PCIBIOS_SUCCESSFUL; 211} 212 213static int local_write_config(int where, int size, u32 value) 214{ 215 u32 n, byte_enables, data; 216 pr_debug("local_write_config %#x to %d size %d\n", value, where, size); 217 n = where % 4; 218 byte_enables = local_byte_lane_enable_bits(n, size); 219 if (byte_enables == 0xffffffff) 220 return PCIBIOS_BAD_REGISTER_NUMBER; 221 data = value << (8*n); 222 crp_write((where & ~3) | byte_enables, data); 223 return PCIBIOS_SUCCESSFUL; 224} 225 226static u32 byte_lane_enable_bits(u32 n, int size) 227{ 228 if (size == 1) 229 return (0xf & ~BIT(n)) << 4; 230 if (size == 2) 231 return (0xf & ~(BIT(n) | BIT(n+1))) << 4; 232 if (size == 4) 233 return 0; 234 return 0xffffffff; 235} 236 237static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) 238{ 239 u32 n, byte_enables, addr, data; 240 u8 bus_num = bus->number; 241 242 pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size, 243 bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); 244 245 *value = 0xffffffff; 246 n = where % 4; 247 byte_enables = byte_lane_enable_bits(n, size); 248 if (byte_enables == 0xffffffff) 249 return PCIBIOS_BAD_REGISTER_NUMBER; 250 251 addr = ixp4xx_config_addr(bus_num, devfn, where); 252 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data)) 253 return PCIBIOS_DEVICE_NOT_FOUND; 254 255 *value = (data >> (8*n)) & bytemask[size]; 256 pr_debug("read_config_byte read %#x\n", *value); 257 return PCIBIOS_SUCCESSFUL; 258} 259 260static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) 261{ 262 u32 n, byte_enables, addr, data; 263 u8 bus_num = bus->number; 264 265 pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where, 266 size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); 267 268 n = where % 4; 269 byte_enables = byte_lane_enable_bits(n, size); 270 if (byte_enables == 0xffffffff) 271 return PCIBIOS_BAD_REGISTER_NUMBER; 272 273 addr = ixp4xx_config_addr(bus_num, devfn, where); 274 data = value << (8*n); 275 if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data)) 276 return PCIBIOS_DEVICE_NOT_FOUND; 277 278 return PCIBIOS_SUCCESSFUL; 279} 280 281struct pci_ops ixp4xx_ops = { 282 .read = ixp4xx_pci_read_config, 283 .write = ixp4xx_pci_write_config, 284}; 285 286/* 287 * PCI abort handler 288 */ 289static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 290{ 291 u32 isr, status; 292 293 isr = *PCI_ISR; 294 local_read_config(PCI_STATUS, 2, &status); 295 pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, " 296 "status = %#x\n", addr, isr, status); 297 298 /* make sure the Master Abort bit is reset */ 299 *PCI_ISR = PCI_ISR_PFE; 300 status |= PCI_STATUS_REC_MASTER_ABORT; 301 local_write_config(PCI_STATUS, 2, status); 302 303 /* 304 * If it was an imprecise abort, then we need to correct the 305 * return address to be _after_ the instruction. 306 */ 307 if (fsr & (1 << 10)) 308 regs->ARM_pc += 4; 309 310 return 0; 311} 312 313 314/* 315 * Setup DMA mask to 64MB on PCI devices. Ignore all other devices. 316 */ 317static int ixp4xx_pci_platform_notify(struct device *dev) 318{ 319 if(dev->bus == &pci_bus_type) { 320 *dev->dma_mask = SZ_64M - 1; 321 dev->coherent_dma_mask = SZ_64M - 1; 322 dmabounce_register_dev(dev, 2048, 4096); 323 } 324 return 0; 325} 326 327static int ixp4xx_pci_platform_notify_remove(struct device *dev) 328{ 329 if(dev->bus == &pci_bus_type) { 330 dmabounce_unregister_dev(dev); 331 } 332 return 0; 333} 334 335int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) 336{ 337 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); 338} 339 340/* 341 * Only first 64MB of memory can be accessed via PCI. 342 * We use GFP_DMA to allocate safe buffers to do map/unmap. 343 * This is really ugly and we need a better way of specifying 344 * DMA-capable regions of memory. 345 */ 346void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, 347 unsigned long *zhole_size) 348{ 349 unsigned int sz = SZ_64M >> PAGE_SHIFT; 350 351 /* 352 * Only adjust if > 64M on current system 353 */ 354 if (node || (zone_size[0] <= sz)) 355 return; 356 357 zone_size[1] = zone_size[0] - sz; 358 zone_size[0] = sz; 359 zhole_size[1] = zhole_size[0]; 360 zhole_size[0] = 0; 361} 362 363void __init ixp4xx_pci_preinit(void) 364{ 365 unsigned long processor_id; 366 367 asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); 368 369 if (!(processor_id & 0xf) && cpu_is_ixp42x()) { 370 printk("PCI: IXP42x A0 silicon detected - " 371 "PCI Non-Prefetch Workaround Enabled\n"); 372 ixp4xx_pci_read = ixp4xx_pci_read_errata; 373 } else 374 ixp4xx_pci_read = ixp4xx_pci_read_no_errata; 375 376 377 /* hook in our fault handler for PCI errors */ 378 hook_fault_code(16+6, abort_handler, SIGBUS, "imprecise external abort"); 379 380 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); 381 382 /* 383 * We use identity AHB->PCI address translation 384 * in the 0x48000000 to 0x4bffffff address space 385 */ 386 *PCI_PCIMEMBASE = 0x48494A4B; 387 388 /* 389 * We also use identity PCI->AHB address translation 390 * in 4 16MB BARs that begin at the physical memory start 391 */ 392 *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + 393 ((PHYS_OFFSET & 0xFF000000) >> 8) + 394 ((PHYS_OFFSET & 0xFF000000) >> 16) + 395 ((PHYS_OFFSET & 0xFF000000) >> 24) + 396 0x00010203; 397 398 if (*PCI_CSR & PCI_CSR_HOST) { 399 printk("PCI: IXP4xx is host\n"); 400 401 pr_debug("setup BARs in controller\n"); 402 403 /* 404 * We configure the PCI inbound memory windows to be 405 * 1:1 mapped to SDRAM 406 */ 407 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000); 408 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000); 409 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000); 410 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000); 411 412 /* 413 * Enable CSR window at 0xff000000. 414 */ 415 local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008); 416 417 /* 418 * Enable the IO window to be way up high, at 0xfffffc00 419 */ 420 local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01); 421 } else { 422 printk("PCI: IXP4xx is target - No bus scan performed\n"); 423 } 424 425 printk("PCI: IXP4xx Using %s access for memory space\n", 426#ifndef CONFIG_IXP4XX_INDIRECT_PCI 427 "direct" 428#else 429 "indirect" 430#endif 431 ); 432 433 pr_debug("clear error bits in ISR\n"); 434 *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE; 435 436 /* 437 * Set Initialize Complete in PCI Control Register: allow IXP4XX to 438 * respond to PCI configuration cycles. Specify that the AHB bus is 439 * operating in big endian mode. Set up byte lane swapping between 440 * little-endian PCI and the big-endian AHB bus 441 */ 442#ifdef __ARMEB__ 443 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; 444#else 445 *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE; 446#endif 447 448 pr_debug("DONE\n"); 449} 450 451int ixp4xx_setup(int nr, struct pci_sys_data *sys) 452{ 453 struct resource *res; 454 455 if (nr >= 1) 456 return 0; 457 458 res = kzalloc(sizeof(*res) * 2, GFP_KERNEL); 459 if (res == NULL) { 460 /* 461 * If we're out of memory this early, something is wrong, 462 * so we might as well catch it here. 463 */ 464 panic("PCI: unable to allocate resources?\n"); 465 } 466 467 local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 468 469 res[0].name = "PCI I/O Space"; 470 res[0].start = 0x00000000; 471 res[0].end = 0x0000ffff; 472 res[0].flags = IORESOURCE_IO; 473 474 res[1].name = "PCI Memory Space"; 475 res[1].start = PCIBIOS_MIN_MEM; 476#ifndef CONFIG_IXP4XX_INDIRECT_PCI 477 res[1].end = 0x4bffffff; 478#else 479 res[1].end = 0x4fffffff; 480#endif 481 res[1].flags = IORESOURCE_MEM; 482 483 request_resource(&ioport_resource, &res[0]); 484 request_resource(&iomem_resource, &res[1]); 485 486 sys->resource[0] = &res[0]; 487 sys->resource[1] = &res[1]; 488 sys->resource[2] = NULL; 489 490 platform_notify = ixp4xx_pci_platform_notify; 491 platform_notify_remove = ixp4xx_pci_platform_notify_remove; 492 493 return 1; 494} 495 496struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) 497{ 498 return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); 499} 500 501/* 502 * We override these so we properly do dmabounce otherwise drivers 503 * are able to set the dma_mask to 0xffffffff and we can no longer 504 * trap bounces. :( 505 * 506 * We just return true on everyhing except for < 64MB in which case 507 * we will fail miseralby and die since we can't handle that case. 508 */ 509int 510pci_set_dma_mask(struct pci_dev *dev, u64 mask) 511{ 512 if (mask >= SZ_64M - 1 ) 513 return 0; 514 515 return -EIO; 516} 517 518int 519pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 520{ 521 if (mask >= SZ_64M - 1 ) 522 return 0; 523 524 return -EIO; 525} 526 527EXPORT_SYMBOL(ixp4xx_pci_read); 528EXPORT_SYMBOL(ixp4xx_pci_write); 529