1/* 2 * arch/arm/mach-ixp2000/core.c 3 * 4 * Common routines used by all IXP2400/2800 based platforms. 5 * 6 * Author: Deepak Saxena <dsaxena@plexity.net> 7 * 8 * Copyright 2004 (C) MontaVista Software, Inc. 9 * 10 * Based on work Copyright (C) 2002-2003 Intel Corporation 11 * 12 * This file is licensed under the terms of the GNU General Public 13 * License version 2. This program is licensed "as is" without any 14 * warranty of any kind, whether express or implied. 15 */ 16 17#include <linux/kernel.h> 18#include <linux/init.h> 19#include <linux/spinlock.h> 20#include <linux/sched.h> 21#include <linux/interrupt.h> 22#include <linux/irq.h> 23#include <linux/serial.h> 24#include <linux/tty.h> 25#include <linux/bitops.h> 26#include <linux/serial_8250.h> 27#include <linux/mm.h> 28 29#include <asm/types.h> 30#include <asm/setup.h> 31#include <asm/memory.h> 32#include <asm/hardware.h> 33#include <asm/irq.h> 34#include <asm/system.h> 35#include <asm/tlbflush.h> 36#include <asm/pgtable.h> 37 38#include <asm/mach/map.h> 39#include <asm/mach/time.h> 40#include <asm/mach/irq.h> 41 42#include <asm/arch/gpio.h> 43 44static DEFINE_SPINLOCK(ixp2000_slowport_lock); 45static unsigned long ixp2000_slowport_irq_flags; 46 47/************************************************************************* 48 * Slowport access routines 49 *************************************************************************/ 50void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg) 51{ 52 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags); 53 54 old_cfg->CCR = *IXP2000_SLOWPORT_CCR; 55 old_cfg->WTC = *IXP2000_SLOWPORT_WTC2; 56 old_cfg->RTC = *IXP2000_SLOWPORT_RTC2; 57 old_cfg->PCR = *IXP2000_SLOWPORT_PCR; 58 old_cfg->ADC = *IXP2000_SLOWPORT_ADC; 59 60 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR); 61 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC); 62 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC); 63 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR); 64 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC); 65} 66 67void ixp2000_release_slowport(struct slowport_cfg *old_cfg) 68{ 69 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR); 70 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC); 71 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC); 72 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR); 73 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC); 74 75 spin_unlock_irqrestore(&ixp2000_slowport_lock, 76 ixp2000_slowport_irq_flags); 77} 78 79/************************************************************************* 80 * Chip specific mappings shared by all IXP2000 systems 81 *************************************************************************/ 82static struct map_desc ixp2000_io_desc[] __initdata = { 83 { 84 .virtual = IXP2000_CAP_VIRT_BASE, 85 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE), 86 .length = IXP2000_CAP_SIZE, 87 .type = MT_DEVICE_IXP2000, 88 }, { 89 .virtual = IXP2000_INTCTL_VIRT_BASE, 90 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE), 91 .length = IXP2000_INTCTL_SIZE, 92 .type = MT_DEVICE_IXP2000, 93 }, { 94 .virtual = IXP2000_PCI_CREG_VIRT_BASE, 95 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE), 96 .length = IXP2000_PCI_CREG_SIZE, 97 .type = MT_DEVICE_IXP2000, 98 }, { 99 .virtual = IXP2000_PCI_CSR_VIRT_BASE, 100 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE), 101 .length = IXP2000_PCI_CSR_SIZE, 102 .type = MT_DEVICE_IXP2000, 103 }, { 104 .virtual = IXP2000_MSF_VIRT_BASE, 105 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE), 106 .length = IXP2000_MSF_SIZE, 107 .type = MT_DEVICE_IXP2000, 108 }, { 109 .virtual = IXP2000_SCRATCH_RING_VIRT_BASE, 110 .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE), 111 .length = IXP2000_SCRATCH_RING_SIZE, 112 .type = MT_DEVICE_IXP2000, 113 }, { 114 .virtual = IXP2000_SRAM0_VIRT_BASE, 115 .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE), 116 .length = IXP2000_SRAM0_SIZE, 117 .type = MT_DEVICE_IXP2000, 118 }, { 119 .virtual = IXP2000_PCI_IO_VIRT_BASE, 120 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE), 121 .length = IXP2000_PCI_IO_SIZE, 122 .type = MT_DEVICE_IXP2000, 123 }, { 124 .virtual = IXP2000_PCI_CFG0_VIRT_BASE, 125 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE), 126 .length = IXP2000_PCI_CFG0_SIZE, 127 .type = MT_DEVICE_IXP2000, 128 }, { 129 .virtual = IXP2000_PCI_CFG1_VIRT_BASE, 130 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE), 131 .length = IXP2000_PCI_CFG1_SIZE, 132 .type = MT_DEVICE_IXP2000, 133 } 134}; 135 136void __init ixp2000_map_io(void) 137{ 138 /* 139 * On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that 140 * XCB=101 (to avoid triggering erratum #66), and given that 141 * this mode speeds up I/O accesses and we have write buffer 142 * flushes in the right places anyway, it doesn't hurt to use 143 * XCB=101 for all IXP2000s. 144 */ 145 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); 146 147 /* Set slowport to 8-bit mode. */ 148 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1); 149} 150 151 152/************************************************************************* 153 * Serial port support for IXP2000 154 *************************************************************************/ 155static struct plat_serial8250_port ixp2000_serial_port[] = { 156 { 157 .mapbase = IXP2000_UART_PHYS_BASE, 158 .membase = (char *)(IXP2000_UART_VIRT_BASE + 3), 159 .irq = IRQ_IXP2000_UART, 160 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 161 .iotype = UPIO_MEM, 162 .regshift = 2, 163 .uartclk = 50000000, 164 }, 165 { }, 166}; 167 168static struct resource ixp2000_uart_resource = { 169 .start = IXP2000_UART_PHYS_BASE, 170 .end = IXP2000_UART_PHYS_BASE + 0x1f, 171 .flags = IORESOURCE_MEM, 172}; 173 174static struct platform_device ixp2000_serial_device = { 175 .name = "serial8250", 176 .id = PLAT8250_DEV_PLATFORM, 177 .dev = { 178 .platform_data = ixp2000_serial_port, 179 }, 180 .num_resources = 1, 181 .resource = &ixp2000_uart_resource, 182}; 183 184void __init ixp2000_uart_init(void) 185{ 186 platform_device_register(&ixp2000_serial_device); 187} 188 189 190/************************************************************************* 191 * Timer-tick functions for IXP2000 192 *************************************************************************/ 193static unsigned ticks_per_jiffy; 194static unsigned ticks_per_usec; 195static unsigned next_jiffy_time; 196static volatile unsigned long *missing_jiffy_timer_csr; 197 198unsigned long ixp2000_gettimeoffset (void) 199{ 200 unsigned long offset; 201 202 offset = next_jiffy_time - *missing_jiffy_timer_csr; 203 204 return offset / ticks_per_usec; 205} 206 207static int ixp2000_timer_interrupt(int irq, void *dev_id) 208{ 209 write_seqlock(&xtime_lock); 210 211 /* clear timer 1 */ 212 ixp2000_reg_wrb(IXP2000_T1_CLR, 1); 213 214 while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr) 215 >= ticks_per_jiffy) { 216 timer_tick(); 217 next_jiffy_time -= ticks_per_jiffy; 218 } 219 220 write_sequnlock(&xtime_lock); 221 222 return IRQ_HANDLED; 223} 224 225static struct irqaction ixp2000_timer_irq = { 226 .name = "IXP2000 Timer Tick", 227 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 228 .handler = ixp2000_timer_interrupt, 229}; 230 231void __init ixp2000_init_time(unsigned long tick_rate) 232{ 233 ticks_per_jiffy = (tick_rate + HZ/2) / HZ; 234 ticks_per_usec = tick_rate / 1000000; 235 236 /* 237 * We use timer 1 as our timer interrupt. 238 */ 239 ixp2000_reg_write(IXP2000_T1_CLR, 0); 240 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1); 241 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7)); 242 243 /* 244 * We use a second timer as a monotonic counter for tracking 245 * missed jiffies. The IXP2000 has four timers, but if we're 246 * on an A-step IXP2800, timer 2 and 3 don't work, so on those 247 * chips we use timer 4. Timer 4 is the only timer that can 248 * be used for the watchdog, so we use timer 2 if we're on a 249 * non-buggy chip. 250 */ 251 if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) { 252 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n"); 253 254 ixp2000_reg_write(IXP2000_T4_CLR, 0); 255 ixp2000_reg_write(IXP2000_T4_CLD, -1); 256 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7)); 257 missing_jiffy_timer_csr = IXP2000_T4_CSR; 258 } else { 259 ixp2000_reg_write(IXP2000_T2_CLR, 0); 260 ixp2000_reg_write(IXP2000_T2_CLD, -1); 261 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7)); 262 missing_jiffy_timer_csr = IXP2000_T2_CSR; 263 } 264 next_jiffy_time = 0xffffffff; 265 266 /* register for interrupt */ 267 setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq); 268} 269 270/************************************************************************* 271 * GPIO helpers 272 *************************************************************************/ 273static unsigned long GPIO_IRQ_falling_edge; 274static unsigned long GPIO_IRQ_rising_edge; 275static unsigned long GPIO_IRQ_level_low; 276static unsigned long GPIO_IRQ_level_high; 277 278static void update_gpio_int_csrs(void) 279{ 280 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge); 281 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge); 282 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low); 283 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high); 284} 285 286void gpio_line_config(int line, int direction) 287{ 288 unsigned long flags; 289 290 local_irq_save(flags); 291 if (direction == GPIO_OUT) { 292 /* if it's an output, it ain't an interrupt anymore */ 293 GPIO_IRQ_falling_edge &= ~(1 << line); 294 GPIO_IRQ_rising_edge &= ~(1 << line); 295 GPIO_IRQ_level_low &= ~(1 << line); 296 GPIO_IRQ_level_high &= ~(1 << line); 297 update_gpio_int_csrs(); 298 299 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line); 300 } else if (direction == GPIO_IN) { 301 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line); 302 } 303 local_irq_restore(flags); 304} 305EXPORT_SYMBOL(gpio_line_config); 306 307 308/************************************************************************* 309 * IRQ handling IXP2000 310 *************************************************************************/ 311static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc) 312{ 313 int i; 314 unsigned long status = *IXP2000_GPIO_INST; 315 316 for (i = 0; i <= 7; i++) { 317 if (status & (1<<i)) { 318 desc = irq_desc + i + IRQ_IXP2000_GPIO0; 319 desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc); 320 } 321 } 322} 323 324static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type) 325{ 326 int line = irq - IRQ_IXP2000_GPIO0; 327 328 /* 329 * First, configure this GPIO line as an input. 330 */ 331 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line); 332 333 /* 334 * Then, set the proper trigger type. 335 */ 336 if (type & IRQT_FALLING) 337 GPIO_IRQ_falling_edge |= 1 << line; 338 else 339 GPIO_IRQ_falling_edge &= ~(1 << line); 340 if (type & IRQT_RISING) 341 GPIO_IRQ_rising_edge |= 1 << line; 342 else 343 GPIO_IRQ_rising_edge &= ~(1 << line); 344 if (type & IRQT_LOW) 345 GPIO_IRQ_level_low |= 1 << line; 346 else 347 GPIO_IRQ_level_low &= ~(1 << line); 348 if (type & IRQT_HIGH) 349 GPIO_IRQ_level_high |= 1 << line; 350 else 351 GPIO_IRQ_level_high &= ~(1 << line); 352 update_gpio_int_csrs(); 353 354 return 0; 355} 356 357static void ixp2000_GPIO_irq_mask_ack(unsigned int irq) 358{ 359 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); 360 361 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 362 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 363 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0))); 364} 365 366static void ixp2000_GPIO_irq_mask(unsigned int irq) 367{ 368 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); 369} 370 371static void ixp2000_GPIO_irq_unmask(unsigned int irq) 372{ 373 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); 374} 375 376static struct irq_chip ixp2000_GPIO_irq_chip = { 377 .ack = ixp2000_GPIO_irq_mask_ack, 378 .mask = ixp2000_GPIO_irq_mask, 379 .unmask = ixp2000_GPIO_irq_unmask, 380 .set_type = ixp2000_GPIO_irq_type, 381}; 382 383static void ixp2000_pci_irq_mask(unsigned int irq) 384{ 385 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; 386 if (irq == IRQ_IXP2000_PCIA) 387 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26))); 388 else if (irq == IRQ_IXP2000_PCIB) 389 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27))); 390} 391 392static void ixp2000_pci_irq_unmask(unsigned int irq) 393{ 394 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; 395 if (irq == IRQ_IXP2000_PCIA) 396 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26))); 397 else if (irq == IRQ_IXP2000_PCIB) 398 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27))); 399} 400 401/* 402 * Error interrupts. These are used extensively by the microengine drivers 403 */ 404static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc) 405{ 406 int i; 407 unsigned long status = *IXP2000_IRQ_ERR_STATUS; 408 409 for(i = 31; i >= 0; i--) { 410 if(status & (1 << i)) { 411 desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i; 412 desc_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc); 413 } 414 } 415} 416 417static void ixp2000_err_irq_mask(unsigned int irq) 418{ 419 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR, 420 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))); 421} 422 423static void ixp2000_err_irq_unmask(unsigned int irq) 424{ 425 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET, 426 (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))); 427} 428 429static struct irq_chip ixp2000_err_irq_chip = { 430 .ack = ixp2000_err_irq_mask, 431 .mask = ixp2000_err_irq_mask, 432 .unmask = ixp2000_err_irq_unmask 433}; 434 435static struct irq_chip ixp2000_pci_irq_chip = { 436 .ack = ixp2000_pci_irq_mask, 437 .mask = ixp2000_pci_irq_mask, 438 .unmask = ixp2000_pci_irq_unmask 439}; 440 441static void ixp2000_irq_mask(unsigned int irq) 442{ 443 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq)); 444} 445 446static void ixp2000_irq_unmask(unsigned int irq) 447{ 448 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq)); 449} 450 451static struct irq_chip ixp2000_irq_chip = { 452 .ack = ixp2000_irq_mask, 453 .mask = ixp2000_irq_mask, 454 .unmask = ixp2000_irq_unmask 455}; 456 457void __init ixp2000_init_irq(void) 458{ 459 int irq; 460 461 /* 462 * Mask all sources 463 */ 464 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff); 465 ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff); 466 467 /* clear all GPIO edge/level detects */ 468 ixp2000_reg_write(IXP2000_GPIO_REDR, 0); 469 ixp2000_reg_write(IXP2000_GPIO_FEDR, 0); 470 ixp2000_reg_write(IXP2000_GPIO_LSHR, 0); 471 ixp2000_reg_write(IXP2000_GPIO_LSLR, 0); 472 ixp2000_reg_write(IXP2000_GPIO_INCR, -1); 473 474 /* clear PCI interrupt sources */ 475 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0); 476 477 /* 478 * Certain bits in the IRQ status register of the 479 * IXP2000 are reserved. Instead of trying to map 480 * things non 1:1 from bit position to IRQ number, 481 * we mark the reserved IRQs as invalid. This makes 482 * our mask/unmask code much simpler. 483 */ 484 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { 485 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { 486 set_irq_chip(irq, &ixp2000_irq_chip); 487 set_irq_handler(irq, handle_level_irq); 488 set_irq_flags(irq, IRQF_VALID); 489 } else set_irq_flags(irq, 0); 490 } 491 492 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { 493 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & 494 IXP2000_VALID_ERR_IRQ_MASK) { 495 set_irq_chip(irq, &ixp2000_err_irq_chip); 496 set_irq_handler(irq, handle_level_irq); 497 set_irq_flags(irq, IRQF_VALID); 498 } 499 else 500 set_irq_flags(irq, 0); 501 } 502 set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); 503 504 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { 505 set_irq_chip(irq, &ixp2000_GPIO_irq_chip); 506 set_irq_handler(irq, handle_level_irq); 507 set_irq_flags(irq, IRQF_VALID); 508 } 509 set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); 510 511 /* 512 * Enable PCI irqs. The actual PCI[AB] decoding is done in 513 * entry-macro.S, so we don't need a chained handler for the 514 * PCI interrupt source. 515 */ 516 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); 517 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { 518 set_irq_chip(irq, &ixp2000_pci_irq_chip); 519 set_irq_handler(irq, handle_level_irq); 520 set_irq_flags(irq, IRQF_VALID); 521 } 522} 523