1/* 2 * Broadcom SiliconBackplane hardware register definitions. 3 * 4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: sbconfig.h,v 13.70 2008/03/28 19:17:04 Exp $ 19 */ 20 21#ifndef _SBCONFIG_H 22#define _SBCONFIG_H 23 24/* cpp contortions to concatenate w/arg prescan */ 25#ifndef PAD 26#define _PADLINE(line) pad ## line 27#define _XSTR(line) _PADLINE(line) 28#define PAD _XSTR(__LINE__) 29#endif 30 31/* enumeration in SB is based on the premise that cores are contiguos in the 32 * enumeration space. 33 */ 34#define SB_BUS_SIZE 0x10000 /* Each bus gets 64Kbytes for cores */ 35#define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE) 36#define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /* Max cores per bus */ 37 38/* 39 * Sonics Configuration Space Registers. 40 */ 41#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */ 42#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */ 43 44#define SBIPSFLAG 0x08 45#define SBTPSFLAG 0x18 46#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */ 47#define SBTMERRLOG 0x50 /* sonics >= 2.3 */ 48#define SBADMATCH3 0x60 49#define SBADMATCH2 0x68 50#define SBADMATCH1 0x70 51#define SBIMSTATE 0x90 52#define SBINTVEC 0x94 53#define SBTMSTATELOW 0x98 54#define SBTMSTATEHIGH 0x9c 55#define SBBWA0 0xa0 56#define SBIMCONFIGLOW 0xa8 57#define SBIMCONFIGHIGH 0xac 58#define SBADMATCH0 0xb0 59#define SBTMCONFIGLOW 0xb8 60#define SBTMCONFIGHIGH 0xbc 61#define SBBCONFIG 0xc0 62#define SBBSTATE 0xc8 63#define SBACTCNFG 0xd8 64#define SBFLAGST 0xe8 65#define SBIDLOW 0xf8 66#define SBIDHIGH 0xfc 67 68/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have 69 * a few registers *below* that line. I think it would be very confusing to try 70 * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here, 71 */ 72 73#define SBIMERRLOGA 0xea8 74#define SBIMERRLOG 0xeb0 75#define SBTMPORTCONNID0 0xed8 76#define SBTMPORTLOCK0 0xef8 77 78#ifndef _LANGUAGE_ASSEMBLY 79 80typedef volatile struct _sbconfig { 81 uint32 PAD[2]; 82 uint32 sbipsflag; /* initiator port ocp slave flag */ 83 uint32 PAD[3]; 84 uint32 sbtpsflag; /* target port ocp slave flag */ 85 uint32 PAD[11]; 86 uint32 sbtmerrloga; /* (sonics >= 2.3) */ 87 uint32 PAD; 88 uint32 sbtmerrlog; /* (sonics >= 2.3) */ 89 uint32 PAD[3]; 90 uint32 sbadmatch3; /* address match3 */ 91 uint32 PAD; 92 uint32 sbadmatch2; /* address match2 */ 93 uint32 PAD; 94 uint32 sbadmatch1; /* address match1 */ 95 uint32 PAD[7]; 96 uint32 sbimstate; /* initiator agent state */ 97 uint32 sbintvec; /* interrupt mask */ 98 uint32 sbtmstatelow; /* target state */ 99 uint32 sbtmstatehigh; /* target state */ 100 uint32 sbbwa0; /* bandwidth allocation table0 */ 101 uint32 PAD; 102 uint32 sbimconfiglow; /* initiator configuration */ 103 uint32 sbimconfighigh; /* initiator configuration */ 104 uint32 sbadmatch0; /* address match0 */ 105 uint32 PAD; 106 uint32 sbtmconfiglow; /* target configuration */ 107 uint32 sbtmconfighigh; /* target configuration */ 108 uint32 sbbconfig; /* broadcast configuration */ 109 uint32 PAD; 110 uint32 sbbstate; /* broadcast state */ 111 uint32 PAD[3]; 112 uint32 sbactcnfg; /* activate configuration */ 113 uint32 PAD[3]; 114 uint32 sbflagst; /* current sbflags */ 115 uint32 PAD[3]; 116 uint32 sbidlow; /* identification */ 117 uint32 sbidhigh; /* identification */ 118} sbconfig_t; 119 120#endif /* _LANGUAGE_ASSEMBLY */ 121 122/* sbipsflag */ 123#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */ 124#define SBIPS_INT1_SHIFT 0 125#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */ 126#define SBIPS_INT2_SHIFT 8 127#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */ 128#define SBIPS_INT3_SHIFT 16 129#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */ 130#define SBIPS_INT4_SHIFT 24 131 132/* sbtpsflag */ 133#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */ 134#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */ 135 136/* sbtmerrlog */ 137#define SBTMEL_CM 0x00000007 /* command */ 138#define SBTMEL_CI 0x0000ff00 /* connection id */ 139#define SBTMEL_EC 0x0f000000 /* error code */ 140#define SBTMEL_ME 0x80000000 /* multiple error */ 141 142/* sbimstate */ 143#define SBIM_PC 0xf /* pipecount */ 144#define SBIM_AP_MASK 0x30 /* arbitration policy */ 145#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */ 146#define SBIM_AP_TS 0x10 /* use timesliaces only */ 147#define SBIM_AP_TK 0x20 /* use token only */ 148#define SBIM_AP_RSV 0x30 /* reserved */ 149#define SBIM_IBE 0x20000 /* inbanderror */ 150#define SBIM_TO 0x40000 /* timeout */ 151#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */ 152#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */ 153 154/* sbtmstatelow */ 155#define SBTML_RESET 0x0001 /* reset */ 156#define SBTML_REJ_MASK 0x0006 /* reject field */ 157#define SBTML_REJ 0x0002 /* reject */ 158#define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */ 159 160#define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */ 161 162/* sbtmstatehigh */ 163#define SBTMH_SERR 0x0001 /* serror */ 164#define SBTMH_INT 0x0002 /* interrupt */ 165#define SBTMH_BUSY 0x0004 /* busy */ 166#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */ 167 168#define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */ 169 170/* sbbwa0 */ 171#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */ 172#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */ 173#define SBBWA_TAB1_SHIFT 16 174 175/* sbimconfiglow */ 176#define SBIMCL_STO_MASK 0x7 /* service timeout */ 177#define SBIMCL_RTO_MASK 0x70 /* request timeout */ 178#define SBIMCL_RTO_SHIFT 4 179#define SBIMCL_CID_MASK 0xff0000 /* connection id */ 180#define SBIMCL_CID_SHIFT 16 181 182/* sbimconfighigh */ 183#define SBIMCH_IEM_MASK 0xc /* inband error mode */ 184#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */ 185#define SBIMCH_TEM_SHIFT 4 186#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */ 187#define SBIMCH_BEM_SHIFT 6 188 189/* sbadmatch0 */ 190#define SBAM_TYPE_MASK 0x3 /* address type */ 191#define SBAM_AD64 0x4 /* reserved */ 192#define SBAM_ADINT0_MASK 0xf8 /* type0 size */ 193#define SBAM_ADINT0_SHIFT 3 194#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */ 195#define SBAM_ADINT1_SHIFT 3 196#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */ 197#define SBAM_ADINT2_SHIFT 3 198#define SBAM_ADEN 0x400 /* enable */ 199#define SBAM_ADNEG 0x800 /* negative decode */ 200#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */ 201#define SBAM_BASE0_SHIFT 8 202#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */ 203#define SBAM_BASE1_SHIFT 12 204#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */ 205#define SBAM_BASE2_SHIFT 16 206 207/* sbtmconfiglow */ 208#define SBTMCL_CD_MASK 0xff /* clock divide */ 209#define SBTMCL_CO_MASK 0xf800 /* clock offset */ 210#define SBTMCL_CO_SHIFT 11 211#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */ 212#define SBTMCL_IF_SHIFT 18 213#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */ 214#define SBTMCL_IM_SHIFT 24 215 216/* sbtmconfighigh */ 217#define SBTMCH_BM_MASK 0x3 /* busy mode */ 218#define SBTMCH_RM_MASK 0x3 /* retry mode */ 219#define SBTMCH_RM_SHIFT 2 220#define SBTMCH_SM_MASK 0x30 /* stop mode */ 221#define SBTMCH_SM_SHIFT 4 222#define SBTMCH_EM_MASK 0x300 /* sb error mode */ 223#define SBTMCH_EM_SHIFT 8 224#define SBTMCH_IM_MASK 0xc00 /* int mode */ 225#define SBTMCH_IM_SHIFT 10 226 227/* sbbconfig */ 228#define SBBC_LAT_MASK 0x3 /* sb latency */ 229#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */ 230#define SBBC_MAX0_SHIFT 16 231#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */ 232#define SBBC_MAX1_SHIFT 20 233 234/* sbbstate */ 235#define SBBS_SRD 0x1 /* st reg disable */ 236#define SBBS_HRD 0x2 /* hold reg disable */ 237 238/* sbidlow */ 239#define SBIDL_CS_MASK 0x3 /* config space */ 240#define SBIDL_AR_MASK 0x38 /* # address ranges supported */ 241#define SBIDL_AR_SHIFT 3 242#define SBIDL_SYNCH 0x40 /* sync */ 243#define SBIDL_INIT 0x80 /* initiator */ 244#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */ 245#define SBIDL_MINLAT_SHIFT 8 246#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */ 247#define SBIDL_MAXLAT_SHIFT 12 248#define SBIDL_FIRST 0x10000 /* this initiator is first */ 249#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */ 250#define SBIDL_CW_SHIFT 18 251#define SBIDL_TP_MASK 0xf00000 /* target ports */ 252#define SBIDL_TP_SHIFT 20 253#define SBIDL_IP_MASK 0xf000000 /* initiator ports */ 254#define SBIDL_IP_SHIFT 24 255#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */ 256#define SBIDL_RV_SHIFT 28 257#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */ 258#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */ 259 260/* sbidhigh */ 261#define SBIDH_RC_MASK 0x000f /* revision code */ 262#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */ 263#define SBIDH_RCE_SHIFT 8 264#define SBCOREREV(sbidh) \ 265 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) 266#define SBIDH_CC_MASK 0x8ff0 /* core code */ 267#define SBIDH_CC_SHIFT 4 268#define SBIDH_VC_MASK 0xffff0000 /* vendor code */ 269#define SBIDH_VC_SHIFT 16 270 271#define SB_COMMIT 0xfd8 /* update buffered registers value */ 272 273/* vendor codes */ 274#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */ 275 276#endif /* _SBCONFIG_H */ 277