1/* 2 * BCM43XX PCI/E core sw API definitions. 3 * 4 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: nicpci.h 401759 2013-05-13 16:08:08Z $ 19 */ 20 21#ifndef _NICPCI_H 22#define _NICPCI_H 23 24#if defined(BCMDHDUSB) || (defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)) 25#define pcicore_find_pci_capability(a, b, c, d) (0) 26#define pcie_readreg(a, b, c, d) (0) 27#define pcie_writereg(a, b, c, d, e) (0) 28 29#define pcie_clkreq(a, b, c) (0) 30#define pcie_lcreg(a, b, c) (0) 31#define pcie_ltrenable(a, b, c) (0) 32#define pcie_obffenable(a, b, c) (0) 33#define pcie_ltr_reg(a, b, c, d) (0) 34#define pcieltrspacing_reg(a, b, c) (0) 35#define pcieltrhysteresiscnt_reg(a, b, c) (0) 36 37#define pcicore_init(a, b, c) (0x0dadbeef) 38#define pcicore_deinit(a) do { } while (0) 39#define pcicore_attach(a, b, c) do { } while (0) 40#define pcicore_hwup(a) do { } while (0) 41#define pcicore_up(a, b) do { } while (0) 42#define pcicore_sleep(a) do { } while (0) 43#define pcicore_down(a, b) do { } while (0) 44 45#define pcie_war_ovr_aspm_update(a, b) do { } while (0) 46#define pcie_power_save_enable(a, b) do { } while (0) 47 48#define pcicore_pcieserdesreg(a, b, c, d, e) (0) 49#define pcicore_pciereg(a, b, c, d, e) (0) 50#if defined(BCMDBG_DUMP) 51#define pcicore_dump_pcieregs(a, b) (0) 52#endif 53#if defined(WLTEST) || defined(BCMDBG_DUMP) 54#define pcicore_dump_pcieinfo(a, b) (0) 55#endif 56 57#define pcicore_pmecap_fast(a) (FALSE) 58#define pcicore_pmeen(a) do { } while (0) 59#define pcicore_pmeclr(a) do { } while (0) 60#define pcicore_pmestat(a) (FALSE) 61#define pcicore_pmestatclr(a) do { } while (0) 62#define pcie_set_request_size(pch, size) do { } while (0) 63#define pcie_get_request_size(pch) (0) 64#define pcie_set_maxpayload_size(pch, size) do { } while (0) 65#define pcie_get_maxpayload_size(pch) (0) 66#define pcie_get_ssid(a) (0) 67#define pcie_get_bar0(a) (0) 68#define pcie_configspace_cache(a) (0) 69#define pcie_configspace_restore(a) (0) 70#define pcie_configspace_get(a, b, c) (0) 71#define pcie_set_L1_entry_time(a, b) do { } while (0) 72#define pcie_disable_TL_clk_gating(a) do { } while (0) 73#define pcie_get_link_speed(a) (0) 74#define pcie_set_error_injection(a, b) do { } while (0) 75#define pcie_set_L1substate(a, b) do { } while (0) 76#define pcie_get_L1substate(a) (0) 77#define pcie_survive_perst(a, b, c) (0) 78#else 79struct sbpcieregs; 80 81extern uint8 pcicore_find_pci_capability(osl_t *osh, uint8 req_cap_id, 82 uchar *buf, uint32 *buflen); 83extern uint pcie_readreg(si_t *sih, struct sbpcieregs *pcieregs, uint addrtype, uint offset); 84extern uint pcie_writereg(si_t *sih, struct sbpcieregs *pcieregs, uint addrtype, uint offset, 85 uint val); 86 87extern uint8 pcie_clkreq(void *pch, uint32 mask, uint32 val); 88extern uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val); 89extern void pcie_set_L1_entry_time(void *pch, uint32 val); 90extern void pcie_disable_TL_clk_gating(void *pch); 91extern void pcie_set_error_injection(void *pch, uint32 mode); 92extern uint8 pcie_ltrenable(void *pch, uint32 mask, uint32 val); 93extern uint8 pcie_obffenable(void *pch, uint32 mask, uint32 val); 94extern void pcie_set_L1substate(void *pch, uint32 substate); 95extern uint32 pcie_get_L1substate(void *pch); 96extern uint32 pcie_ltr_reg(void *pch, uint32 reg, uint32 mask, uint32 val); 97extern uint32 pcieltrspacing_reg(void *pch, uint32 mask, uint32 val); 98extern uint32 pcieltrhysteresiscnt_reg(void *pch, uint32 mask, uint32 val); 99 100extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs); 101extern void pcicore_deinit(void *pch); 102extern void pcicore_attach(void *pch, char *pvars, int state); 103extern void pcicore_hwup(void *pch); 104extern void pcicore_up(void *pch, int state); 105extern void pcicore_sleep(void *pch); 106extern void pcicore_down(void *pch, int state); 107 108extern void pcie_war_ovr_aspm_update(void *pch, uint8 aspm); 109extern void pcie_power_save_enable(void *pch, bool enable); 110 111extern uint32 pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, 112 uint32 mask, uint32 val); 113 114extern uint32 pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type); 115 116#if defined(WLTEST) || defined(BCMDBG_DUMP) 117extern int pcicore_dump_pcieinfo(void *pch, struct bcmstrbuf *b); 118#endif 119 120#if defined(BCMDBG_DUMP) 121extern int pcicore_dump_pcieregs(void *pch, struct bcmstrbuf *b); 122#endif 123 124 125extern bool pcicore_pmecap_fast(osl_t *osh); 126extern void pcicore_pmeen(void *pch); 127extern void pcicore_pmeclr(void *pch); 128extern void pcicore_pmestatclr(void *pch); 129extern bool pcicore_pmestat(void *pch); 130extern void pcie_set_request_size(void *pch, uint16 size); 131extern uint16 pcie_get_request_size(void *pch); 132extern void pcie_set_maxpayload_size(void *pch, uint16 size); 133extern uint16 pcie_get_maxpayload_size(void *pch); 134extern uint16 pcie_get_ssid(void *pch); 135extern uint32 pcie_get_bar0(void *pch); 136extern int pcie_configspace_cache(void* pch); 137extern int pcie_configspace_restore(void* pch); 138extern int pcie_configspace_get(void* pch, uint8 *buf, uint size); 139extern uint32 pcie_get_link_speed(void* pch); 140extern uint32 pcie_survive_perst(void* pch, uint32 mask, uint32 val); 141#endif 142 143#define PCIE_MRRS_OVERRIDE(sih) \ 144 ((pi->sih->boardvendor == VENDOR_APPLE) && \ 145 ((pi->sih->boardtype == BCM94331X19) || \ 146 (pi->sih->boardtype == BCM94331X28) || \ 147 (pi->sih->boardtype == BCM94331X28B) || \ 148 (pi->sih->boardtype == BCM94331X29B) || \ 149 (pi->sih->boardtype == BCM94331X29D) || \ 150 (pi->sih->boardtype == BCM94331X19C) || \ 151 (pi->sih->boardtype == BCM94331X33))) 152 153#define PCIE_DRIVE_STRENGTH_OVERRIDE(sih) \ 154 ((CHIPID((sih)->chip) == BCM4331_CHIP_ID) && \ 155 ((sih)->boardtype == BCM94331X19 || \ 156 (sih)->boardtype == BCM94331X28 || \ 157 (sih)->boardtype == BCM94331X29B || \ 158 (sih)->boardtype == BCM94331X19C)) 159#endif /* _NICPCI_H */ 160