1/* 2 * Broadcom SiliconBackplane MIPS definitions 3 * 4 * SB MIPS cores are custom MIPS32 processors with SiliconBackplane 5 * OCP interfaces. The CP0 processor ID is 0x00024000, where bits 6 * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP 7 * interface. The core revision is stored in the SB ID register in SB 8 * configuration space. 9 * 10 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 11 * 12 * Permission to use, copy, modify, and/or distribute this software for any 13 * purpose with or without fee is hereby granted, provided that the above 14 * copyright notice and this permission notice appear in all copies. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 17 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 20 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 21 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 22 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 23 * 24 * $Id: mips33_core.h,v 13.3 2008/03/25 22:43:52 Exp $ 25 */ 26 27#ifndef _mips33_core_h_ 28#define _mips33_core_h_ 29 30#include <mipsinc.h> 31 32#ifndef _LANGUAGE_ASSEMBLY 33 34/* cpp contortions to concatenate w/arg prescan */ 35#ifndef PAD 36#define _PADLINE(line) pad ## line 37#define _XSTR(line) _PADLINE(line) 38#define PAD _XSTR(__LINE__) 39#endif /* PAD */ 40 41typedef volatile struct { 42 uint32 corecontrol; 43 uint32 PAD[2]; 44 uint32 biststatus; 45 uint32 PAD[4]; 46 uint32 intstatus; 47 uint32 intmask; 48 uint32 timer; 49} mips33regs_t; 50 51#endif /* _LANGUAGE_ASSEMBLY */ 52 53#endif /* _mips33_core_h_ */ 54