1/* 2 * HND Minimal OS Abstraction Layer. 3 * 4 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: min_osl.h 341899 2012-06-29 04:06:38Z $ 19 */ 20 21#ifndef _min_osl_h_ 22#define _min_osl_h_ 23 24#include <typedefs.h> 25#include <hndsoc.h> 26#include <sbhndcpu.h> 27#include <bcmstdlib.h> 28 29#ifdef mips 30/* Cache support */ 31extern void caches_on(void); 32extern void blast_dcache(void); 33extern void blast_icache(void); 34#elif defined(__ARM_ARCH_7A__) 35extern void caches_on(void); 36extern void blast_dcache(void); 37extern void blast_icache(void); 38#else /* !mips */ 39/* Cache support (or lack thereof) */ 40static inline void caches_on(void) { return; }; 41static inline void blast_dcache(void) { return; }; 42static inline void blast_icache(void) { return; }; 43#endif /* mips */ 44 45/* assert & debugging */ 46#define ASSERT(exp) do {} while (0) 47#define BCMDBG_TRACE(val) do {} while (0) 48 49/* PCMCIA attribute space access macros */ 50#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \ 51 ASSERT(0) 52#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \ 53 ASSERT(0) 54 55/* PCI configuration space access macros */ 56#define OSL_PCI_READ_CONFIG(loc, offset, size) \ 57 (offset == 8 ? 0 : 0xffffffff) 58#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \ 59 do {} while (0) 60 61/* PCI device bus # and slot # */ 62#define OSL_PCI_BUS(osh) (0) 63#define OSL_PCI_SLOT(osh) (0) 64 65/* register access macros */ 66#ifdef IL_BIGENDIAN 67#ifdef BCMHND74K 68 69#define wreg32(r, v) (*(volatile uint32 *)((uint32)(r) ^ 4) = (uint32)(v)) 70#define rreg32(r) (*(volatile uint32 *)((uint32)(r) ^ 4)) 71#define wreg16(r, v) (*(volatile uint16 *)((uint32)(r) ^ 6) = (uint16)(v)) 72#define rreg16(r) (*(volatile uint16 *)((uint32)(r) ^ 6)) 73#define wreg8(r, v) (*(volatile uint8 *)((uint32)(r) ^ 7) = (uint8)(v)) 74#define rreg8(r) (*(volatile uint8 *)((uint32)(r) ^ 7)) 75 76#else /* !BCMHND74K */ 77 78#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v)) 79#define rreg32(r) (*(volatile uint32*)(r)) 80#define wreg16(r, v) (*(volatile uint16 *)((uint32)(r) ^ 2) = (uint16)(v)) 81#define rreg16(r) (*(volatile uint16 *)((uint32)(r) ^ 2)) 82#define wreg8(r, v) (*(volatile uint8 *)((uint32)(r) ^ 3) = (uint8)(v)) 83#define rreg8(r) (*(volatile uint8 *)((uint32)(r) ^ 3)) 84 85#endif /* BCMHND74K */ 86 87#else /* !IL_BIGENDIAN */ 88 89#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v)) 90#define rreg32(r) (*(volatile uint32*)(r)) 91#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v)) 92#define rreg16(r) (*(volatile uint16*)(r)) 93#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v)) 94#define rreg8(r) (*(volatile uint8*)(r)) 95 96#endif /* IL_BIGENDIAN */ 97 98#define R_REG(osh, r) ({ \ 99 __typeof(*(r)) __osl_v; \ 100 switch (sizeof(*(r))) { \ 101 case sizeof(uint8): __osl_v = rreg8((void *)(r)); break; \ 102 case sizeof(uint16): __osl_v = rreg16((void *)(r)); break; \ 103 case sizeof(uint32): __osl_v = rreg32((void *)(r)); break; \ 104 } \ 105 __osl_v; \ 106}) 107#define W_REG(osh, r, v) do { \ 108 switch (sizeof(*(r))) { \ 109 case sizeof(uint8): wreg8((void *)(r), (v)); break; \ 110 case sizeof(uint16): wreg16((void *)(r), (v)); break; \ 111 case sizeof(uint32): wreg32((void *)(r), (v)); break; \ 112 } \ 113} while (0) 114#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v)) 115#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v)) 116 117/* general purpose memory allocation */ 118#define MALLOC(osh, size) malloc(size) 119#define MALLOC_ALIGN(osh, size, align_bits) malloc_align((size), (align_bits)) 120#define MFREE(osh, addr, size) free(addr) 121#define MALLOCED(osh) 0 122#define MALLOC_FAILED(osh) 0 123#define MALLOC_DUMP(osh, b) 124extern int free(void *ptr); 125extern void *malloc(uint size); 126extern void *malloc_align(uint size, uint align_bits); 127 128/* uncached virtual address */ 129#ifdef __mips__ 130#define OSL_UNCACHED(va) ((void *)KSEG1ADDR((ulong)(va))) 131#define OSL_CACHED(va) ((void *)KSEG0ADDR((ulong)(va))) 132#elif defined(__ARM_ARCH_7A__) 133#define OSL_UNCACHED(va) ((void *)(va)) 134#define OSL_CACHED(va) ((void *)(va)) 135/* ARM NorthStar */ 136#define OSL_CACHE_FLUSH(va, len) _cfe_flushcache_rang(va, len) 137#else 138#define OSL_UNCACHED(va) ((void *)(va)) 139#define OSL_CACHED(va) ((void *)(va)) 140#define PHYSADDR_MASK 0xffffffff 141#define PHYSADDR(va) ((uintptr)(va)) 142#endif 143 144#ifdef __mips__ 145#define OSL_PREF_RANGE_LD(va, sz) prefetch_range_PREF_LOAD_RETAINED(va, sz) 146#define OSL_PREF_RANGE_ST(va, sz) prefetch_range_PREF_STORE_RETAINED(va, sz) 147#else /* __mips__ */ 148#define OSL_PREF_RANGE_LD(va, sz) 149#define OSL_PREF_RANGE_ST(va, sz) 150#endif /* __mips__ */ 151 152/* host/bus architecture-specific address byte swap */ 153#define BUS_SWAP32(v) (v) 154 155/* microsecond delay */ 156#define OSL_DELAY(usec) udelay(usec) 157extern void udelay(uint32 usec); 158 159/* get processor cycle count */ 160#define OSL_GETCYCLES(x) ((x) = osl_getcycles()) 161extern uint32 osl_getcycles(void); 162 163/* map/unmap physical to virtual I/O */ 164#define REG_MAP(pa, size) (OSL_UNCACHED(pa)) 165#define REG_UNMAP(va) do {} while (0) 166 167/* dereference an address that may cause a bus exception */ 168#define BUSPROBE(val, addr) (uint32 *)(addr) = (val) 169 170/* Misc stubs */ 171#define osl_attach(pdev) ((osl_t*)pdev) 172#define osl_detach(osh) 173 174#define PKTFREESETCB(osh, _tx_fn, _tx_ctx) 175 176extern void *osl_init(void); 177#define OSL_ERROR(bcmerror) osl_error(bcmerror) 178extern int osl_error(int); 179 180/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */ 181#define PKTBUFSZ (MAXPKTBUFSZ - LBUFSZ) 182 183/* packet primitives */ 184#define PKTGET(osh, len, send) ((void *)NULL) 185#define PKTFREE(osh, p, send) 186#define PKTDATA(osh, lb) ((void *)NULL) 187#define PKTLEN(osh, lb) 0 188#define PKTHEADROOM(osh, lb) 0 189#define PKTTAILROOM(osh, lb) 0 190#define PKTNEXT(osh, lb) ((void *)NULL) 191#define PKTSETNEXT(osh, lb, x) 192#define PKTSETLEN(osh, lb, len) 193#define PKTPUSH(osh, lb, bytes) 194#define PKTPULL(osh, lb, bytes) 195#define PKTDUP(osh, p) 196#define PKTTAG(lb) ((void *)NULL) 197#define PKTLINK(lb) ((void *)NULL) 198#define PKTSETLINK(lb, x) 199#define PKTPRIO(lb) 0 200#define PKTSETPRIO(lb, x) 201#define PKTSHARED(lb) 1 202#define PKTALLOCED(osh) 0 203#define PKTLIST_DUMP(osh, buf) 204#define PKTFRMNATIVE(osh, lb) ((void *)NULL) 205#define PKTTONATIVE(osh, p) ((struct lbuf *)NULL) 206#define PKTSETPOOL(osh, lb, x, y) do {} while (0) 207#define PKTPOOL(osh, lb) FALSE 208#define PKTSHRINK(osh, m) (m) 209 210/* Global ASSERT type */ 211extern uint32 g_assert_type; 212 213/* Kernel: File Operations: start */ 214#define osl_os_open_image(filename) NULL 215#define osl_os_get_image_block(buf, len, image) 0 216#define osl_os_close_image(image) do {} while (0) 217/* Kernel: File Operations: end */ 218 219#endif /* _min_osl_h_ */ 220