1/*
2 * gmacdefs - Broadcom gmac (Unimac) specific definitions
3 *
4 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: gmac_core.h 376344 2012-12-24 21:10:09Z $
18 */
19
20#ifndef	_gmac_core_h_
21#define	_gmac_core_h_
22
23
24/* cpp contortions to concatenate w/arg prescan */
25#ifndef PAD
26#define	_PADLINE(line)	pad ## line
27#define	_XSTR(line)	_PADLINE(line)
28#define	PAD		_XSTR(__LINE__)
29#endif	/* PAD */
30
31/* We have 4 DMA TX channels */
32#define	GMAC_NUM_DMA_TX		4
33
34typedef volatile struct {
35	dma64regs_t	dmaxmt;		/* dma tx */
36	uint32 PAD[2];
37	dma64regs_t	dmarcv;		/* dma rx */
38	uint32 PAD[2];
39} dma64_t;
40
41/*
42 * Host Interface Registers
43 */
44typedef volatile struct _gmacregs {
45	uint32	devcontrol;		/* 0x000 */
46	uint32	devstatus;		/* 0x004 */
47	uint32	PAD;
48	uint32	biststatus;		/* 0x00c */
49	uint32	PAD[4];
50	uint32	intstatus;		/* 0x020 */
51	uint32	intmask;		/* 0x024 */
52	uint32	gptimer;		/* 0x028 */
53	uint32	PAD[53];
54	uint32	intrecvlazy;		/* 0x100 */
55	uint32	flowctlthresh;		/* 0x104 */
56	uint32	wrrthresh;		/* 0x108 */
57	uint32	gmac_idle_cnt_thresh;	/* 0x10c */
58	uint32	PAD[28];
59	uint32	phyaccess;		/* 0x180 */
60	uint32	PAD;
61	uint32	phycontrol;		/* 0x188 */
62	uint32	txqctl;			/* 0x18c */
63	uint32	rxqctl;			/* 0x190 */
64	uint32	gpioselect;		/* 0x194 */
65	uint32	gpio_output_en;		/* 0x198 */
66	uint32	PAD[17];
67	uint32	clk_ctl_st;		/* 0x1e0 */
68	uint32	hw_war;			/* 0x1e4 */
69	uint32	pwrctl;			/* 0x1e8 */
70	uint32	PAD[5];
71
72	dma64_t dmaregs[GMAC_NUM_DMA_TX];
73
74	/* GAMC MIB counters */
75	gmacmib_t	mib;
76	uint32	PAD[245];
77
78	uint32	unimacversion;		/* 0x800 */
79	uint32	hdbkpctl;		/* 0x804 */
80	uint32	cmdcfg;			/* 0x808 */
81	uint32	macaddrhigh;		/* 0x80c */
82	uint32	macaddrlow;		/* 0x810 */
83	uint32	rxmaxlength;		/* 0x814 */
84	uint32	pausequanta;		/* 0x818 */
85	uint32	PAD[10];
86	uint32	macmode;		/* 0x844 */
87	uint32	outertag;		/* 0x848 */
88	uint32	innertag;		/* 0x84c */
89	uint32	PAD[3];
90	uint32	txipg;			/* 0x85c */
91	uint32	PAD[180];
92	uint32	pausectl;		/* 0xb30 */
93	uint32	txflush;		/* 0xb34 */
94	uint32	rxstatus;		/* 0xb38 */
95	uint32	txstatus;		/* 0xb3c */
96} gmacregs_t;
97
98#define	GM_MIB_BASE		0x300
99#define	GM_MIB_LIMIT		0x800
100
101/*
102 * register-specific flag definitions
103 */
104
105/* device control */
106#define	DC_TSM			0x00000002
107#define	DC_CFCO			0x00000004
108#define	DC_RLSS			0x00000008
109#define	DC_MROR			0x00000010
110#define	DC_FCM_MASK		0x00000060
111#define	DC_FCM_SHIFT		5
112#define	DC_NAE			0x00000080
113#define	DC_TF			0x00000100
114#define	DC_RDS_MASK		0x00030000
115#define	DC_RDS_SHIFT		16
116#define	DC_TDS_MASK		0x000c0000
117#define	DC_TDS_SHIFT		18
118
119/* device status */
120#define	DS_RBF			0x00000001
121#define	DS_RDF			0x00000002
122#define	DS_RIF			0x00000004
123#define	DS_TBF			0x00000008
124#define	DS_TDF			0x00000010
125#define	DS_TIF			0x00000020
126#define	DS_PO			0x00000040
127#define	DS_MM_MASK		0x00000300
128#define	DS_MM_SHIFT		8
129
130/* bist status */
131#define	BS_MTF			0x00000001
132#define	BS_MRF			0x00000002
133#define	BS_TDB			0x00000004
134#define	BS_TIB			0x00000008
135#define	BS_TBF			0x00000010
136#define	BS_RDB			0x00000020
137#define	BS_RIB			0x00000040
138#define	BS_RBF			0x00000080
139#define	BS_URTF			0x00000100
140#define	BS_UTF			0x00000200
141#define	BS_URF			0x00000400
142
143/* interrupt status and mask registers */
144#define	I_MRO			0x00000001
145#define	I_MTO			0x00000002
146#define	I_TFD			0x00000004
147#define	I_LS			0x00000008
148#define	I_MDIO			0x00000010
149#define	I_MR			0x00000020
150#define	I_MT			0x00000040
151#define	I_TO			0x00000080
152#define	I_PDEE			0x00000400
153#define	I_PDE			0x00000800
154#define	I_DE			0x00001000
155#define	I_RDU			0x00002000
156#define	I_RFO			0x00004000
157#define	I_XFU			0x00008000
158#define	I_RI			0x00010000
159#define	I_XI0			0x01000000
160#define	I_XI1			0x02000000
161#define	I_XI2			0x04000000
162#define	I_XI3			0x08000000
163#define	I_INTMASK		0x0f01fcff
164#define	I_ERRMASK		0x0000fc00
165
166/* interrupt receive lazy */
167#define	IRL_TO_MASK		0x00ffffff
168#define	IRL_FC_MASK		0xff000000
169#define	IRL_FC_SHIFT		24
170
171/* flow control thresholds */
172#define	FCT_TT_MASK		0x00000fff
173#define	FCT_RT_MASK		0x0fff0000
174#define	FCT_RT_SHIFT		16
175
176/* txq aribter wrr thresholds */
177#define	WRRT_Q0T_MASK		0x000000ff
178#define	WRRT_Q1T_MASK		0x0000ff00
179#define	WRRT_Q1T_SHIFT		8
180#define	WRRT_Q2T_MASK		0x00ff0000
181#define	WRRT_Q2T_SHIFT		16
182#define	WRRT_Q3T_MASK		0xff000000
183#define	WRRT_Q3T_SHIFT		24
184
185/* phy access */
186#define	PA_DATA_MASK		0x0000ffff
187#define	PA_ADDR_MASK		0x001f0000
188#define	PA_ADDR_SHIFT		16
189#define	PA_REG_MASK		0x1f000000
190#define	PA_REG_SHIFT		24
191#define	PA_WRITE		0x20000000
192#define	PA_START		0x40000000
193
194/* phy control */
195#define	PC_EPA_MASK		0x0000001f
196#define	PC_MCT_MASK		0x007f0000
197#define	PC_MCT_SHIFT		16
198#define	PC_MTE			0x00800000
199
200/* rxq control */
201#define	RC_DBT_MASK		0x00000fff
202#define	RC_DBT_SHIFT		0
203#define	RC_PTE			0x00001000
204#define	RC_MDP_MASK		0x3f000000
205#define	RC_MDP_SHIFT		24
206
207#define RC_MAC_DATA_PERIOD	9
208
209/* txq control */
210#define	TC_DBT_MASK		0x00000fff
211#define	TC_DBT_SHIFT		0
212
213/* gpio select */
214#define	GS_GSC_MASK		0x0000000f
215#define	GS_GSC_SHIFT		0
216
217/* gpio output enable */
218#define	GS_GOE_MASK		0x0000ffff
219#define	GS_GOE_SHIFT		0
220
221/* clk control status */
222#define CS_FA			0x00000001
223#define CS_FH			0x00000002
224#define CS_FI			0x00000004
225#define CS_AQ			0x00000008
226#define CS_HQ			0x00000010
227#define CS_FC			0x00000020
228#define CS_ER			0x00000100
229#define CS_AA			0x00010000
230#define CS_HA			0x00020000
231#define CS_BA			0x00040000
232#define CS_BH			0x00080000
233#define CS_ES			0x01000000
234
235/* command config */
236#define	CC_TE			0x00000001
237#define	CC_RE			0x00000002
238#define	CC_ES_MASK		0x0000000c
239#define	CC_ES_SHIFT		2
240#define	CC_PROM			0x00000010
241#define	CC_PAD_EN		0x00000020
242#define	CC_CF			0x00000040
243#define	CC_PF			0x00000080
244#define	CC_RPI			0x00000100
245#define	CC_TAI			0x00000200
246#define	CC_HD			0x00000400
247#define	CC_HD_SHIFT		10
248#define CC_SR(corerev)  ((corerev == 4) ? 0x00002000 : 0x00000800)
249#define	CC_ML			0x00008000
250#define	CC_AE			0x00400000
251#define	CC_CFE			0x00800000
252#define	CC_NLC			0x01000000
253#define	CC_RL			0x02000000
254#define	CC_RED			0x04000000
255#define	CC_PE			0x08000000
256#define	CC_TPI			0x10000000
257#define	CC_AT			0x20000000
258
259/* mac addr high */
260#define	MH_HI_MASK		0xffff
261#define	MH_HI_SHIFT		16
262#define	MH_MID_MASK		0xffff
263#define	MH_MID_SHIFT		0
264
265/* mac addr low */
266#define	ML_LO_MASK		0xffff
267#define	ML_LO_SHIFT		0
268
269/* Core specific control flags */
270#define SICF_SWCLKE		0x0004
271#define SICF_SWRST		0x0008
272
273/* Core specific status flags */
274#define SISF_SW_ATTACHED	0x0800
275
276/* 4707 has 4 GMAC and need to be reset before start access */
277#define MAX_GMAC_CORES_4707	4
278
279#endif	/* _gmac_core_h_ */
280