1/* 2 * gmacdefs - Broadcom gmac (Unimac) specific definitions 3 * 4 * Copyright (C) 2013, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * $Id: gmac_common.h 376344 2012-12-24 21:10:09Z $ 18 */ 19 20#ifndef _gmac_common_core_h_ 21#define _gmac_common_core_h_ 22 23#ifndef PAD 24#define _PADLINE(line) pad ## line 25#define _XSTR(line) _PADLINE(line) 26#define PAD XSTR(__LINE__) 27#endif 28 29typedef volatile struct _gmac_commonregs { 30 uint32 stag0; 31 uint32 stag1; 32 uint32 stag2; 33 uint32 stag3; 34 uint32 PAD[4]; 35 uint32 parsercontrol; 36 uint32 mib_max_len; 37 uint32 PAD[54]; 38 uint32 phyaccess; 39 uint32 phycontrol; 40 uint32 PAD[2]; 41 uint32 gmac0_rgmii_cntl; 42 uint32 PAD[59]; 43 uint32 cfp_access; 44 uint32 PAD[3]; 45 uint32 cfp_tcam_data0; 46 uint32 cfp_tcam_data1; 47 uint32 cfp_tcam_data2; 48 uint32 cfp_tcam_data3; 49 uint32 cfp_tcam_data4; 50 uint32 cfp_tcam_data5; 51 uint32 cfp_tcam_data6; 52 uint32 cfp_tcam_data7; 53 uint32 cfp_tcam_mask0; 54 uint32 cfp_tcam_mask1; 55 uint32 cfp_tcam_mask2; 56 uint32 cfp_tcam_mask3; 57 uint32 cfp_tcam_mask4; 58 uint32 cfp_tcam_mask5; 59 uint32 cfp_tcam_mask6; 60 uint32 cfp_tcam_mask7; 61 uint32 cfp_action_data; 62 uint32 PAD[19]; 63 uint32 tcam_bist_cntl; 64 uint32 tcam_bist_status; 65 uint32 tcam_cmp_status; 66 uint32 tcam_disable; 67 uint32 PAD[16]; 68 uint32 tcam_test_cntl; 69 uint32 PAD[3]; 70 uint32 udf_0_a3_a0; 71 uint32 udf_0_a7_a4; 72 uint32 udf_0_a8; 73 uint32 PAD[1]; 74 uint32 udf_1_a3_a0; 75 uint32 udf_1_a7_a4; 76 uint32 udf_1_a8; 77 uint32 PAD[1]; 78 uint32 udf_2_a3_a0; 79 uint32 udf_2_a7_a4; 80 uint32 udf_2_a8; 81 uint32 PAD[1]; 82 uint32 udf_0_b3_b0; 83 uint32 udf_0_b7_b4; 84 uint32 udf_0_b8; 85 uint32 PAD[1]; 86 uint32 udf_1_b3_b0; 87 uint32 udf_1_b7_b4; 88 uint32 udf_1_b8; 89 uint32 PAD[1]; 90 uint32 udf_2_b3_b0; 91 uint32 udf_2_b7_b4; 92 uint32 udf_2_b8; 93 uint32 PAD[1]; 94 uint32 udf_0_c3_c0; 95 uint32 udf_0_c7_c4; 96 uint32 udf_0_c8; 97 uint32 PAD[1]; 98 uint32 udf_1_c3_c0; 99 uint32 udf_1_c7_c4; 100 uint32 udf_1_c8; 101 uint32 PAD[1]; 102 uint32 udf_2_c3_c0; 103 uint32 udf_2_c7_c4; 104 uint32 udf_2_c8; 105 uint32 PAD[1]; 106 uint32 udf_0_d3_d0; 107 uint32 udf_0_d7_d4; 108 uint32 udf_0_d11_d8; 109} gmac_commonregs_t; 110 111/* stag0 offset0x0 */ 112#define STAG0_TPID_SHIFT 0 113#define STAG0_TPID_MASK 0xffff 114 115/* stag1 offset0x4 */ 116#define STAG1_TPID_SHIFT 0 117#define STAG1_TPID_MASK 0xffff 118 119/* stag2 offset0x8 */ 120#define STAG2_TPID_SHIFT 0 121#define STAG2_TPID_MASK 0xffff 122 123/* stag3 offset0xc */ 124#define STAG3_TPID_SHIFT 0 125#define STAG3_TPID_MASK 0xffff 126 127/* parsercontrol offset0x20 */ 128#define PARSERCONTROL_MAX_PARSER_LEN_TH_SHIFT 0 129#define PARSERCONTROL_MAX_PARSER_LEN_TH_MASK 0x3fff 130 131/* mib_max_len offset0x24 */ 132#define MIB_MAX_LEN_MIB_MAX_LEN_SHIFT 0 133#define MIB_MAX_LEN_MIB_MAX_LEN_MASK 0x3fff 134 135/* phyaccess offset0x100 */ 136#define PHYACCESS_TRIGGER_SHIFT 30 137#define PHYACCESS_TRIGGER_MASK 0x40000000 138#define PHYACCESS_WR_CMD_SHIFT 29 139#define PHYACCESS_WR_CMD_MASK 0x20000000 140#define PHYACCESS_CPU_REG_ADDR_SHIFT 24 141#define PHYACCESS_CPU_REG_ADDR_MASK 0x1f000000 142#define PHYACCESS_CPU_PHY_ADDR_SHIFT 16 143#define PHYACCESS_CPU_PHY_ADDR_MASK 0x1f0000 144#define PHYACCESS_ACC_DATA_SHIFT 0 145#define PHYACCESS_ACC_DATA_MASK 0xffff 146 147/* phycontrol offset0x104 */ 148#define PHYCONTROL_SD_ACCESS_EN_SHIFT 25 149#define PHYCONTROL_SD_ACCESS_EN_MASK 0x2000000 150#define PHYCONTROL_NWAY_AUTO_POLLING_EN_SHIFT 24 151#define PHYCONTROL_NWAY_AUTO_POLLING_EN_MASK 0x1000000 152#define PHYCONTROL_MDC_TRANSITION_EN_SHIFT 23 153#define PHYCONTROL_MDC_TRANSITION_EN_MASK 0x800000 154#define PHYCONTROL_MDC_CYCLE_TH_SHIFT 16 155#define PHYCONTROL_MDC_CYCLE_TH_MASK 0x7f0000 156#define PHYCONTROL_EXT_PHY_ADDR_SHIFT 0 157#define PHYCONTROL_EXT_PHY_ADDR_MASK 0x1f 158 159/* gmac0_rgmii_cntl offset0x110 */ 160#define GMAC0_RGMII_CNTL_TIMING_SEL_SHIFT 0 161#define GMAC0_RGMII_CNTL_TIMING_SEL_MASK 0x1 162#define GMAC0_RGMII_CNTL_RGMII_DLL_RXC_BYPASS_SHIFT 1 163#define GMAC0_RGMII_CNTL_RGMII_DLL_RXC_BYPASS_MASK 0x2 164#define GMAC0_RGMII_CNTL_BYPASS_2NS_DEL_SHIFT 2 165#define GMAC0_RGMII_CNTL_BYPASS_2NS_DEL_MASK 0x4 166#define GMAC0_RGMII_CNTL_DEL_STRB_SHIFT 3 167#define GMAC0_RGMII_CNTL_DEL_STRB_MASK 0x8 168#define GMAC0_RGMII_CNTL_DEL_VALUE_SHIFT 4 169#define GMAC0_RGMII_CNTL_DEL_VALUE_MASK 0x70 170#define GMAC0_RGMII_CNTL_DEL_ADDR_SHIFT 7 171#define GMAC0_RGMII_CNTL_DEL_ADDR_MASK 0x780 172 173/* cfp_access offset0x200 */ 174#define CFP_ACCESS_OP_START_DONE_SHIFT 0 175#define CFP_ACCESS_OP_START_DONE_MASK 0x1 176#define CFP_ACCESS_OP_SEL_SHIFT 1 177#define CFP_ACCESS_OP_SEL_MASK 0xe 178#define CFP_ACCESS_CFP_RAM_CLEAR_SHIFT 4 179#define CFP_ACCESS_CFP_RAM_CLEAR_MASK 0x10 180#define CFP_ACCESS_RESERVED1_SHIFT 5 181#define CFP_ACCESS_RESERVED1_MASK 0x3e0 182#define CFP_ACCESS_RAM_SEL_SHIFT 10 183#define CFP_ACCESS_RAM_SEL_MASK 0x7c00 184#define CFP_ACCESS_TCAM_RESET_SHIFT 15 185#define CFP_ACCESS_TCAM_RESET_MASK 0x8000 186#define CFP_ACCESS_XCESS_ADDR_SHIFT 16 187#define CFP_ACCESS_XCESS_ADDR_MASK 0x1ff0000 188#define CFP_ACCESS_RESERVED0_SHIFT 25 189#define CFP_ACCESS_RESERVED0_MASK 0xe000000 190#define CFP_ACCESS_RD_STATUS_SHIFT 28 191#define CFP_ACCESS_RD_STATUS_MASK 0xf0000000 192 193/* cfp_tcam_data0 offset0x210 */ 194#define CFP_TCAM_DATA0_DATA_SHIFT 0 195#define CFP_TCAM_DATA0_DATA_MASK 0xffffffff 196 197/* cfp_tcam_data1 offset0x214 */ 198#define CFP_TCAM_DATA1_DATA_SHIFT 0 199#define CFP_TCAM_DATA1_DATA_MASK 0xffffffff 200 201/* cfp_tcam_data2 offset0x218 */ 202#define CFP_TCAM_DATA2_DATA_SHIFT 0 203#define CFP_TCAM_DATA2_DATA_MASK 0xffffffff 204 205/* cfp_tcam_data3 offset0x21c */ 206#define CFP_TCAM_DATA3_DATA_SHIFT 0 207#define CFP_TCAM_DATA3_DATA_MASK 0xffffffff 208 209/* cfp_tcam_data4 offset0x220 */ 210#define CFP_TCAM_DATA4_DATA_SHIFT 0 211#define CFP_TCAM_DATA4_DATA_MASK 0xffffffff 212 213/* cfp_tcam_data5 offset0x224 */ 214#define CFP_TCAM_DATA5_DATA_SHIFT 0 215#define CFP_TCAM_DATA5_DATA_MASK 0xffffffff 216 217/* cfp_tcam_data6 offset0x228 */ 218#define CFP_TCAM_DATA6_DATA_SHIFT 0 219#define CFP_TCAM_DATA6_DATA_MASK 0xffffffff 220 221/* cfp_tcam_data7 offset0x22c */ 222#define CFP_TCAM_DATA7_DATA_SHIFT 0 223#define CFP_TCAM_DATA7_DATA_MASK 0xffffffff 224 225/* cfp_tcam_mask0 offset0x230 */ 226#define CFP_TCAM_MASK0_DATA_SHIFT 0 227#define CFP_TCAM_MASK0_DATA_MASK 0xffffffff 228 229/* cfp_tcam_mask1 offset0x234 */ 230#define CFP_TCAM_MASK1_DATA_SHIFT 0 231#define CFP_TCAM_MASK1_DATA_MASK 0xffffffff 232 233/* cfp_tcam_mask2 offset0x238 */ 234#define CFP_TCAM_MASK2_DATA_SHIFT 0 235#define CFP_TCAM_MASK2_DATA_MASK 0xffffffff 236 237/* cfp_tcam_mask3 offset0x23c */ 238#define CFP_TCAM_MASK3_DATA_SHIFT 0 239#define CFP_TCAM_MASK3_DATA_MASK 0xffffffff 240 241/* cfp_tcam_mask4 offset0x240 */ 242#define CFP_TCAM_MASK4_DATA_SHIFT 0 243#define CFP_TCAM_MASK4_DATA_MASK 0xffffffff 244 245/* cfp_tcam_mask5 offset0x244 */ 246#define CFP_TCAM_MASK5_DATA_SHIFT 0 247#define CFP_TCAM_MASK5_DATA_MASK 0xffffffff 248 249/* cfp_tcam_mask6 offset0x248 */ 250#define CFP_TCAM_MASK6_DATA_SHIFT 0 251#define CFP_TCAM_MASK6_DATA_MASK 0xffffffff 252 253/* cfp_tcam_mask7 offset0x24c */ 254#define CFP_TCAM_MASK7_DATA_SHIFT 0 255#define CFP_TCAM_MASK7_DATA_MASK 0xffffffff 256 257/* cfp_action_data offset0x250 */ 258#define CFP_ACTION_DATA_CHAINID_SHIFT 0 259#define CFP_ACTION_DATA_CHAINID_MASK 0xff 260#define CFP_ACTION_DATA_CHANNELID_SHIFT 8 261#define CFP_ACTION_DATA_CHANNELID_MASK 0xf00 262#define CFP_ACTION_DATA_DROP_SHIFT 12 263#define CFP_ACTION_DATA_DROP_MASK 0x1000 264#define CFP_ACTION_DATA_RESERVED_SHIFT 13 265#define CFP_ACTION_DATA_RESERVED_MASK 0xffffe000 266 267/* tcam_bist_cntl offset0x2a0 */ 268#define TCAM_BIST_CNTL_TCAM_BIST_EN_SHIFT 0 269#define TCAM_BIST_CNTL_TCAM_BIST_EN_MASK 0x1 270#define TCAM_BIST_CNTL_TCAM_BIST_TCAM_SEL_SHIFT 1 271#define TCAM_BIST_CNTL_TCAM_BIST_TCAM_SEL_MASK 0x6 272#define TCAM_BIST_CNTL_RESERVED1_SHIFT 3 273#define TCAM_BIST_CNTL_RESERVED1_MASK 0x8 274#define TCAM_BIST_CNTL_TCAM_BIST_STATUS_SEL_SHIFT 4 275#define TCAM_BIST_CNTL_TCAM_BIST_STATUS_SEL_MASK 0xf0 276#define TCAM_BIST_CNTL_TCAM_BIST_SKIP_ERR_CNT_SHIFT 8 277#define TCAM_BIST_CNTL_TCAM_BIST_SKIP_ERR_CNT_MASK 0xff00 278#define TCAM_BIST_CNTL_TCAM_TEST_COMPARE_SHIFT 16 279#define TCAM_BIST_CNTL_TCAM_TEST_COMPARE_MASK 0x10000 280#define TCAM_BIST_CNTL_RESERVED_SHIFT 17 281#define TCAM_BIST_CNTL_RESERVED_MASK 0x7ffe0000 282#define TCAM_BIST_CNTL_TCAM_BIST_DONE_SHIFT 31 283#define TCAM_BIST_CNTL_TCAM_BIST_DONE_MASK 0x80000000 284 285/* tcam_bist_status offset0x2a4 */ 286#define TCAM_BIST_STATUS_TCAM_BIST_STATUS_SHIFT 0 287#define TCAM_BIST_STATUS_TCAM_BIST_STATUS_MASK 0xffff 288#define TCAM_BIST_STATUS_RESERVED_SHIFT 16 289#define TCAM_BIST_STATUS_RESERVED_MASK 0xffff0000 290 291/* tcam_cmp_status offset0x2a8 */ 292#define TCAM_CMP_STATUS_TCAM_HIT_ADDR_SHIFT 0 293#define TCAM_CMP_STATUS_TCAM_HIT_ADDR_MASK 0x1ff 294#define TCAM_CMP_STATUS_RESERVED2_SHIFT 9 295#define TCAM_CMP_STATUS_RESERVED2_MASK 0x7e00 296#define TCAM_CMP_STATUS_TCAM_HIT_SHIFT 15 297#define TCAM_CMP_STATUS_TCAM_HIT_MASK 0x8000 298#define TCAM_CMP_STATUS_RESERVED1_SHIFT 16 299#define TCAM_CMP_STATUS_RESERVED1_MASK 0xffff0000 300 301/* tcam_disable offset0x2ac */ 302#define TCAM_DISABLE_TCAM_DISABLE_SHIFT 0 303#define TCAM_DISABLE_TCAM_DISABLE_MASK 0xf 304#define TCAM_DISABLE_RESERVED_SHIFT 4 305#define TCAM_DISABLE_RESERVED_MASK 0xfffffff0 306 307/* tcam_test_cntl offset0x2f0 */ 308#define TCAM_TEST_CNTL_TCAM_TEST_CNTL_SHIFT 0 309#define TCAM_TEST_CNTL_TCAM_TEST_CNTL_MASK 0x7ff 310#define TCAM_TEST_CNTL_RESERVED_SHIFT 11 311#define TCAM_TEST_CNTL_RESERVED_MASK 0xfffff800 312 313/* udf_0_a3_a0 offset0x300 */ 314#define UDF_0_A3_A0_CFG_UDF_0_A0_SHIFT 0 315#define UDF_0_A3_A0_CFG_UDF_0_A0_MASK 0xff 316#define UDF_0_A3_A0_CFG_UDF_0_A1_SHIFT 8 317#define UDF_0_A3_A0_CFG_UDF_0_A1_MASK 0xff00 318#define UDF_0_A3_A0_CFG_UDF_0_A2_SHIFT 16 319#define UDF_0_A3_A0_CFG_UDF_0_A2_MASK 0xff0000 320#define UDF_0_A3_A0_CFG_UDF_0_A3_SHIFT 24 321#define UDF_0_A3_A0_CFG_UDF_0_A3_MASK 0xff000000 322 323/* udf_0_a7_a4 offset0x304 */ 324#define UDF_0_A7_A4_CFG_UDF_0_A4_SHIFT 0 325#define UDF_0_A7_A4_CFG_UDF_0_A4_MASK 0xff 326#define UDF_0_A7_A4_CFG_UDF_0_A5_SHIFT 8 327#define UDF_0_A7_A4_CFG_UDF_0_A5_MASK 0xff00 328#define UDF_0_A7_A4_CFG_UDF_0_A6_SHIFT 16 329#define UDF_0_A7_A4_CFG_UDF_0_A6_MASK 0xff0000 330#define UDF_0_A7_A4_CFG_UDF_0_A7_SHIFT 24 331#define UDF_0_A7_A4_CFG_UDF_0_A7_MASK 0xff000000 332 333/* udf_0_a8 offset0x308 */ 334#define UDF_0_A8_CFG_UDF_0_A8_SHIFT 0 335#define UDF_0_A8_CFG_UDF_0_A8_MASK 0xff 336 337/* udf_1_a3_a0 offset0x310 */ 338#define UDF_1_A3_A0_CFG_UDF_1_A0_SHIFT 0 339#define UDF_1_A3_A0_CFG_UDF_1_A0_MASK 0xff 340#define UDF_1_A3_A0_CFG_UDF_1_A1_SHIFT 8 341#define UDF_1_A3_A0_CFG_UDF_1_A1_MASK 0xff00 342#define UDF_1_A3_A0_CFG_UDF_1_A2_SHIFT 16 343#define UDF_1_A3_A0_CFG_UDF_1_A2_MASK 0xff0000 344#define UDF_1_A3_A0_CFG_UDF_1_A3_SHIFT 24 345#define UDF_1_A3_A0_CFG_UDF_1_A3_MASK 0xff000000 346 347/* udf_1_a7_a4 offset0x314 */ 348#define UDF_1_A7_A4_CFG_UDF_1_A4_SHIFT 0 349#define UDF_1_A7_A4_CFG_UDF_1_A4_MASK 0xff 350#define UDF_1_A7_A4_CFG_UDF_1_A5_SHIFT 8 351#define UDF_1_A7_A4_CFG_UDF_1_A5_MASK 0xff00 352#define UDF_1_A7_A4_CFG_UDF_1_A6_SHIFT 16 353#define UDF_1_A7_A4_CFG_UDF_1_A6_MASK 0xff0000 354#define UDF_1_A7_A4_CFG_UDF_1_A7_SHIFT 24 355#define UDF_1_A7_A4_CFG_UDF_1_A7_MASK 0xff000000 356 357/* udf_1_a8 offset0x318 */ 358#define UDF_1_A8_CFG_UDF_1_A8_SHIFT 0 359#define UDF_1_A8_CFG_UDF_1_A8_MASK 0xff 360 361/* udf_2_a3_a0 offset0x320 */ 362#define UDF_2_A3_A0_CFG_UDF_2_A0_SHIFT 0 363#define UDF_2_A3_A0_CFG_UDF_2_A0_MASK 0xff 364#define UDF_2_A3_A0_CFG_UDF_2_A1_SHIFT 8 365#define UDF_2_A3_A0_CFG_UDF_2_A1_MASK 0xff00 366#define UDF_2_A3_A0_CFG_UDF_2_A2_SHIFT 16 367#define UDF_2_A3_A0_CFG_UDF_2_A2_MASK 0xff0000 368#define UDF_2_A3_A0_CFG_UDF_2_A3_SHIFT 24 369#define UDF_2_A3_A0_CFG_UDF_2_A3_MASK 0xff000000 370 371/* udf_2_a7_a4 offset0x324 */ 372#define UDF_2_A7_A4_CFG_UDF_2_A4_SHIFT 0 373#define UDF_2_A7_A4_CFG_UDF_2_A4_MASK 0xff 374#define UDF_2_A7_A4_CFG_UDF_2_A5_SHIFT 8 375#define UDF_2_A7_A4_CFG_UDF_2_A5_MASK 0xff00 376#define UDF_2_A7_A4_CFG_UDF_2_A6_SHIFT 16 377#define UDF_2_A7_A4_CFG_UDF_2_A6_MASK 0xff0000 378#define UDF_2_A7_A4_CFG_UDF_2_A7_SHIFT 24 379#define UDF_2_A7_A4_CFG_UDF_2_A7_MASK 0xff000000 380 381/* udf_2_a8 offset0x328 */ 382#define UDF_2_A8_CFG_UDF_2_A8_SHIFT 0 383#define UDF_2_A8_CFG_UDF_2_A8_MASK 0xff 384 385/* udf_0_b3_b0 offset0x330 */ 386#define UDF_0_B3_B0_CFG_UDF_0_B0_SHIFT 0 387#define UDF_0_B3_B0_CFG_UDF_0_B0_MASK 0xff 388#define UDF_0_B3_B0_CFG_UDF_0_B1_SHIFT 8 389#define UDF_0_B3_B0_CFG_UDF_0_B1_MASK 0xff00 390#define UDF_0_B3_B0_CFG_UDF_0_B2_SHIFT 16 391#define UDF_0_B3_B0_CFG_UDF_0_B2_MASK 0xff0000 392#define UDF_0_B3_B0_CFG_UDF_0_B3_SHIFT 24 393#define UDF_0_B3_B0_CFG_UDF_0_B3_MASK 0xff000000 394 395/* udf_0_b7_b4 offset0x334 */ 396#define UDF_0_B7_B4_CFG_UDF_0_B4_SHIFT 0 397#define UDF_0_B7_B4_CFG_UDF_0_B4_MASK 0xff 398#define UDF_0_B7_B4_CFG_UDF_0_B5_SHIFT 8 399#define UDF_0_B7_B4_CFG_UDF_0_B5_MASK 0xff00 400#define UDF_0_B7_B4_CFG_UDF_0_B6_SHIFT 16 401#define UDF_0_B7_B4_CFG_UDF_0_B6_MASK 0xff0000 402#define UDF_0_B7_B4_CFG_UDF_0_B7_SHIFT 24 403#define UDF_0_B7_B4_CFG_UDF_0_B7_MASK 0xff000000 404 405/* udf_0_b8 offset0x338 */ 406#define UDF_0_B8_CFG_UDF_0_B8_SHIFT 0 407#define UDF_0_B8_CFG_UDF_0_B8_MASK 0xff 408 409/* udf_1_b3_b0 offset0x340 */ 410#define UDF_1_B3_B0_CFG_UDF_1_B0_SHIFT 0 411#define UDF_1_B3_B0_CFG_UDF_1_B0_MASK 0xff 412#define UDF_1_B3_B0_CFG_UDF_1_B1_SHIFT 8 413#define UDF_1_B3_B0_CFG_UDF_1_B1_MASK 0xff00 414#define UDF_1_B3_B0_CFG_UDF_1_B2_SHIFT 16 415#define UDF_1_B3_B0_CFG_UDF_1_B2_MASK 0xff0000 416#define UDF_1_B3_B0_CFG_UDF_1_B3_SHIFT 24 417#define UDF_1_B3_B0_CFG_UDF_1_B3_MASK 0xff000000 418 419/* udf_1_b7_b4 offset0x344 */ 420#define UDF_1_B7_B4_CFG_UDF_1_B4_SHIFT 0 421#define UDF_1_B7_B4_CFG_UDF_1_B4_MASK 0xff 422#define UDF_1_B7_B4_CFG_UDF_1_B5_SHIFT 8 423#define UDF_1_B7_B4_CFG_UDF_1_B5_MASK 0xff00 424#define UDF_1_B7_B4_CFG_UDF_1_B6_SHIFT 16 425#define UDF_1_B7_B4_CFG_UDF_1_B6_MASK 0xff0000 426#define UDF_1_B7_B4_CFG_UDF_1_B7_SHIFT 24 427#define UDF_1_B7_B4_CFG_UDF_1_B7_MASK 0xff000000 428 429/* udf_1_b8 offset0x348 */ 430#define UDF_1_B8_CFG_UDF_1_B8_SHIFT 0 431#define UDF_1_B8_CFG_UDF_1_B8_MASK 0xff 432 433/* udf_2_b3_b0 offset0x350 */ 434#define UDF_2_B3_B0_CFG_UDF_2_B0_SHIFT 0 435#define UDF_2_B3_B0_CFG_UDF_2_B0_MASK 0xff 436#define UDF_2_B3_B0_CFG_UDF_2_B1_SHIFT 8 437#define UDF_2_B3_B0_CFG_UDF_2_B1_MASK 0xff00 438#define UDF_2_B3_B0_CFG_UDF_2_B2_SHIFT 16 439#define UDF_2_B3_B0_CFG_UDF_2_B2_MASK 0xff0000 440#define UDF_2_B3_B0_CFG_UDF_2_B3_SHIFT 24 441#define UDF_2_B3_B0_CFG_UDF_2_B3_MASK 0xff000000 442 443/* udf_2_b7_b4 offset0x354 */ 444#define UDF_2_B7_B4_CFG_UDF_2_B4_SHIFT 0 445#define UDF_2_B7_B4_CFG_UDF_2_B4_MASK 0xff 446#define UDF_2_B7_B4_CFG_UDF_2_B5_SHIFT 8 447#define UDF_2_B7_B4_CFG_UDF_2_B5_MASK 0xff00 448#define UDF_2_B7_B4_CFG_UDF_2_B6_SHIFT 16 449#define UDF_2_B7_B4_CFG_UDF_2_B6_MASK 0xff0000 450#define UDF_2_B7_B4_CFG_UDF_2_B7_SHIFT 24 451#define UDF_2_B7_B4_CFG_UDF_2_B7_MASK 0xff000000 452 453/* udf_2_b8 offset0x358 */ 454#define UDF_2_B8_CFG_UDF_2_B8_SHIFT 0 455#define UDF_2_B8_CFG_UDF_2_B8_MASK 0xff 456 457/* udf_0_c3_c0 offset0x360 */ 458#define UDF_0_C3_C0_CFG_UDF_0_C0_SHIFT 0 459#define UDF_0_C3_C0_CFG_UDF_0_C0_MASK 0xff 460#define UDF_0_C3_C0_CFG_UDF_0_C1_SHIFT 8 461#define UDF_0_C3_C0_CFG_UDF_0_C1_MASK 0xff00 462#define UDF_0_C3_C0_CFG_UDF_0_C2_SHIFT 16 463#define UDF_0_C3_C0_CFG_UDF_0_C2_MASK 0xff0000 464#define UDF_0_C3_C0_CFG_UDF_0_C3_SHIFT 24 465#define UDF_0_C3_C0_CFG_UDF_0_C3_MASK 0xff000000 466 467/* udf_0_c7_c4 offset0x364 */ 468#define UDF_0_C7_C4_CFG_UDF_0_C4_SHIFT 0 469#define UDF_0_C7_C4_CFG_UDF_0_C4_MASK 0xff 470#define UDF_0_C7_C4_CFG_UDF_0_C5_SHIFT 8 471#define UDF_0_C7_C4_CFG_UDF_0_C5_MASK 0xff00 472#define UDF_0_C7_C4_CFG_UDF_0_C6_SHIFT 16 473#define UDF_0_C7_C4_CFG_UDF_0_C6_MASK 0xff0000 474#define UDF_0_C7_C4_CFG_UDF_0_C7_SHIFT 24 475#define UDF_0_C7_C4_CFG_UDF_0_C7_MASK 0xff000000 476 477/* udf_0_c8 offset0x368 */ 478#define UDF_0_C8_CFG_UDF_0_C8_SHIFT 0 479#define UDF_0_C8_CFG_UDF_0_C8_MASK 0xff 480 481/* udf_1_c3_c0 offset0x370 */ 482#define UDF_1_C3_C0_CFG_UDF_1_C0_SHIFT 0 483#define UDF_1_C3_C0_CFG_UDF_1_C0_MASK 0xff 484#define UDF_1_C3_C0_CFG_UDF_1_C1_SHIFT 8 485#define UDF_1_C3_C0_CFG_UDF_1_C1_MASK 0xff00 486#define UDF_1_C3_C0_CFG_UDF_1_C2_SHIFT 16 487#define UDF_1_C3_C0_CFG_UDF_1_C2_MASK 0xff0000 488#define UDF_1_C3_C0_CFG_UDF_1_C3_SHIFT 24 489#define UDF_1_C3_C0_CFG_UDF_1_C3_MASK 0xff000000 490 491/* udf_1_c7_c4 offset0x374 */ 492#define UDF_1_C7_C4_CFG_UDF_1_C4_SHIFT 0 493#define UDF_1_C7_C4_CFG_UDF_1_C4_MASK 0xff 494#define UDF_1_C7_C4_CFG_UDF_1_C5_SHIFT 8 495#define UDF_1_C7_C4_CFG_UDF_1_C5_MASK 0xff00 496#define UDF_1_C7_C4_CFG_UDF_1_C6_SHIFT 16 497#define UDF_1_C7_C4_CFG_UDF_1_C6_MASK 0xff0000 498#define UDF_1_C7_C4_CFG_UDF_1_C7_SHIFT 24 499#define UDF_1_C7_C4_CFG_UDF_1_C7_MASK 0xff000000 500 501/* udf_1_c8 offset0x378 */ 502#define UDF_1_C8_CFG_UDF_1_C8_SHIFT 0 503#define UDF_1_C8_CFG_UDF_1_C8_MASK 0xff 504 505/* udf_2_c3_c0 offset0x380 */ 506#define UDF_2_C3_C0_CFG_UDF_2_C0_SHIFT 0 507#define UDF_2_C3_C0_CFG_UDF_2_C0_MASK 0xff 508#define UDF_2_C3_C0_CFG_UDF_2_C1_SHIFT 8 509#define UDF_2_C3_C0_CFG_UDF_2_C1_MASK 0xff00 510#define UDF_2_C3_C0_CFG_UDF_2_C2_SHIFT 16 511#define UDF_2_C3_C0_CFG_UDF_2_C2_MASK 0xff0000 512#define UDF_2_C3_C0_CFG_UDF_2_C3_SHIFT 24 513#define UDF_2_C3_C0_CFG_UDF_2_C3_MASK 0xff000000 514 515/* udf_2_c7_c4 offset0x384 */ 516#define UDF_2_C7_C4_CFG_UDF_2_C4_SHIFT 0 517#define UDF_2_C7_C4_CFG_UDF_2_C4_MASK 0xff 518#define UDF_2_C7_C4_CFG_UDF_2_C5_SHIFT 8 519#define UDF_2_C7_C4_CFG_UDF_2_C5_MASK 0xff00 520#define UDF_2_C7_C4_CFG_UDF_2_C6_SHIFT 16 521#define UDF_2_C7_C4_CFG_UDF_2_C6_MASK 0xff0000 522#define UDF_2_C7_C4_CFG_UDF_2_C7_SHIFT 24 523#define UDF_2_C7_C4_CFG_UDF_2_C7_MASK 0xff000000 524 525/* udf_2_c8 offset0x388 */ 526#define UDF_2_C8_CFG_UDF_2_C8_SHIFT 0 527#define UDF_2_C8_CFG_UDF_2_C8_MASK 0xff 528 529/* udf_0_d3_d0 offset0x390 */ 530#define UDF_0_D3_D0_CFG_UDF_0_D0_SHIFT 0 531#define UDF_0_D3_D0_CFG_UDF_0_D0_MASK 0xff 532#define UDF_0_D3_D0_CFG_UDF_0_D1_SHIFT 8 533#define UDF_0_D3_D0_CFG_UDF_0_D1_MASK 0xff00 534#define UDF_0_D3_D0_CFG_UDF_0_D2_SHIFT 16 535#define UDF_0_D3_D0_CFG_UDF_0_D2_MASK 0xff0000 536#define UDF_0_D3_D0_CFG_UDF_0_D3_SHIFT 24 537#define UDF_0_D3_D0_CFG_UDF_0_D3_MASK 0xff000000 538 539/* udf_0_d7_d4 offset0x394 */ 540#define UDF_0_D7_D4_CFG_UDF_0_D4_SHIFT 0 541#define UDF_0_D7_D4_CFG_UDF_0_D4_MASK 0xff 542#define UDF_0_D7_D4_CFG_UDF_0_D5_SHIFT 8 543#define UDF_0_D7_D4_CFG_UDF_0_D5_MASK 0xff00 544#define UDF_0_D7_D4_CFG_UDF_0_D6_SHIFT 16 545#define UDF_0_D7_D4_CFG_UDF_0_D6_MASK 0xff0000 546#define UDF_0_D7_D4_CFG_UDF_0_D7_SHIFT 24 547#define UDF_0_D7_D4_CFG_UDF_0_D7_MASK 0xff000000 548 549/* udf_0_d11_d8 offset0x398 */ 550#define UDF_0_D11_D8_CFG_UDF_0_D8_SHIFT 0 551#define UDF_0_D11_D8_CFG_UDF_0_D8_MASK 0xff 552#define UDF_0_D11_D8_CFG_UDF_0_D9_SHIFT 8 553#define UDF_0_D11_D8_CFG_UDF_0_D9_MASK 0xff00 554#define UDF_0_D11_D8_CFG_UDF_0_D10_SHIFT 16 555#define UDF_0_D11_D8_CFG_UDF_0_D10_MASK 0xff0000 556#define UDF_0_D11_D8_CFG_UDF_0_D11_SHIFT 24 557#define UDF_0_D11_D8_CFG_UDF_0_D11_MASK 0xff000000 558 559#endif /* _gmac_common_core_h_ */ 560