1/*
2 * Driver for Digigram miXart soundcards
3 *
4 * definitions and makros for basic card access
5 *
6 * Copyright (c) 2003 by Digigram <alsa@digigram.com>
7 *
8 *   This program is free software; you can redistribute it and/or modify
9 *   it under the terms of the GNU General Public License as published by
10 *   the Free Software Foundation; either version 2 of the License, or
11 *   (at your option) any later version.
12 *
13 *   This program is distributed in the hope that it will be useful,
14 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 *   GNU General Public License for more details.
17 *
18 *   You should have received a copy of the GNU General Public License
19 *   along with this program; if not, write to the Free Software
20 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21 */
22
23#ifndef __SOUND_MIXART_HWDEP_H
24#define __SOUND_MIXART_HWDEP_H
25
26#include <sound/hwdep.h>
27
28#define readl_be(x) be32_to_cpu(__raw_readl(x))
29#define writel_be(data,addr) __raw_writel(cpu_to_be32(data),addr)
30
31#define readl_le(x) le32_to_cpu(__raw_readl(x))
32#define writel_le(data,addr) __raw_writel(cpu_to_le32(data),addr)
33
34#define MIXART_MEM(mgr,x)	((mgr)->mem[0].virt + (x))
35#define MIXART_REG(mgr,x)	((mgr)->mem[1].virt + (x))
36
37
38/* Daughter board Type */
39#define DAUGHTER_TYPE_MASK     0x0F
40#define DAUGHTER_VER_MASK      0xF0
41#define DAUGHTER_TYPEVER_MASK  (DAUGHTER_TYPE_MASK|DAUGHTER_VER_MASK)
42
43#define MIXART_DAUGHTER_TYPE_NONE     0x00
44#define MIXART_DAUGHTER_TYPE_COBRANET 0x08
45#define MIXART_DAUGHTER_TYPE_AES      0x0E
46
47
48
49#define MIXART_BA0_SIZE 	(16 * 1024 * 1024) /* 16M */
50#define MIXART_BA1_SIZE 	(4  * 1024)        /* 4k */
51
52/*
53 * -----------BAR 0 --------------------------------------------------------------------------------------------------------
54 */
55#define  MIXART_PSEUDOREG                          0x2000                    /* base address for pseudoregister */
56
57#define  MIXART_PSEUDOREG_BOARDNUMBER              MIXART_PSEUDOREG+0        /* board number */
58
59/* perfmeter (available when elf loaded)*/
60#define  MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET  MIXART_PSEUDOREG+0x70     /* streaming load */
61#define  MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET  MIXART_PSEUDOREG+0x78     /* system load (reference)*/
62#define  MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET  MIXART_PSEUDOREG+0x7C     /* mailbox load */
63#define  MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET  MIXART_PSEUDOREG+0x74     /* interrupt handling  load */
64
65/* motherboard xilinx loader info */
66#define  MIXART_PSEUDOREG_MXLX_BASE_ADDR_OFFSET    MIXART_PSEUDOREG+0x9C     /* 0x00600000 */
67#define  MIXART_PSEUDOREG_MXLX_SIZE_OFFSET         MIXART_PSEUDOREG+0xA0     /* xilinx size in bytes */
68#define  MIXART_PSEUDOREG_MXLX_STATUS_OFFSET       MIXART_PSEUDOREG+0xA4     /* status = EMBEBBED_STAT_XXX */
69
70/* elf loader info */
71#define  MIXART_PSEUDOREG_ELF_STATUS_OFFSET        MIXART_PSEUDOREG+0xB0     /* status = EMBEBBED_STAT_XXX */
72
73/*
74*  after the elf code is loaded, and the flowtable info was passed to it,
75*  the driver polls on this address, until it shows 1 (presence) or 2 (absence)
76*  once it is non-zero, the daughter board type may be read
77*/
78#define  MIXART_PSEUDOREG_DBRD_PRESENCE_OFFSET     MIXART_PSEUDOREG+0x990
79
80/* Global info structure */
81#define  MIXART_PSEUDOREG_DBRD_TYPE_OFFSET         MIXART_PSEUDOREG+0x994    /* Type and version of daughterboard  */
82
83
84/* daughterboard xilinx loader info */
85#define  MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET    MIXART_PSEUDOREG+0x998    /* get the address here where to write the file */
86#define  MIXART_PSEUDOREG_DXLX_SIZE_OFFSET         MIXART_PSEUDOREG+0x99C    /* xilinx size in bytes */
87#define  MIXART_PSEUDOREG_DXLX_STATUS_OFFSET       MIXART_PSEUDOREG+0x9A0    /* status = EMBEBBED_STAT_XXX */
88
89/*  */
90#define  MIXART_FLOWTABLE_PTR                      0x3000                    /* pointer to flow table */
91
92/* mailbox addresses  */
93
94/* message DRV -> EMB */
95#define MSG_INBOUND_POST_HEAD       0x010008	/* DRV posts MF + increment4 */
96#define	MSG_INBOUND_POST_TAIL       0x01000C	/* EMB gets MF + increment4 */
97/* message EMB -> DRV */
98#define	MSG_OUTBOUND_POST_TAIL      0x01001C	/* DRV gets MF + increment4 */
99#define	MSG_OUTBOUND_POST_HEAD      0x010018	/* EMB posts MF + increment4 */
100/* Get Free Frames */
101#define MSG_INBOUND_FREE_TAIL       0x010004	/* DRV gets MFA + increment4 */
102#define MSG_OUTBOUND_FREE_TAIL      0x010014	/* EMB gets MFA + increment4 */
103/* Put Free Frames */
104#define MSG_OUTBOUND_FREE_HEAD      0x010010	/* DRV puts MFA + increment4 */
105#define MSG_INBOUND_FREE_HEAD       0x010000    /* EMB puts MFA + increment4 */
106
107/* firmware addresses of the message fifos */
108#define MSG_BOUND_STACK_SIZE        0x004000    /* size of each following stack */
109/* posted messages */
110#define MSG_OUTBOUND_POST_STACK     0x108000    /* stack of messages to the DRV */
111#define MSG_INBOUND_POST_STACK      0x104000    /* stack of messages to the EMB */
112/* available empty messages */
113#define MSG_OUTBOUND_FREE_STACK     0x10C000    /* stack of free enveloped for EMB */
114#define MSG_INBOUND_FREE_STACK      0x100000    /* stack of free enveloped for DRV */
115
116
117/* defines for mailbox message frames */
118#define MSG_FRAME_OFFSET            0x64
119#define MSG_FRAME_SIZE              0x6400
120#define MSG_FRAME_NUMBER            32
121#define MSG_FROM_AGENT_ITMF_OFFSET  (MSG_FRAME_OFFSET + (MSG_FRAME_SIZE * MSG_FRAME_NUMBER))
122#define MSG_TO_AGENT_ITMF_OFFSET    (MSG_FROM_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
123#define MSG_HOST_RSC_PROTECTION     (MSG_TO_AGENT_ITMF_OFFSET + MSG_FRAME_SIZE)
124#define MSG_AGENT_RSC_PROTECTION    (MSG_HOST_RSC_PROTECTION + 4)
125
126
127/*
128 * -----------BAR 1 --------------------------------------------------------------------------------------------------------
129 */
130
131/* interrupt addresses and constants */
132#define MIXART_PCI_OMIMR_OFFSET                 0x34    /* outbound message interrupt mask register */
133#define MIXART_PCI_OMISR_OFFSET                 0x30    /* outbound message interrupt status register */
134#define MIXART_PCI_ODBR_OFFSET                  0x60    /* outbound doorbell register */
135
136#define MIXART_BA1_BRUTAL_RESET_OFFSET          0x68    /* write 1 in LSBit to reset board */
137
138#define MIXART_HOST_ALL_INTERRUPT_MASKED        0x02B   /* 0000 0010 1011 */
139#define MIXART_ALLOW_OUTBOUND_DOORBELL          0x023   /* 0000 0010 0011 */
140#define MIXART_OIDI                             0x008   /* 0000 0000 1000 */
141
142
143int snd_mixart_setup_firmware(struct mixart_mgr *mgr);
144
145#endif /* __SOUND_MIXART_HWDEP_H */
146