1/* 2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards. 3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net> 4 * Takashi Iwai <tiwai@suse.de> 5 * 6 * Most of the hardware init stuffs are based on maestro3 driver for 7 * OSS/Free by Zach Brown. Many thanks to Zach! 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * 24 * ChangeLog: 25 * Aug. 27, 2001 26 * - Fixed deadlock on capture 27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org> 28 * 29 */ 30 31#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2" 32#define DRIVER_NAME "Maestro3" 33 34#include <sound/driver.h> 35#include <asm/io.h> 36#include <linux/delay.h> 37#include <linux/interrupt.h> 38#include <linux/init.h> 39#include <linux/pci.h> 40#include <linux/dma-mapping.h> 41#include <linux/slab.h> 42#include <linux/vmalloc.h> 43#include <linux/moduleparam.h> 44#include <linux/firmware.h> 45#include <sound/core.h> 46#include <sound/info.h> 47#include <sound/control.h> 48#include <sound/pcm.h> 49#include <sound/mpu401.h> 50#include <sound/ac97_codec.h> 51#include <sound/initval.h> 52#include <asm/byteorder.h> 53 54MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>"); 55MODULE_DESCRIPTION("ESS Maestro3 PCI"); 56MODULE_LICENSE("GPL"); 57MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI}," 58 "{ESS,ES1988}," 59 "{ESS,Allegro PCI}," 60 "{ESS,Allegro-1 PCI}," 61 "{ESS,Canyon3D-2/LE PCI}}"); 62#ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL 63MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw"); 64MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw"); 65#endif 66 67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 69static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */ 70static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; 71static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; 72 73module_param_array(index, int, NULL, 0444); 74MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 75module_param_array(id, charp, NULL, 0444); 76MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 77module_param_array(enable, bool, NULL, 0444); 78MODULE_PARM_DESC(enable, "Enable this soundcard."); 79module_param_array(external_amp, bool, NULL, 0444); 80MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard."); 81module_param_array(amp_gpio, int, NULL, 0444); 82MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)"); 83 84#define MAX_PLAYBACKS 2 85#define MAX_CAPTURES 1 86#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES) 87 88 89/* 90 * maestro3 registers 91 */ 92 93/* Allegro PCI configuration registers */ 94#define PCI_LEGACY_AUDIO_CTRL 0x40 95#define SOUND_BLASTER_ENABLE 0x00000001 96#define FM_SYNTHESIS_ENABLE 0x00000002 97#define GAME_PORT_ENABLE 0x00000004 98#define MPU401_IO_ENABLE 0x00000008 99#define MPU401_IRQ_ENABLE 0x00000010 100#define ALIAS_10BIT_IO 0x00000020 101#define SB_DMA_MASK 0x000000C0 102#define SB_DMA_0 0x00000040 103#define SB_DMA_1 0x00000040 104#define SB_DMA_R 0x00000080 105#define SB_DMA_3 0x000000C0 106#define SB_IRQ_MASK 0x00000700 107#define SB_IRQ_5 0x00000000 108#define SB_IRQ_7 0x00000100 109#define SB_IRQ_9 0x00000200 110#define SB_IRQ_10 0x00000300 111#define MIDI_IRQ_MASK 0x00003800 112#define SERIAL_IRQ_ENABLE 0x00004000 113#define DISABLE_LEGACY 0x00008000 114 115#define PCI_ALLEGRO_CONFIG 0x50 116#define SB_ADDR_240 0x00000004 117#define MPU_ADDR_MASK 0x00000018 118#define MPU_ADDR_330 0x00000000 119#define MPU_ADDR_300 0x00000008 120#define MPU_ADDR_320 0x00000010 121#define MPU_ADDR_340 0x00000018 122#define USE_PCI_TIMING 0x00000040 123#define POSTED_WRITE_ENABLE 0x00000080 124#define DMA_POLICY_MASK 0x00000700 125#define DMA_DDMA 0x00000000 126#define DMA_TDMA 0x00000100 127#define DMA_PCPCI 0x00000200 128#define DMA_WBDMA16 0x00000400 129#define DMA_WBDMA4 0x00000500 130#define DMA_WBDMA2 0x00000600 131#define DMA_WBDMA1 0x00000700 132#define DMA_SAFE_GUARD 0x00000800 133#define HI_PERF_GP_ENABLE 0x00001000 134#define PIC_SNOOP_MODE_0 0x00002000 135#define PIC_SNOOP_MODE_1 0x00004000 136#define SOUNDBLASTER_IRQ_MASK 0x00008000 137#define RING_IN_ENABLE 0x00010000 138#define SPDIF_TEST_MODE 0x00020000 139#define CLK_MULT_MODE_SELECT_2 0x00040000 140#define EEPROM_WRITE_ENABLE 0x00080000 141#define CODEC_DIR_IN 0x00100000 142#define HV_BUTTON_FROM_GD 0x00200000 143#define REDUCED_DEBOUNCE 0x00400000 144#define HV_CTRL_ENABLE 0x00800000 145#define SPDIF_ENABLE 0x01000000 146#define CLK_DIV_SELECT 0x06000000 147#define CLK_DIV_BY_48 0x00000000 148#define CLK_DIV_BY_49 0x02000000 149#define CLK_DIV_BY_50 0x04000000 150#define CLK_DIV_RESERVED 0x06000000 151#define PM_CTRL_ENABLE 0x08000000 152#define CLK_MULT_MODE_SELECT 0x30000000 153#define CLK_MULT_MODE_SHIFT 28 154#define CLK_MULT_MODE_0 0x00000000 155#define CLK_MULT_MODE_1 0x10000000 156#define CLK_MULT_MODE_2 0x20000000 157#define CLK_MULT_MODE_3 0x30000000 158#define INT_CLK_SELECT 0x40000000 159#define INT_CLK_MULT_RESET 0x80000000 160 161/* M3 */ 162#define INT_CLK_SRC_NOT_PCI 0x00100000 163#define INT_CLK_MULT_ENABLE 0x80000000 164 165#define PCI_ACPI_CONTROL 0x54 166#define PCI_ACPI_D0 0x00000000 167#define PCI_ACPI_D1 0xB4F70000 168#define PCI_ACPI_D2 0xB4F7B4F7 169 170#define PCI_USER_CONFIG 0x58 171#define EXT_PCI_MASTER_ENABLE 0x00000001 172#define SPDIF_OUT_SELECT 0x00000002 173#define TEST_PIN_DIR_CTRL 0x00000004 174#define AC97_CODEC_TEST 0x00000020 175#define TRI_STATE_BUFFER 0x00000080 176#define IN_CLK_12MHZ_SELECT 0x00000100 177#define MULTI_FUNC_DISABLE 0x00000200 178#define EXT_MASTER_PAIR_SEL 0x00000400 179#define PCI_MASTER_SUPPORT 0x00000800 180#define STOP_CLOCK_ENABLE 0x00001000 181#define EAPD_DRIVE_ENABLE 0x00002000 182#define REQ_TRI_STATE_ENABLE 0x00004000 183#define REQ_LOW_ENABLE 0x00008000 184#define MIDI_1_ENABLE 0x00010000 185#define MIDI_2_ENABLE 0x00020000 186#define SB_AUDIO_SYNC 0x00040000 187#define HV_CTRL_TEST 0x00100000 188#define SOUNDBLASTER_TEST 0x00400000 189 190#define PCI_USER_CONFIG_C 0x5C 191 192#define PCI_DDMA_CTRL 0x60 193#define DDMA_ENABLE 0x00000001 194 195 196/* Allegro registers */ 197#define HOST_INT_CTRL 0x18 198#define SB_INT_ENABLE 0x0001 199#define MPU401_INT_ENABLE 0x0002 200#define ASSP_INT_ENABLE 0x0010 201#define RING_INT_ENABLE 0x0020 202#define HV_INT_ENABLE 0x0040 203#define CLKRUN_GEN_ENABLE 0x0100 204#define HV_CTRL_TO_PME 0x0400 205#define SOFTWARE_RESET_ENABLE 0x8000 206 207/* 208 * should be using the above defines, probably. 209 */ 210#define REGB_ENABLE_RESET 0x01 211#define REGB_STOP_CLOCK 0x10 212 213#define HOST_INT_STATUS 0x1A 214#define SB_INT_PENDING 0x01 215#define MPU401_INT_PENDING 0x02 216#define ASSP_INT_PENDING 0x10 217#define RING_INT_PENDING 0x20 218#define HV_INT_PENDING 0x40 219 220#define HARDWARE_VOL_CTRL 0x1B 221#define SHADOW_MIX_REG_VOICE 0x1C 222#define HW_VOL_COUNTER_VOICE 0x1D 223#define SHADOW_MIX_REG_MASTER 0x1E 224#define HW_VOL_COUNTER_MASTER 0x1F 225 226#define CODEC_COMMAND 0x30 227#define CODEC_READ_B 0x80 228 229#define CODEC_STATUS 0x30 230#define CODEC_BUSY_B 0x01 231 232#define CODEC_DATA 0x32 233 234#define RING_BUS_CTRL_A 0x36 235#define RAC_PME_ENABLE 0x0100 236#define RAC_SDFS_ENABLE 0x0200 237#define LAC_PME_ENABLE 0x0400 238#define LAC_SDFS_ENABLE 0x0800 239#define SERIAL_AC_LINK_ENABLE 0x1000 240#define IO_SRAM_ENABLE 0x2000 241#define IIS_INPUT_ENABLE 0x8000 242 243#define RING_BUS_CTRL_B 0x38 244#define SECOND_CODEC_ID_MASK 0x0003 245#define SPDIF_FUNC_ENABLE 0x0010 246#define SECOND_AC_ENABLE 0x0020 247#define SB_MODULE_INTF_ENABLE 0x0040 248#define SSPE_ENABLE 0x0040 249#define M3I_DOCK_ENABLE 0x0080 250 251#define SDO_OUT_DEST_CTRL 0x3A 252#define COMMAND_ADDR_OUT 0x0003 253#define PCM_LR_OUT_LOCAL 0x0000 254#define PCM_LR_OUT_REMOTE 0x0004 255#define PCM_LR_OUT_MUTE 0x0008 256#define PCM_LR_OUT_BOTH 0x000C 257#define LINE1_DAC_OUT_LOCAL 0x0000 258#define LINE1_DAC_OUT_REMOTE 0x0010 259#define LINE1_DAC_OUT_MUTE 0x0020 260#define LINE1_DAC_OUT_BOTH 0x0030 261#define PCM_CLS_OUT_LOCAL 0x0000 262#define PCM_CLS_OUT_REMOTE 0x0040 263#define PCM_CLS_OUT_MUTE 0x0080 264#define PCM_CLS_OUT_BOTH 0x00C0 265#define PCM_RLF_OUT_LOCAL 0x0000 266#define PCM_RLF_OUT_REMOTE 0x0100 267#define PCM_RLF_OUT_MUTE 0x0200 268#define PCM_RLF_OUT_BOTH 0x0300 269#define LINE2_DAC_OUT_LOCAL 0x0000 270#define LINE2_DAC_OUT_REMOTE 0x0400 271#define LINE2_DAC_OUT_MUTE 0x0800 272#define LINE2_DAC_OUT_BOTH 0x0C00 273#define HANDSET_OUT_LOCAL 0x0000 274#define HANDSET_OUT_REMOTE 0x1000 275#define HANDSET_OUT_MUTE 0x2000 276#define HANDSET_OUT_BOTH 0x3000 277#define IO_CTRL_OUT_LOCAL 0x0000 278#define IO_CTRL_OUT_REMOTE 0x4000 279#define IO_CTRL_OUT_MUTE 0x8000 280#define IO_CTRL_OUT_BOTH 0xC000 281 282#define SDO_IN_DEST_CTRL 0x3C 283#define STATUS_ADDR_IN 0x0003 284#define PCM_LR_IN_LOCAL 0x0000 285#define PCM_LR_IN_REMOTE 0x0004 286#define PCM_LR_RESERVED 0x0008 287#define PCM_LR_IN_BOTH 0x000C 288#define LINE1_ADC_IN_LOCAL 0x0000 289#define LINE1_ADC_IN_REMOTE 0x0010 290#define LINE1_ADC_IN_MUTE 0x0020 291#define MIC_ADC_IN_LOCAL 0x0000 292#define MIC_ADC_IN_REMOTE 0x0040 293#define MIC_ADC_IN_MUTE 0x0080 294#define LINE2_DAC_IN_LOCAL 0x0000 295#define LINE2_DAC_IN_REMOTE 0x0400 296#define LINE2_DAC_IN_MUTE 0x0800 297#define HANDSET_IN_LOCAL 0x0000 298#define HANDSET_IN_REMOTE 0x1000 299#define HANDSET_IN_MUTE 0x2000 300#define IO_STATUS_IN_LOCAL 0x0000 301#define IO_STATUS_IN_REMOTE 0x4000 302 303#define SPDIF_IN_CTRL 0x3E 304#define SPDIF_IN_ENABLE 0x0001 305 306#define GPIO_DATA 0x60 307#define GPIO_DATA_MASK 0x0FFF 308#define GPIO_HV_STATUS 0x3000 309#define GPIO_PME_STATUS 0x4000 310 311#define GPIO_MASK 0x64 312#define GPIO_DIRECTION 0x68 313#define GPO_PRIMARY_AC97 0x0001 314#define GPI_LINEOUT_SENSE 0x0004 315#define GPO_SECONDARY_AC97 0x0008 316#define GPI_VOL_DOWN 0x0010 317#define GPI_VOL_UP 0x0020 318#define GPI_IIS_CLK 0x0040 319#define GPI_IIS_LRCLK 0x0080 320#define GPI_IIS_DATA 0x0100 321#define GPI_DOCKING_STATUS 0x0100 322#define GPI_HEADPHONE_SENSE 0x0200 323#define GPO_EXT_AMP_SHUTDOWN 0x1000 324 325#define GPO_EXT_AMP_M3 1 /* default m3 amp */ 326#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */ 327 328/* M3 */ 329#define GPO_M3_EXT_AMP_SHUTDN 0x0002 330 331#define ASSP_INDEX_PORT 0x80 332#define ASSP_MEMORY_PORT 0x82 333#define ASSP_DATA_PORT 0x84 334 335#define MPU401_DATA_PORT 0x98 336#define MPU401_STATUS_PORT 0x99 337 338#define CLK_MULT_DATA_PORT 0x9C 339 340#define ASSP_CONTROL_A 0xA2 341#define ASSP_0_WS_ENABLE 0x01 342#define ASSP_CTRL_A_RESERVED1 0x02 343#define ASSP_CTRL_A_RESERVED2 0x04 344#define ASSP_CLK_49MHZ_SELECT 0x08 345#define FAST_PLU_ENABLE 0x10 346#define ASSP_CTRL_A_RESERVED3 0x20 347#define DSP_CLK_36MHZ_SELECT 0x40 348 349#define ASSP_CONTROL_B 0xA4 350#define RESET_ASSP 0x00 351#define RUN_ASSP 0x01 352#define ENABLE_ASSP_CLOCK 0x00 353#define STOP_ASSP_CLOCK 0x10 354#define RESET_TOGGLE 0x40 355 356#define ASSP_CONTROL_C 0xA6 357#define ASSP_HOST_INT_ENABLE 0x01 358#define FM_ADDR_REMAP_DISABLE 0x02 359#define HOST_WRITE_PORT_ENABLE 0x08 360 361#define ASSP_HOST_INT_STATUS 0xAC 362#define DSP2HOST_REQ_PIORECORD 0x01 363#define DSP2HOST_REQ_I2SRATE 0x02 364#define DSP2HOST_REQ_TIMER 0x04 365 366/* AC97 registers */ 367/*#define AC97_RESET 0x00*/ 368 369#define AC97_VOL_MUTE_B 0x8000 370#define AC97_VOL_M 0x1F 371#define AC97_LEFT_VOL_S 8 372 373#define AC97_MASTER_VOL 0x02 374#define AC97_LINE_LEVEL_VOL 0x04 375#define AC97_MASTER_MONO_VOL 0x06 376#define AC97_PC_BEEP_VOL 0x0A 377#define AC97_PC_BEEP_VOL_M 0x0F 378#define AC97_SROUND_MASTER_VOL 0x38 379#define AC97_PC_BEEP_VOL_S 1 380 381/*#define AC97_PHONE_VOL 0x0C 382#define AC97_MIC_VOL 0x0E*/ 383#define AC97_MIC_20DB_ENABLE 0x40 384 385/*#define AC97_LINEIN_VOL 0x10 386#define AC97_CD_VOL 0x12 387#define AC97_VIDEO_VOL 0x14 388#define AC97_AUX_VOL 0x16*/ 389#define AC97_PCM_OUT_VOL 0x18 390/*#define AC97_RECORD_SELECT 0x1A*/ 391#define AC97_RECORD_MIC 0x00 392#define AC97_RECORD_CD 0x01 393#define AC97_RECORD_VIDEO 0x02 394#define AC97_RECORD_AUX 0x03 395#define AC97_RECORD_MONO_MUX 0x02 396#define AC97_RECORD_DIGITAL 0x03 397#define AC97_RECORD_LINE 0x04 398#define AC97_RECORD_STEREO 0x05 399#define AC97_RECORD_MONO 0x06 400#define AC97_RECORD_PHONE 0x07 401 402/*#define AC97_RECORD_GAIN 0x1C*/ 403#define AC97_RECORD_VOL_M 0x0F 404 405/*#define AC97_GENERAL_PURPOSE 0x20*/ 406#define AC97_POWER_DOWN_CTRL 0x26 407#define AC97_ADC_READY 0x0001 408#define AC97_DAC_READY 0x0002 409#define AC97_ANALOG_READY 0x0004 410#define AC97_VREF_ON 0x0008 411#define AC97_PR0 0x0100 412#define AC97_PR1 0x0200 413#define AC97_PR2 0x0400 414#define AC97_PR3 0x0800 415#define AC97_PR4 0x1000 416 417#define AC97_RESERVED1 0x28 418 419#define AC97_VENDOR_TEST 0x5A 420 421#define AC97_CLOCK_DELAY 0x5C 422#define AC97_LINEOUT_MUX_SEL 0x0001 423#define AC97_MONO_MUX_SEL 0x0002 424#define AC97_CLOCK_DELAY_SEL 0x1F 425#define AC97_DAC_CDS_SHIFT 6 426#define AC97_ADC_CDS_SHIFT 11 427 428#define AC97_MULTI_CHANNEL_SEL 0x74 429 430/*#define AC97_VENDOR_ID1 0x7C 431#define AC97_VENDOR_ID2 0x7E*/ 432 433/* 434 * ASSP control regs 435 */ 436#define DSP_PORT_TIMER_COUNT 0x06 437 438#define DSP_PORT_MEMORY_INDEX 0x80 439 440#define DSP_PORT_MEMORY_TYPE 0x82 441#define MEMTYPE_INTERNAL_CODE 0x0002 442#define MEMTYPE_INTERNAL_DATA 0x0003 443#define MEMTYPE_MASK 0x0003 444 445#define DSP_PORT_MEMORY_DATA 0x84 446 447#define DSP_PORT_CONTROL_REG_A 0xA2 448#define DSP_PORT_CONTROL_REG_B 0xA4 449#define DSP_PORT_CONTROL_REG_C 0xA6 450 451#define REV_A_CODE_MEMORY_BEGIN 0x0000 452#define REV_A_CODE_MEMORY_END 0x0FFF 453#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 454#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) 455 456#define REV_B_CODE_MEMORY_BEGIN 0x0000 457#define REV_B_CODE_MEMORY_END 0x0BFF 458#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 459#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) 460 461#define REV_A_DATA_MEMORY_BEGIN 0x1000 462#define REV_A_DATA_MEMORY_END 0x2FFF 463#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 464#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) 465 466#define REV_B_DATA_MEMORY_BEGIN 0x1000 467#define REV_B_DATA_MEMORY_END 0x2BFF 468#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 469#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) 470 471 472#define NUM_UNITS_KERNEL_CODE 16 473#define NUM_UNITS_KERNEL_DATA 2 474 475#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 476#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 477 478/* 479 * Kernel data layout 480 */ 481 482#define DP_SHIFT_COUNT 7 483 484#define KDATA_BASE_ADDR 0x1000 485#define KDATA_BASE_ADDR2 0x1080 486 487#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) 488#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) 489#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) 490#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) 491#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) 492#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) 493#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) 494#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) 495#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) 496 497#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) 498#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) 499 500#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) 501#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) 502#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) 503#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) 504#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) 505#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) 506#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) 507#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) 508#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) 509#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) 510 511#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) 512#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) 513 514#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) 515#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) 516 517#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) 518#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) 519 520#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) 521#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) 522#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) 523 524#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) 525#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) 526#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) 527#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) 528#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) 529 530#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) 531#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) 532#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) 533 534#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) 535#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) 536#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) 537 538#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) 539#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) 540#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) 541#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) 542#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) 543#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) 544#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) 545#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) 546#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) 547#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) 548 549#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) 550#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) 551#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) 552 553#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) 554#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) 555 556#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) 557#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) 558#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) 559 560#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) 561#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) 562#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) 563#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) 564#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) 565#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) 566 567#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) 568#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) 569#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) 570#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) 571#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) 572#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) 573 574#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) 575#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) 576#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) 577#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) 578#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) 579#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) 580 581#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) 582#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) 583#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) 584#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) 585 586#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) 587#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) 588 589#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) 590#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) 591 592#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) 593#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) 594#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) 595#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) 596#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) 597 598#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) 599#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) 600 601#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) 602#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) 603#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) 604 605#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) 606#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) 607 608#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) 609 610#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) 611#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) 612#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) 613#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) 614#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) 615#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) 616#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) 617#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) 618#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) 619#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) 620#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) 621#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) 622 623#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) 624#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) 625#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) 626#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) 627 628#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) 629#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) 630 631#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) 632#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) 633#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) 634#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) 635 636#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) 637#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) 638#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) 639#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) 640#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) 641 642/* 643 * second 'segment' (?) reserved for mixer 644 * buffers.. 645 */ 646 647#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) 648#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) 649#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) 650#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) 651#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) 652#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) 653#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) 654#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) 655#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) 656#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) 657#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) 658#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) 659#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) 660#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) 661#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) 662#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) 663 664#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) 665#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) 666#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) 667#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) 668#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) 669#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) 670#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) 671#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) 672#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) 673#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) 674#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) 675 676#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) 677#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) 678#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) 679#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) 680#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) 681#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) 682 683#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) 684#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) 685#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) 686#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) 687 688/* 689 * client data area offsets 690 */ 691#define CDATA_INSTANCE_READY 0x00 692 693#define CDATA_HOST_SRC_ADDRL 0x01 694#define CDATA_HOST_SRC_ADDRH 0x02 695#define CDATA_HOST_SRC_END_PLUS_1L 0x03 696#define CDATA_HOST_SRC_END_PLUS_1H 0x04 697#define CDATA_HOST_SRC_CURRENTL 0x05 698#define CDATA_HOST_SRC_CURRENTH 0x06 699 700#define CDATA_IN_BUF_CONNECT 0x07 701#define CDATA_OUT_BUF_CONNECT 0x08 702 703#define CDATA_IN_BUF_BEGIN 0x09 704#define CDATA_IN_BUF_END_PLUS_1 0x0A 705#define CDATA_IN_BUF_HEAD 0x0B 706#define CDATA_IN_BUF_TAIL 0x0C 707#define CDATA_OUT_BUF_BEGIN 0x0D 708#define CDATA_OUT_BUF_END_PLUS_1 0x0E 709#define CDATA_OUT_BUF_HEAD 0x0F 710#define CDATA_OUT_BUF_TAIL 0x10 711 712#define CDATA_DMA_CONTROL 0x11 713#define CDATA_RESERVED 0x12 714 715#define CDATA_FREQUENCY 0x13 716#define CDATA_LEFT_VOLUME 0x14 717#define CDATA_RIGHT_VOLUME 0x15 718#define CDATA_LEFT_SUR_VOL 0x16 719#define CDATA_RIGHT_SUR_VOL 0x17 720 721#define CDATA_HEADER_LEN 0x18 722 723#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN 724#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) 725#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) 726#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) 727#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) 728#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) 729#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) 730#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) 731 732#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) 733#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 734#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 735#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) 736#define MINISRC_BIQUAD_STAGE 2 737#define MINISRC_COEF_LOC 0x175 738 739#define DMACONTROL_BLOCK_MASK 0x000F 740#define DMAC_BLOCK0_SELECTOR 0x0000 741#define DMAC_BLOCK1_SELECTOR 0x0001 742#define DMAC_BLOCK2_SELECTOR 0x0002 743#define DMAC_BLOCK3_SELECTOR 0x0003 744#define DMAC_BLOCK4_SELECTOR 0x0004 745#define DMAC_BLOCK5_SELECTOR 0x0005 746#define DMAC_BLOCK6_SELECTOR 0x0006 747#define DMAC_BLOCK7_SELECTOR 0x0007 748#define DMAC_BLOCK8_SELECTOR 0x0008 749#define DMAC_BLOCK9_SELECTOR 0x0009 750#define DMAC_BLOCKA_SELECTOR 0x000A 751#define DMAC_BLOCKB_SELECTOR 0x000B 752#define DMAC_BLOCKC_SELECTOR 0x000C 753#define DMAC_BLOCKD_SELECTOR 0x000D 754#define DMAC_BLOCKE_SELECTOR 0x000E 755#define DMAC_BLOCKF_SELECTOR 0x000F 756#define DMACONTROL_PAGE_MASK 0x00F0 757#define DMAC_PAGE0_SELECTOR 0x0030 758#define DMAC_PAGE1_SELECTOR 0x0020 759#define DMAC_PAGE2_SELECTOR 0x0010 760#define DMAC_PAGE3_SELECTOR 0x0000 761#define DMACONTROL_AUTOREPEAT 0x1000 762#define DMACONTROL_STOPPED 0x2000 763#define DMACONTROL_DIRECTION 0x0100 764 765/* 766 * an arbitrary volume we set the internal 767 * volume settings to so that the ac97 volume 768 * range is a little less insane. 0x7fff is 769 * max. 770 */ 771#define ARB_VOLUME ( 0x6800 ) 772 773/* 774 */ 775 776struct m3_list { 777 int curlen; 778 int mem_addr; 779 int max; 780}; 781 782struct m3_dma { 783 784 int number; 785 struct snd_pcm_substream *substream; 786 787 struct assp_instance { 788 unsigned short code, data; 789 } inst; 790 791 int running; 792 int opened; 793 794 unsigned long buffer_addr; 795 int dma_size; 796 int period_size; 797 unsigned int hwptr; 798 int count; 799 800 int index[3]; 801 struct m3_list *index_list[3]; 802 803 int in_lists; 804 805 struct list_head list; 806 807}; 808 809struct snd_m3 { 810 811 struct snd_card *card; 812 813 unsigned long iobase; 814 815 int irq; 816 unsigned int allegro_flag : 1; 817 818 struct snd_ac97 *ac97; 819 820 struct snd_pcm *pcm; 821 822 struct pci_dev *pci; 823 824 int dacs_active; 825 int timer_users; 826 827 struct m3_list msrc_list; 828 struct m3_list mixer_list; 829 struct m3_list adc1_list; 830 struct m3_list dma_list; 831 832 /* for storing reset state..*/ 833 u8 reset_state; 834 835 int external_amp; 836 int amp_gpio; /* gpio pin # for external amp, -1 = default */ 837 unsigned int hv_config; /* hardware-volume config bits */ 838 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION 839 (e.g. for IrDA on Dell Inspirons) */ 840 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */ 841 842 /* midi */ 843 struct snd_rawmidi *rmidi; 844 845 /* pcm streams */ 846 int num_substreams; 847 struct m3_dma *substreams; 848 849 spinlock_t reg_lock; 850 spinlock_t ac97_lock; 851 852 struct snd_kcontrol *master_switch; 853 struct snd_kcontrol *master_volume; 854 struct tasklet_struct hwvol_tq; 855 856#ifdef CONFIG_PM 857 u16 *suspend_mem; 858#endif 859 860 const struct firmware *assp_kernel_image; 861 const struct firmware *assp_minisrc_image; 862}; 863 864/* 865 * pci ids 866 */ 867static struct pci_device_id snd_m3_ids[] = { 868 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID, 869 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 870 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID, 871 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 872 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID, 873 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 874 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID, 875 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 876 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID, 877 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 878 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID, 879 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 880 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID, 881 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 882 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID, 883 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 884 {0,}, 885}; 886 887MODULE_DEVICE_TABLE(pci, snd_m3_ids); 888 889static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = { 890 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d), 891 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d), 892 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03), 893 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03), 894 { } /* END */ 895}; 896 897static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = { 898 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1), 899 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1), 900 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1), 901 { } /* END */ 902}; 903 904/* hardware volume quirks */ 905static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = { 906 /* Allegro chips */ 907 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 908 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 909 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 910 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 911 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 912 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 913 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 914 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 915 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 916 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 917 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 918 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 919 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 920 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 921 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 922 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 923 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 924 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 925 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 926 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 927 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 928 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 929 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 930 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 931 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), 932 SND_PCI_QUIRK(0x1033, 0x80F1, NULL, 933 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 934 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */ 935 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 936 SND_PCI_QUIRK(0x107B, 0x340A, NULL, 937 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 938 SND_PCI_QUIRK(0x107B, 0x3450, NULL, 939 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 940 SND_PCI_QUIRK(0x109F, 0x3134, NULL, 941 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 942 SND_PCI_QUIRK(0x109F, 0x3161, NULL, 943 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 944 SND_PCI_QUIRK(0x144D, 0x3280, NULL, 945 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 946 SND_PCI_QUIRK(0x144D, 0x3281, NULL, 947 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 948 SND_PCI_QUIRK(0x144D, 0xC002, NULL, 949 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 950 SND_PCI_QUIRK(0x144D, 0xC003, NULL, 951 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 952 SND_PCI_QUIRK(0x1509, 0x1740, NULL, 953 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 954 SND_PCI_QUIRK(0x1610, 0x0010, NULL, 955 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), 956 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE), 957 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE), 958 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE), 959 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE), 960 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE), 961 /* Maestro3 chips */ 962 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE), 963 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE), 964 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE), 965 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE), 966 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE), 967 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE), 968 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE), 969 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE), 970 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE), 971 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE), 972 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE), 973 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE), 974 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE), 975 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 976 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 977 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 978 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), 979 { } /* END */ 980}; 981 982/* HP Omnibook quirks */ 983static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = { 984 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */ 985 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */ 986 { } /* END */ 987}; 988 989/* 990 * lowlevel functions 991 */ 992 993static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg) 994{ 995 outw(value, chip->iobase + reg); 996} 997 998static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg) 999{ 1000 return inw(chip->iobase + reg); 1001} 1002 1003static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg) 1004{ 1005 outb(value, chip->iobase + reg); 1006} 1007 1008static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg) 1009{ 1010 return inb(chip->iobase + reg); 1011} 1012 1013/* 1014 * access 16bit words to the code or data regions of the dsp's memory. 1015 * index addresses 16bit words. 1016 */ 1017static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index) 1018{ 1019 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); 1020 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); 1021 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA); 1022} 1023 1024static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data) 1025{ 1026 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); 1027 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); 1028 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA); 1029} 1030 1031static void snd_m3_assp_halt(struct snd_m3 *chip) 1032{ 1033 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; 1034 msleep(10); 1035 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); 1036} 1037 1038static void snd_m3_assp_continue(struct snd_m3 *chip) 1039{ 1040 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); 1041} 1042 1043 1044/* 1045 * This makes me sad. the maestro3 has lists 1046 * internally that must be packed.. 0 terminates, 1047 * apparently, or maybe all unused entries have 1048 * to be 0, the lists have static lengths set 1049 * by the binary code images. 1050 */ 1051 1052static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val) 1053{ 1054 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1055 list->mem_addr + list->curlen, 1056 val); 1057 return list->curlen++; 1058} 1059 1060static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index) 1061{ 1062 u16 val; 1063 int lastindex = list->curlen - 1; 1064 1065 if (index != lastindex) { 1066 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1067 list->mem_addr + lastindex); 1068 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1069 list->mem_addr + index, 1070 val); 1071 } 1072 1073 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1074 list->mem_addr + lastindex, 1075 0); 1076 1077 list->curlen--; 1078} 1079 1080static void snd_m3_inc_timer_users(struct snd_m3 *chip) 1081{ 1082 chip->timer_users++; 1083 if (chip->timer_users != 1) 1084 return; 1085 1086 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1087 KDATA_TIMER_COUNT_RELOAD, 1088 240); 1089 1090 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1091 KDATA_TIMER_COUNT_CURRENT, 1092 240); 1093 1094 snd_m3_outw(chip, 1095 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE, 1096 HOST_INT_CTRL); 1097} 1098 1099static void snd_m3_dec_timer_users(struct snd_m3 *chip) 1100{ 1101 chip->timer_users--; 1102 if (chip->timer_users > 0) 1103 return; 1104 1105 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1106 KDATA_TIMER_COUNT_RELOAD, 1107 0); 1108 1109 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1110 KDATA_TIMER_COUNT_CURRENT, 1111 0); 1112 1113 snd_m3_outw(chip, 1114 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE, 1115 HOST_INT_CTRL); 1116} 1117 1118/* 1119 * start/stop 1120 */ 1121 1122/* spinlock held! */ 1123static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s, 1124 struct snd_pcm_substream *subs) 1125{ 1126 if (! s || ! subs) 1127 return -EINVAL; 1128 1129 snd_m3_inc_timer_users(chip); 1130 switch (subs->stream) { 1131 case SNDRV_PCM_STREAM_PLAYBACK: 1132 chip->dacs_active++; 1133 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1134 s->inst.data + CDATA_INSTANCE_READY, 1); 1135 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1136 KDATA_MIXER_TASK_NUMBER, 1137 chip->dacs_active); 1138 break; 1139 case SNDRV_PCM_STREAM_CAPTURE: 1140 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1141 KDATA_ADC1_REQUEST, 1); 1142 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1143 s->inst.data + CDATA_INSTANCE_READY, 1); 1144 break; 1145 } 1146 return 0; 1147} 1148 1149/* spinlock held! */ 1150static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s, 1151 struct snd_pcm_substream *subs) 1152{ 1153 if (! s || ! subs) 1154 return -EINVAL; 1155 1156 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1157 s->inst.data + CDATA_INSTANCE_READY, 0); 1158 snd_m3_dec_timer_users(chip); 1159 switch (subs->stream) { 1160 case SNDRV_PCM_STREAM_PLAYBACK: 1161 chip->dacs_active--; 1162 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1163 KDATA_MIXER_TASK_NUMBER, 1164 chip->dacs_active); 1165 break; 1166 case SNDRV_PCM_STREAM_CAPTURE: 1167 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1168 KDATA_ADC1_REQUEST, 0); 1169 break; 1170 } 1171 return 0; 1172} 1173 1174static int 1175snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd) 1176{ 1177 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1178 struct m3_dma *s = subs->runtime->private_data; 1179 int err = -EINVAL; 1180 1181 snd_assert(s != NULL, return -ENXIO); 1182 1183 spin_lock(&chip->reg_lock); 1184 switch (cmd) { 1185 case SNDRV_PCM_TRIGGER_START: 1186 case SNDRV_PCM_TRIGGER_RESUME: 1187 if (s->running) 1188 err = -EBUSY; 1189 else { 1190 s->running = 1; 1191 err = snd_m3_pcm_start(chip, s, subs); 1192 } 1193 break; 1194 case SNDRV_PCM_TRIGGER_STOP: 1195 case SNDRV_PCM_TRIGGER_SUSPEND: 1196 if (! s->running) 1197 err = 0; /* should return error? */ 1198 else { 1199 s->running = 0; 1200 err = snd_m3_pcm_stop(chip, s, subs); 1201 } 1202 break; 1203 } 1204 spin_unlock(&chip->reg_lock); 1205 return err; 1206} 1207 1208/* 1209 * setup 1210 */ 1211static void 1212snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) 1213{ 1214 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer; 1215 struct snd_pcm_runtime *runtime = subs->runtime; 1216 1217 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1218 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 1219 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 1220 } else { 1221 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); 1222 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 1223 } 1224 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2); 1225 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1; 1226 1227 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size); 1228 s->period_size = frames_to_bytes(runtime, runtime->period_size); 1229 s->hwptr = 0; 1230 s->count = 0; 1231 1232#define LO(x) ((x) & 0xffff) 1233#define HI(x) LO((x) >> 16) 1234 1235 /* host dma buffer pointers */ 1236 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1237 s->inst.data + CDATA_HOST_SRC_ADDRL, 1238 LO(s->buffer_addr)); 1239 1240 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1241 s->inst.data + CDATA_HOST_SRC_ADDRH, 1242 HI(s->buffer_addr)); 1243 1244 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1245 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L, 1246 LO(s->buffer_addr + s->dma_size)); 1247 1248 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1249 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H, 1250 HI(s->buffer_addr + s->dma_size)); 1251 1252 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1253 s->inst.data + CDATA_HOST_SRC_CURRENTL, 1254 LO(s->buffer_addr)); 1255 1256 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1257 s->inst.data + CDATA_HOST_SRC_CURRENTH, 1258 HI(s->buffer_addr)); 1259#undef LO 1260#undef HI 1261 1262 /* dsp buffers */ 1263 1264 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1265 s->inst.data + CDATA_IN_BUF_BEGIN, 1266 dsp_in_buffer); 1267 1268 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1269 s->inst.data + CDATA_IN_BUF_END_PLUS_1, 1270 dsp_in_buffer + (dsp_in_size / 2)); 1271 1272 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1273 s->inst.data + CDATA_IN_BUF_HEAD, 1274 dsp_in_buffer); 1275 1276 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1277 s->inst.data + CDATA_IN_BUF_TAIL, 1278 dsp_in_buffer); 1279 1280 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1281 s->inst.data + CDATA_OUT_BUF_BEGIN, 1282 dsp_out_buffer); 1283 1284 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1285 s->inst.data + CDATA_OUT_BUF_END_PLUS_1, 1286 dsp_out_buffer + (dsp_out_size / 2)); 1287 1288 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1289 s->inst.data + CDATA_OUT_BUF_HEAD, 1290 dsp_out_buffer); 1291 1292 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1293 s->inst.data + CDATA_OUT_BUF_TAIL, 1294 dsp_out_buffer); 1295} 1296 1297static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s, 1298 struct snd_pcm_runtime *runtime) 1299{ 1300 u32 freq; 1301 1302 /* 1303 * put us in the lists if we're not already there 1304 */ 1305 if (! s->in_lists) { 1306 s->index[0] = snd_m3_add_list(chip, s->index_list[0], 1307 s->inst.data >> DP_SHIFT_COUNT); 1308 s->index[1] = snd_m3_add_list(chip, s->index_list[1], 1309 s->inst.data >> DP_SHIFT_COUNT); 1310 s->index[2] = snd_m3_add_list(chip, s->index_list[2], 1311 s->inst.data >> DP_SHIFT_COUNT); 1312 s->in_lists = 1; 1313 } 1314 1315 /* write to 'mono' word */ 1316 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1317 s->inst.data + SRC3_DIRECTION_OFFSET + 1, 1318 runtime->channels == 2 ? 0 : 1); 1319 /* write to '8bit' word */ 1320 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1321 s->inst.data + SRC3_DIRECTION_OFFSET + 2, 1322 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1); 1323 1324 /* set up dac/adc rate */ 1325 freq = ((runtime->rate << 15) + 24000 ) / 48000; 1326 if (freq) 1327 freq--; 1328 1329 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1330 s->inst.data + CDATA_FREQUENCY, 1331 freq); 1332} 1333 1334 1335static const struct play_vals { 1336 u16 addr, val; 1337} pv[] = { 1338 {CDATA_LEFT_VOLUME, ARB_VOLUME}, 1339 {CDATA_RIGHT_VOLUME, ARB_VOLUME}, 1340 {SRC3_DIRECTION_OFFSET, 0} , 1341 /* +1, +2 are stereo/16 bit */ 1342 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ 1343 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ 1344 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ 1345 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ 1346 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ 1347 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ 1348 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ 1349 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ 1350 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ 1351 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ 1352 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ 1353 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ 1354 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ 1355 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ 1356 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ 1357 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ 1358 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ 1359}; 1360 1361 1362/* the mode passed should be already shifted and masked */ 1363static void 1364snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s, 1365 struct snd_pcm_substream *subs) 1366{ 1367 unsigned int i; 1368 1369 /* 1370 * some per client initializers 1371 */ 1372 1373 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1374 s->inst.data + SRC3_DIRECTION_OFFSET + 12, 1375 s->inst.data + 40 + 8); 1376 1377 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1378 s->inst.data + SRC3_DIRECTION_OFFSET + 19, 1379 s->inst.code + MINISRC_COEF_LOC); 1380 1381 /* enable or disable low pass filter? */ 1382 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1383 s->inst.data + SRC3_DIRECTION_OFFSET + 22, 1384 subs->runtime->rate > 45000 ? 0xff : 0); 1385 1386 /* tell it which way dma is going? */ 1387 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1388 s->inst.data + CDATA_DMA_CONTROL, 1389 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 1390 1391 /* 1392 * set an armload of static initializers 1393 */ 1394 for (i = 0; i < ARRAY_SIZE(pv); i++) 1395 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1396 s->inst.data + pv[i].addr, pv[i].val); 1397} 1398 1399/* 1400 * Native record driver 1401 */ 1402static const struct rec_vals { 1403 u16 addr, val; 1404} rv[] = { 1405 {CDATA_LEFT_VOLUME, ARB_VOLUME}, 1406 {CDATA_RIGHT_VOLUME, ARB_VOLUME}, 1407 {SRC3_DIRECTION_OFFSET, 1} , 1408 /* +1, +2 are stereo/16 bit */ 1409 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ 1410 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ 1411 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ 1412 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ 1413 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ 1414 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ 1415 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ 1416 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ 1417 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ 1418 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ 1419 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ 1420 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ 1421 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ 1422 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ 1423 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ 1424 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ 1425 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ 1426 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ 1427 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ 1428}; 1429 1430static void 1431snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) 1432{ 1433 unsigned int i; 1434 1435 /* 1436 * some per client initializers 1437 */ 1438 1439 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1440 s->inst.data + SRC3_DIRECTION_OFFSET + 12, 1441 s->inst.data + 40 + 8); 1442 1443 /* tell it which way dma is going? */ 1444 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1445 s->inst.data + CDATA_DMA_CONTROL, 1446 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 1447 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 1448 1449 /* 1450 * set an armload of static initializers 1451 */ 1452 for (i = 0; i < ARRAY_SIZE(rv); i++) 1453 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1454 s->inst.data + rv[i].addr, rv[i].val); 1455} 1456 1457static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream, 1458 struct snd_pcm_hw_params *hw_params) 1459{ 1460 struct m3_dma *s = substream->runtime->private_data; 1461 int err; 1462 1463 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 1464 return err; 1465 /* set buffer address */ 1466 s->buffer_addr = substream->runtime->dma_addr; 1467 if (s->buffer_addr & 0x3) { 1468 snd_printk(KERN_ERR "oh my, not aligned\n"); 1469 s->buffer_addr = s->buffer_addr & ~0x3; 1470 } 1471 return 0; 1472} 1473 1474static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream) 1475{ 1476 struct m3_dma *s; 1477 1478 if (substream->runtime->private_data == NULL) 1479 return 0; 1480 s = substream->runtime->private_data; 1481 snd_pcm_lib_free_pages(substream); 1482 s->buffer_addr = 0; 1483 return 0; 1484} 1485 1486static int 1487snd_m3_pcm_prepare(struct snd_pcm_substream *subs) 1488{ 1489 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1490 struct snd_pcm_runtime *runtime = subs->runtime; 1491 struct m3_dma *s = runtime->private_data; 1492 1493 snd_assert(s != NULL, return -ENXIO); 1494 1495 if (runtime->format != SNDRV_PCM_FORMAT_U8 && 1496 runtime->format != SNDRV_PCM_FORMAT_S16_LE) 1497 return -EINVAL; 1498 if (runtime->rate > 48000 || 1499 runtime->rate < 8000) 1500 return -EINVAL; 1501 1502 spin_lock_irq(&chip->reg_lock); 1503 1504 snd_m3_pcm_setup1(chip, s, subs); 1505 1506 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) 1507 snd_m3_playback_setup(chip, s, subs); 1508 else 1509 snd_m3_capture_setup(chip, s, subs); 1510 1511 snd_m3_pcm_setup2(chip, s, runtime); 1512 1513 spin_unlock_irq(&chip->reg_lock); 1514 1515 return 0; 1516} 1517 1518/* 1519 * get current pointer 1520 */ 1521static unsigned int 1522snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) 1523{ 1524 u16 hi = 0, lo = 0; 1525 int retry = 10; 1526 u32 addr; 1527 1528 /* 1529 * try and get a valid answer 1530 */ 1531 while (retry--) { 1532 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1533 s->inst.data + CDATA_HOST_SRC_CURRENTH); 1534 1535 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1536 s->inst.data + CDATA_HOST_SRC_CURRENTL); 1537 1538 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1539 s->inst.data + CDATA_HOST_SRC_CURRENTH)) 1540 break; 1541 } 1542 addr = lo | ((u32)hi<<16); 1543 return (unsigned int)(addr - s->buffer_addr); 1544} 1545 1546static snd_pcm_uframes_t 1547snd_m3_pcm_pointer(struct snd_pcm_substream *subs) 1548{ 1549 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1550 unsigned int ptr; 1551 struct m3_dma *s = subs->runtime->private_data; 1552 snd_assert(s != NULL, return 0); 1553 1554 spin_lock(&chip->reg_lock); 1555 ptr = snd_m3_get_pointer(chip, s, subs); 1556 spin_unlock(&chip->reg_lock); 1557 return bytes_to_frames(subs->runtime, ptr); 1558} 1559 1560 1561/* update pointer */ 1562/* spinlock held! */ 1563static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s) 1564{ 1565 struct snd_pcm_substream *subs = s->substream; 1566 unsigned int hwptr; 1567 int diff; 1568 1569 if (! s->running) 1570 return; 1571 1572 hwptr = snd_m3_get_pointer(chip, s, subs); 1573 1574 /* try to avoid expensive modulo divisions */ 1575 if (hwptr >= s->dma_size) 1576 hwptr %= s->dma_size; 1577 1578 diff = s->dma_size + hwptr - s->hwptr; 1579 if (diff >= s->dma_size) 1580 diff %= s->dma_size; 1581 1582 s->hwptr = hwptr; 1583 s->count += diff; 1584 1585 if (s->count >= (signed)s->period_size) { 1586 1587 if (s->count < 2 * (signed)s->period_size) 1588 s->count -= (signed)s->period_size; 1589 else 1590 s->count %= s->period_size; 1591 1592 spin_unlock(&chip->reg_lock); 1593 snd_pcm_period_elapsed(subs); 1594 spin_lock(&chip->reg_lock); 1595 } 1596} 1597 1598static void snd_m3_update_hw_volume(unsigned long private_data) 1599{ 1600 struct snd_m3 *chip = (struct snd_m3 *) private_data; 1601 int x, val; 1602 unsigned long flags; 1603 1604 /* Figure out which volume control button was pushed, 1605 based on differences from the default register 1606 values. */ 1607 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee; 1608 1609 /* Reset the volume control registers. */ 1610 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE); 1611 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE); 1612 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER); 1613 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER); 1614 1615 if (!chip->master_switch || !chip->master_volume) 1616 return; 1617 1618 spin_lock_irqsave(&chip->ac97_lock, flags); 1619 1620 val = chip->ac97->regs[AC97_MASTER_VOL]; 1621 switch (x) { 1622 case 0x88: 1623 /* mute */ 1624 val ^= 0x8000; 1625 chip->ac97->regs[AC97_MASTER_VOL] = val; 1626 outw(val, chip->iobase + CODEC_DATA); 1627 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND); 1628 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1629 &chip->master_switch->id); 1630 break; 1631 case 0xaa: 1632 /* volume up */ 1633 if ((val & 0x7f) > 0) 1634 val--; 1635 if ((val & 0x7f00) > 0) 1636 val -= 0x0100; 1637 chip->ac97->regs[AC97_MASTER_VOL] = val; 1638 outw(val, chip->iobase + CODEC_DATA); 1639 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND); 1640 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1641 &chip->master_volume->id); 1642 break; 1643 case 0x66: 1644 /* volume down */ 1645 if ((val & 0x7f) < 0x1f) 1646 val++; 1647 if ((val & 0x7f00) < 0x1f00) 1648 val += 0x0100; 1649 chip->ac97->regs[AC97_MASTER_VOL] = val; 1650 outw(val, chip->iobase + CODEC_DATA); 1651 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND); 1652 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1653 &chip->master_volume->id); 1654 break; 1655 } 1656 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1657} 1658 1659static irqreturn_t snd_m3_interrupt(int irq, void *dev_id) 1660{ 1661 struct snd_m3 *chip = dev_id; 1662 u8 status; 1663 int i; 1664 1665 status = inb(chip->iobase + HOST_INT_STATUS); 1666 1667 if (status == 0xff) 1668 return IRQ_NONE; 1669 1670 if (status & HV_INT_PENDING) 1671 tasklet_hi_schedule(&chip->hwvol_tq); 1672 1673 /* 1674 * ack an assp int if its running 1675 * and has an int pending 1676 */ 1677 if (status & ASSP_INT_PENDING) { 1678 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B); 1679 if (!(ctl & STOP_ASSP_CLOCK)) { 1680 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS); 1681 if (ctl & DSP2HOST_REQ_TIMER) { 1682 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS); 1683 /* update adc/dac info if it was a timer int */ 1684 spin_lock(&chip->reg_lock); 1685 for (i = 0; i < chip->num_substreams; i++) { 1686 struct m3_dma *s = &chip->substreams[i]; 1687 if (s->running) 1688 snd_m3_update_ptr(chip, s); 1689 } 1690 spin_unlock(&chip->reg_lock); 1691 } 1692 } 1693 } 1694 1695 1696 /* ack ints */ 1697 outb(status, chip->iobase + HOST_INT_STATUS); 1698 1699 return IRQ_HANDLED; 1700} 1701 1702 1703/* 1704 */ 1705 1706static struct snd_pcm_hardware snd_m3_playback = 1707{ 1708 .info = (SNDRV_PCM_INFO_MMAP | 1709 SNDRV_PCM_INFO_INTERLEAVED | 1710 SNDRV_PCM_INFO_MMAP_VALID | 1711 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1712 /*SNDRV_PCM_INFO_PAUSE |*/ 1713 SNDRV_PCM_INFO_RESUME), 1714 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1715 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1716 .rate_min = 8000, 1717 .rate_max = 48000, 1718 .channels_min = 1, 1719 .channels_max = 2, 1720 .buffer_bytes_max = (512*1024), 1721 .period_bytes_min = 64, 1722 .period_bytes_max = (512*1024), 1723 .periods_min = 1, 1724 .periods_max = 1024, 1725}; 1726 1727static struct snd_pcm_hardware snd_m3_capture = 1728{ 1729 .info = (SNDRV_PCM_INFO_MMAP | 1730 SNDRV_PCM_INFO_INTERLEAVED | 1731 SNDRV_PCM_INFO_MMAP_VALID | 1732 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1733 /*SNDRV_PCM_INFO_PAUSE |*/ 1734 SNDRV_PCM_INFO_RESUME), 1735 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1736 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1737 .rate_min = 8000, 1738 .rate_max = 48000, 1739 .channels_min = 1, 1740 .channels_max = 2, 1741 .buffer_bytes_max = (512*1024), 1742 .period_bytes_min = 64, 1743 .period_bytes_max = (512*1024), 1744 .periods_min = 1, 1745 .periods_max = 1024, 1746}; 1747 1748 1749/* 1750 */ 1751 1752static int 1753snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs) 1754{ 1755 int i; 1756 struct m3_dma *s; 1757 1758 spin_lock_irq(&chip->reg_lock); 1759 for (i = 0; i < chip->num_substreams; i++) { 1760 s = &chip->substreams[i]; 1761 if (! s->opened) 1762 goto __found; 1763 } 1764 spin_unlock_irq(&chip->reg_lock); 1765 return -ENOMEM; 1766__found: 1767 s->opened = 1; 1768 s->running = 0; 1769 spin_unlock_irq(&chip->reg_lock); 1770 1771 subs->runtime->private_data = s; 1772 s->substream = subs; 1773 1774 /* set list owners */ 1775 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1776 s->index_list[0] = &chip->mixer_list; 1777 } else 1778 s->index_list[0] = &chip->adc1_list; 1779 s->index_list[1] = &chip->msrc_list; 1780 s->index_list[2] = &chip->dma_list; 1781 1782 return 0; 1783} 1784 1785static void 1786snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs) 1787{ 1788 struct m3_dma *s = subs->runtime->private_data; 1789 1790 if (s == NULL) 1791 return; /* not opened properly */ 1792 1793 spin_lock_irq(&chip->reg_lock); 1794 if (s->substream && s->running) 1795 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */ 1796 if (s->in_lists) { 1797 snd_m3_remove_list(chip, s->index_list[0], s->index[0]); 1798 snd_m3_remove_list(chip, s->index_list[1], s->index[1]); 1799 snd_m3_remove_list(chip, s->index_list[2], s->index[2]); 1800 s->in_lists = 0; 1801 } 1802 s->running = 0; 1803 s->opened = 0; 1804 spin_unlock_irq(&chip->reg_lock); 1805} 1806 1807static int 1808snd_m3_playback_open(struct snd_pcm_substream *subs) 1809{ 1810 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1811 struct snd_pcm_runtime *runtime = subs->runtime; 1812 int err; 1813 1814 if ((err = snd_m3_substream_open(chip, subs)) < 0) 1815 return err; 1816 1817 runtime->hw = snd_m3_playback; 1818 snd_pcm_set_sync(subs); 1819 1820 return 0; 1821} 1822 1823static int 1824snd_m3_playback_close(struct snd_pcm_substream *subs) 1825{ 1826 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1827 1828 snd_m3_substream_close(chip, subs); 1829 return 0; 1830} 1831 1832static int 1833snd_m3_capture_open(struct snd_pcm_substream *subs) 1834{ 1835 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1836 struct snd_pcm_runtime *runtime = subs->runtime; 1837 int err; 1838 1839 if ((err = snd_m3_substream_open(chip, subs)) < 0) 1840 return err; 1841 1842 runtime->hw = snd_m3_capture; 1843 snd_pcm_set_sync(subs); 1844 1845 return 0; 1846} 1847 1848static int 1849snd_m3_capture_close(struct snd_pcm_substream *subs) 1850{ 1851 struct snd_m3 *chip = snd_pcm_substream_chip(subs); 1852 1853 snd_m3_substream_close(chip, subs); 1854 return 0; 1855} 1856 1857/* 1858 * create pcm instance 1859 */ 1860 1861static struct snd_pcm_ops snd_m3_playback_ops = { 1862 .open = snd_m3_playback_open, 1863 .close = snd_m3_playback_close, 1864 .ioctl = snd_pcm_lib_ioctl, 1865 .hw_params = snd_m3_pcm_hw_params, 1866 .hw_free = snd_m3_pcm_hw_free, 1867 .prepare = snd_m3_pcm_prepare, 1868 .trigger = snd_m3_pcm_trigger, 1869 .pointer = snd_m3_pcm_pointer, 1870}; 1871 1872static struct snd_pcm_ops snd_m3_capture_ops = { 1873 .open = snd_m3_capture_open, 1874 .close = snd_m3_capture_close, 1875 .ioctl = snd_pcm_lib_ioctl, 1876 .hw_params = snd_m3_pcm_hw_params, 1877 .hw_free = snd_m3_pcm_hw_free, 1878 .prepare = snd_m3_pcm_prepare, 1879 .trigger = snd_m3_pcm_trigger, 1880 .pointer = snd_m3_pcm_pointer, 1881}; 1882 1883static int __devinit 1884snd_m3_pcm(struct snd_m3 * chip, int device) 1885{ 1886 struct snd_pcm *pcm; 1887 int err; 1888 1889 err = snd_pcm_new(chip->card, chip->card->driver, device, 1890 MAX_PLAYBACKS, MAX_CAPTURES, &pcm); 1891 if (err < 0) 1892 return err; 1893 1894 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops); 1895 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops); 1896 1897 pcm->private_data = chip; 1898 pcm->info_flags = 0; 1899 strcpy(pcm->name, chip->card->driver); 1900 chip->pcm = pcm; 1901 1902 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1903 snd_dma_pci_data(chip->pci), 64*1024, 64*1024); 1904 1905 return 0; 1906} 1907 1908 1909/* 1910 * ac97 interface 1911 */ 1912 1913/* 1914 * Wait for the ac97 serial bus to be free. 1915 * return nonzero if the bus is still busy. 1916 */ 1917static int snd_m3_ac97_wait(struct snd_m3 *chip) 1918{ 1919 int i = 10000; 1920 1921 do { 1922 if (! (snd_m3_inb(chip, 0x30) & 1)) 1923 return 0; 1924 cpu_relax(); 1925 } while (i-- > 0); 1926 1927 snd_printk(KERN_ERR "ac97 serial bus busy\n"); 1928 return 1; 1929} 1930 1931static unsigned short 1932snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 1933{ 1934 struct snd_m3 *chip = ac97->private_data; 1935 unsigned long flags; 1936 unsigned short data = 0xffff; 1937 1938 if (snd_m3_ac97_wait(chip)) 1939 goto fail; 1940 spin_lock_irqsave(&chip->ac97_lock, flags); 1941 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); 1942 if (snd_m3_ac97_wait(chip)) 1943 goto fail_unlock; 1944 data = snd_m3_inw(chip, CODEC_DATA); 1945fail_unlock: 1946 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1947fail: 1948 return data; 1949} 1950 1951static void 1952snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) 1953{ 1954 struct snd_m3 *chip = ac97->private_data; 1955 unsigned long flags; 1956 1957 if (snd_m3_ac97_wait(chip)) 1958 return; 1959 spin_lock_irqsave(&chip->ac97_lock, flags); 1960 snd_m3_outw(chip, val, CODEC_DATA); 1961 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); 1962 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1963} 1964 1965 1966static void snd_m3_remote_codec_config(int io, int isremote) 1967{ 1968 isremote = isremote ? 1 : 0; 1969 1970 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote, 1971 io + RING_BUS_CTRL_B); 1972 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote, 1973 io + SDO_OUT_DEST_CTRL); 1974 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote, 1975 io + SDO_IN_DEST_CTRL); 1976} 1977 1978/* 1979 * hack, returns non zero on err 1980 */ 1981static int snd_m3_try_read_vendor(struct snd_m3 *chip) 1982{ 1983 u16 ret; 1984 1985 if (snd_m3_ac97_wait(chip)) 1986 return 1; 1987 1988 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30); 1989 1990 if (snd_m3_ac97_wait(chip)) 1991 return 1; 1992 1993 ret = snd_m3_inw(chip, 0x32); 1994 1995 return (ret == 0) || (ret == 0xffff); 1996} 1997 1998static void snd_m3_ac97_reset(struct snd_m3 *chip) 1999{ 2000 u16 dir; 2001 int delay1 = 0, delay2 = 0, i; 2002 int io = chip->iobase; 2003 2004 if (chip->allegro_flag) { 2005 /* 2006 * the onboard codec on the allegro seems 2007 * to want to wait a very long time before 2008 * coming back to life 2009 */ 2010 delay1 = 50; 2011 delay2 = 800; 2012 } else { 2013 /* maestro3 */ 2014 delay1 = 20; 2015 delay2 = 500; 2016 } 2017 2018 for (i = 0; i < 5; i++) { 2019 dir = inw(io + GPIO_DIRECTION); 2020 if (!chip->irda_workaround) 2021 dir |= 0x10; /* assuming pci bus master? */ 2022 2023 snd_m3_remote_codec_config(io, 0); 2024 2025 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A); 2026 udelay(20); 2027 2028 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION); 2029 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK); 2030 outw(0, io + GPIO_DATA); 2031 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION); 2032 2033 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1)); 2034 2035 outw(GPO_PRIMARY_AC97, io + GPIO_DATA); 2036 udelay(5); 2037 /* ok, bring back the ac-link */ 2038 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A); 2039 outw(~0, io + GPIO_MASK); 2040 2041 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2)); 2042 2043 if (! snd_m3_try_read_vendor(chip)) 2044 break; 2045 2046 delay1 += 10; 2047 delay2 += 100; 2048 2049 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n", 2050 delay1, delay2); 2051 } 2052 2053} 2054 2055static int __devinit snd_m3_mixer(struct snd_m3 *chip) 2056{ 2057 struct snd_ac97_bus *pbus; 2058 struct snd_ac97_template ac97; 2059 struct snd_ctl_elem_id id; 2060 int err; 2061 static struct snd_ac97_bus_ops ops = { 2062 .write = snd_m3_ac97_write, 2063 .read = snd_m3_ac97_read, 2064 }; 2065 2066 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) 2067 return err; 2068 2069 memset(&ac97, 0, sizeof(ac97)); 2070 ac97.private_data = chip; 2071 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) 2072 return err; 2073 2074 /* seems ac97 PCM needs initialization.. hack hack.. */ 2075 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15); 2076 schedule_timeout_uninterruptible(msecs_to_jiffies(100)); 2077 snd_ac97_write(chip->ac97, AC97_PCM, 0); 2078 2079 memset(&id, 0, sizeof(id)); 2080 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2081 strcpy(id.name, "Master Playback Switch"); 2082 chip->master_switch = snd_ctl_find_id(chip->card, &id); 2083 memset(&id, 0, sizeof(id)); 2084 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2085 strcpy(id.name, "Master Playback Volume"); 2086 chip->master_volume = snd_ctl_find_id(chip->card, &id); 2087 2088 return 0; 2089} 2090 2091 2092#ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL 2093 2094/* 2095 * DSP Code images 2096 */ 2097 2098static const u16 assp_kernel_image[] = { 2099 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4, 2100 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 2101 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 2102 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4, 2103 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08, 2104 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909, 2105 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41, 2106 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308, 2107 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910, 2108 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00, 2109 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026, 2110 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0, 2111 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012, 2112 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A, 2113 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000, 2114 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05, 2115 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26, 2116 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300, 2117 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88, 2118 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008, 2119 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80, 2120 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71, 2121 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A, 2122 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100, 2123 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900, 2124 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903, 2125 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309, 2126 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B, 2127 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540, 2128 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C, 2129 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380, 2130 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340, 2131 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041, 2132 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18, 2133 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 2134 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9, 2135 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8, 2136 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A, 2137 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80, 2138 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 2139 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80, 2140 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A, 2141 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F, 2142 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1, 2143 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034, 2144 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 2145 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977, 2146 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B, 2147 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388, 2148 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 2149 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473, 2150 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473, 2151 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880, 2152 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80, 2153 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6, 2154 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909, 2155 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED, 2156 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005, 2157 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 2158 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4, 2159 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 2160 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10, 2161 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070, 2162 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71, 2163 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A, 2164 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061, 2165 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A, 2166 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6, 2167 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A, 2168 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6, 2169 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358, 2170 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6, 2171 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9, 2172 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379, 2173 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6, 2174 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C, 2175 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166, 2176 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B, 2177 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A, 2178 0xBE3A, 2179}; 2180 2181/* 2182 * Mini sample rate converter code image 2183 * that is to be loaded at 0x400 on the DSP. 2184 */ 2185static const u16 assp_minisrc_image[] = { 2186 2187 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412, 2188 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41, 2189 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907, 2190 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01, 2191 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904, 2192 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D, 2193 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD, 2194 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22, 2195 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0, 2196 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9, 2197 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89, 2198 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0, 2199 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484, 2200 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80, 2201 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624, 2202 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4, 2203 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027, 2204 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903, 2205 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809, 2206 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46, 2207 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47, 2208 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0, 2209 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516, 2210 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E, 2211 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C, 2212 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180, 2213 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E, 2214 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0, 2215 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0, 2216 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0, 2217 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F, 2218 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 2219 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 2220}; 2221 2222static const struct firmware assp_kernel = { 2223 .data = (u8 *)assp_kernel_image, 2224 .size = sizeof assp_kernel_image 2225}; 2226static const struct firmware assp_minisrc = { 2227 .data = (u8 *)assp_minisrc_image, 2228 .size = sizeof assp_minisrc_image 2229}; 2230 2231#else /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */ 2232 2233#ifdef __LITTLE_ENDIAN 2234static inline void snd_m3_convert_from_le(const struct firmware *fw) { } 2235#else 2236static void snd_m3_convert_from_le(const struct firmware *fw) 2237{ 2238 int i; 2239 u16 *data = (u16 *)fw->data; 2240 2241 for (i = 0; i < fw->size / 2; ++i) 2242 le16_to_cpus(&data[i]); 2243} 2244#endif 2245 2246#endif /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */ 2247 2248 2249/* 2250 * initialize ASSP 2251 */ 2252 2253#define MINISRC_LPF_LEN 10 2254static const u16 minisrc_lpf[MINISRC_LPF_LEN] = { 2255 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, 2256 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F 2257}; 2258 2259static void snd_m3_assp_init(struct snd_m3 *chip) 2260{ 2261 unsigned int i; 2262 u16 *data; 2263 2264 /* zero kernel data */ 2265 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) 2266 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2267 KDATA_BASE_ADDR + i, 0); 2268 2269 /* zero mixer data? */ 2270 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) 2271 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2272 KDATA_BASE_ADDR2 + i, 0); 2273 2274 /* init dma pointer */ 2275 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2276 KDATA_CURRENT_DMA, 2277 KDATA_DMA_XFER0); 2278 2279 /* write kernel into code memory.. */ 2280 data = (u16 *)chip->assp_kernel_image->data; 2281 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) { 2282 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2283 REV_B_CODE_MEMORY_BEGIN + i, data[i]); 2284 } 2285 2286 /* 2287 * We only have this one client and we know that 0x400 2288 * is free in our kernel's mem map, so lets just 2289 * drop it there. It seems that the minisrc doesn't 2290 * need vectors, so we won't bother with them.. 2291 */ 2292 data = (u16 *)chip->assp_minisrc_image->data; 2293 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) { 2294 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2295 0x400 + i, data[i]); 2296 } 2297 2298 /* 2299 * write the coefficients for the low pass filter? 2300 */ 2301 for (i = 0; i < MINISRC_LPF_LEN ; i++) { 2302 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2303 0x400 + MINISRC_COEF_LOC + i, 2304 minisrc_lpf[i]); 2305 } 2306 2307 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2308 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, 2309 0x8000); 2310 2311 /* 2312 * the minisrc is the only thing on 2313 * our task list.. 2314 */ 2315 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2316 KDATA_TASK0, 2317 0x400); 2318 2319 /* 2320 * init the mixer number.. 2321 */ 2322 2323 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2324 KDATA_MIXER_TASK_NUMBER,0); 2325 2326 /* 2327 * EXTREME KERNEL MASTER VOLUME 2328 */ 2329 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2330 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); 2331 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2332 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); 2333 2334 chip->mixer_list.curlen = 0; 2335 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0; 2336 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS; 2337 chip->adc1_list.curlen = 0; 2338 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0; 2339 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS; 2340 chip->dma_list.curlen = 0; 2341 chip->dma_list.mem_addr = KDATA_DMA_XFER0; 2342 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS; 2343 chip->msrc_list.curlen = 0; 2344 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC; 2345 chip->msrc_list.max = MAX_INSTANCE_MINISRC; 2346} 2347 2348 2349static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index) 2350{ 2351 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + 2352 MINISRC_IN_BUFFER_SIZE / 2 + 2353 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 ); 2354 int address, i; 2355 2356 /* 2357 * the revb memory map has 0x1100 through 0x1c00 2358 * free. 2359 */ 2360 2361 /* 2362 * align instance address to 256 bytes so that its 2363 * shifted list address is aligned. 2364 * list address = (mem address >> 1) >> 7; 2365 */ 2366 data_bytes = ALIGN(data_bytes, 256); 2367 address = 0x1100 + ((data_bytes/2) * index); 2368 2369 if ((address + (data_bytes/2)) >= 0x1c00) { 2370 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n", 2371 data_bytes, index, address); 2372 return -ENOMEM; 2373 } 2374 2375 s->number = index; 2376 s->inst.code = 0x400; 2377 s->inst.data = address; 2378 2379 for (i = data_bytes / 2; i > 0; address++, i--) { 2380 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2381 address, 0); 2382 } 2383 2384 return 0; 2385} 2386 2387 2388/* 2389 * this works for the reference board, have to find 2390 * out about others 2391 * 2392 * this needs more magic for 4 speaker, but.. 2393 */ 2394static void 2395snd_m3_amp_enable(struct snd_m3 *chip, int enable) 2396{ 2397 int io = chip->iobase; 2398 u16 gpo, polarity; 2399 2400 if (! chip->external_amp) 2401 return; 2402 2403 polarity = enable ? 0 : 1; 2404 polarity = polarity << chip->amp_gpio; 2405 gpo = 1 << chip->amp_gpio; 2406 2407 outw(~gpo, io + GPIO_MASK); 2408 2409 outw(inw(io + GPIO_DIRECTION) | gpo, 2410 io + GPIO_DIRECTION); 2411 2412 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity), 2413 io + GPIO_DATA); 2414 2415 outw(0xffff, io + GPIO_MASK); 2416} 2417 2418static int 2419snd_m3_chip_init(struct snd_m3 *chip) 2420{ 2421 struct pci_dev *pcidev = chip->pci; 2422 unsigned long io = chip->iobase; 2423 u32 n; 2424 u16 w; 2425 u8 t; /* makes as much sense as 'n', no? */ 2426 2427 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w); 2428 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE| 2429 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO| 2430 DISABLE_LEGACY); 2431 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w); 2432 2433 if (chip->is_omnibook) { 2434 /* 2435 * Volume buttons on some HP OmniBook laptops don't work 2436 * correctly. This makes them work for the most part. 2437 * 2438 * Volume up and down buttons on the laptop side work. 2439 * Fn+cursor_up (volme up) works. 2440 * Fn+cursor_down (volume down) doesn't work. 2441 * Fn+F7 (mute) works acts as volume up. 2442 */ 2443 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK); 2444 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION); 2445 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA); 2446 outw(0xffff, io + GPIO_MASK); 2447 } 2448 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); 2449 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD); 2450 n |= chip->hv_config; 2451 /* For some reason we must always use reduced debounce. */ 2452 n |= REDUCED_DEBOUNCE; 2453 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 2454 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); 2455 2456 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B); 2457 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); 2458 n &= ~INT_CLK_SELECT; 2459 if (!chip->allegro_flag) { 2460 n &= ~INT_CLK_MULT_ENABLE; 2461 n |= INT_CLK_SRC_NOT_PCI; 2462 } 2463 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 ); 2464 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); 2465 2466 if (chip->allegro_flag) { 2467 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n); 2468 n |= IN_CLK_12MHZ_SELECT; 2469 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n); 2470 } 2471 2472 t = inb(chip->iobase + ASSP_CONTROL_A); 2473 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 2474 t |= ASSP_CLK_49MHZ_SELECT; 2475 t |= ASSP_0_WS_ENABLE; 2476 outb(t, chip->iobase + ASSP_CONTROL_A); 2477 2478 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */ 2479 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); 2480 2481 outb(0x00, io + HARDWARE_VOL_CTRL); 2482 outb(0x88, io + SHADOW_MIX_REG_VOICE); 2483 outb(0x88, io + HW_VOL_COUNTER_VOICE); 2484 outb(0x88, io + SHADOW_MIX_REG_MASTER); 2485 outb(0x88, io + HW_VOL_COUNTER_MASTER); 2486 2487 return 0; 2488} 2489 2490static void 2491snd_m3_enable_ints(struct snd_m3 *chip) 2492{ 2493 unsigned long io = chip->iobase; 2494 unsigned short val; 2495 2496 /* TODO: MPU401 not supported yet */ 2497 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/; 2498 if (chip->hv_config & HV_CTRL_ENABLE) 2499 val |= HV_INT_ENABLE; 2500 outw(val, io + HOST_INT_CTRL); 2501 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, 2502 io + ASSP_CONTROL_C); 2503} 2504 2505 2506/* 2507 */ 2508 2509static int snd_m3_free(struct snd_m3 *chip) 2510{ 2511 struct m3_dma *s; 2512 int i; 2513 2514 if (chip->substreams) { 2515 spin_lock_irq(&chip->reg_lock); 2516 for (i = 0; i < chip->num_substreams; i++) { 2517 s = &chip->substreams[i]; 2518 /* check surviving pcms; this should not happen though.. */ 2519 if (s->substream && s->running) 2520 snd_m3_pcm_stop(chip, s, s->substream); 2521 } 2522 spin_unlock_irq(&chip->reg_lock); 2523 kfree(chip->substreams); 2524 } 2525 if (chip->iobase) { 2526 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */ 2527 } 2528 2529#ifdef CONFIG_PM 2530 vfree(chip->suspend_mem); 2531#endif 2532 2533 if (chip->irq >= 0) { 2534 synchronize_irq(chip->irq); 2535 free_irq(chip->irq, chip); 2536 } 2537 2538 if (chip->iobase) 2539 pci_release_regions(chip->pci); 2540 2541#ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL 2542 release_firmware(chip->assp_kernel_image); 2543 release_firmware(chip->assp_minisrc_image); 2544#endif 2545 2546 pci_disable_device(chip->pci); 2547 kfree(chip); 2548 return 0; 2549} 2550 2551 2552/* 2553 * APM support 2554 */ 2555#ifdef CONFIG_PM 2556static int m3_suspend(struct pci_dev *pci, pm_message_t state) 2557{ 2558 struct snd_card *card = pci_get_drvdata(pci); 2559 struct snd_m3 *chip = card->private_data; 2560 int i, index; 2561 2562 if (chip->suspend_mem == NULL) 2563 return 0; 2564 2565 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2566 snd_pcm_suspend_all(chip->pcm); 2567 snd_ac97_suspend(chip->ac97); 2568 2569 msleep(10); /* give the assp a chance to idle.. */ 2570 2571 snd_m3_assp_halt(chip); 2572 2573 /* save dsp image */ 2574 index = 0; 2575 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 2576 chip->suspend_mem[index++] = 2577 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i); 2578 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) 2579 chip->suspend_mem[index++] = 2580 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i); 2581 2582 pci_disable_device(pci); 2583 pci_save_state(pci); 2584 pci_set_power_state(pci, pci_choose_state(pci, state)); 2585 return 0; 2586} 2587 2588static int m3_resume(struct pci_dev *pci) 2589{ 2590 struct snd_card *card = pci_get_drvdata(pci); 2591 struct snd_m3 *chip = card->private_data; 2592 int i, index; 2593 2594 if (chip->suspend_mem == NULL) 2595 return 0; 2596 2597 pci_set_power_state(pci, PCI_D0); 2598 pci_restore_state(pci); 2599 if (pci_enable_device(pci) < 0) { 2600 printk(KERN_ERR "maestor3: pci_enable_device failed, " 2601 "disabling device\n"); 2602 snd_card_disconnect(card); 2603 return -EIO; 2604 } 2605 pci_set_master(pci); 2606 2607 /* first lets just bring everything back. .*/ 2608 snd_m3_outw(chip, 0, 0x54); 2609 snd_m3_outw(chip, 0, 0x56); 2610 2611 snd_m3_chip_init(chip); 2612 snd_m3_assp_halt(chip); 2613 snd_m3_ac97_reset(chip); 2614 2615 /* restore dsp image */ 2616 index = 0; 2617 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 2618 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, 2619 chip->suspend_mem[index++]); 2620 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) 2621 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, 2622 chip->suspend_mem[index++]); 2623 2624 /* tell the dma engine to restart itself */ 2625 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2626 KDATA_DMA_ACTIVE, 0); 2627 2628 /* restore ac97 registers */ 2629 snd_ac97_resume(chip->ac97); 2630 2631 snd_m3_assp_continue(chip); 2632 snd_m3_enable_ints(chip); 2633 snd_m3_amp_enable(chip, 1); 2634 2635 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2636 return 0; 2637} 2638#endif /* CONFIG_PM */ 2639 2640 2641/* 2642 */ 2643 2644static int snd_m3_dev_free(struct snd_device *device) 2645{ 2646 struct snd_m3 *chip = device->device_data; 2647 return snd_m3_free(chip); 2648} 2649 2650static int __devinit 2651snd_m3_create(struct snd_card *card, struct pci_dev *pci, 2652 int enable_amp, 2653 int amp_gpio, 2654 struct snd_m3 **chip_ret) 2655{ 2656 struct snd_m3 *chip; 2657 int i, err; 2658 const struct snd_pci_quirk *quirk; 2659 static struct snd_device_ops ops = { 2660 .dev_free = snd_m3_dev_free, 2661 }; 2662 2663 *chip_ret = NULL; 2664 2665 if (pci_enable_device(pci)) 2666 return -EIO; 2667 2668 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2669 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 || 2670 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) { 2671 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n"); 2672 pci_disable_device(pci); 2673 return -ENXIO; 2674 } 2675 2676 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2677 if (chip == NULL) { 2678 pci_disable_device(pci); 2679 return -ENOMEM; 2680 } 2681 2682 spin_lock_init(&chip->reg_lock); 2683 spin_lock_init(&chip->ac97_lock); 2684 2685 switch (pci->device) { 2686 case PCI_DEVICE_ID_ESS_ALLEGRO: 2687 case PCI_DEVICE_ID_ESS_ALLEGRO_1: 2688 case PCI_DEVICE_ID_ESS_CANYON3D_2LE: 2689 case PCI_DEVICE_ID_ESS_CANYON3D_2: 2690 chip->allegro_flag = 1; 2691 break; 2692 } 2693 2694 chip->card = card; 2695 chip->pci = pci; 2696 chip->irq = -1; 2697 2698 chip->external_amp = enable_amp; 2699 if (amp_gpio >= 0 && amp_gpio <= 0x0f) 2700 chip->amp_gpio = amp_gpio; 2701 else { 2702 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list); 2703 if (quirk) { 2704 snd_printdd(KERN_INFO "maestro3: set amp-gpio " 2705 "for '%s'\n", quirk->name); 2706 chip->amp_gpio = quirk->value; 2707 } else if (chip->allegro_flag) 2708 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO; 2709 else /* presumably this is for all 'maestro3's.. */ 2710 chip->amp_gpio = GPO_EXT_AMP_M3; 2711 } 2712 2713 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list); 2714 if (quirk) { 2715 snd_printdd(KERN_INFO "maestro3: enabled irda workaround " 2716 "for '%s'\n", quirk->name); 2717 chip->irda_workaround = 1; 2718 } 2719 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list); 2720 if (quirk) 2721 chip->hv_config = quirk->value; 2722 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list)) 2723 chip->is_omnibook = 1; 2724 2725 chip->num_substreams = NR_DSPS; 2726 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma), 2727 GFP_KERNEL); 2728 if (chip->substreams == NULL) { 2729 kfree(chip); 2730 pci_disable_device(pci); 2731 return -ENOMEM; 2732 } 2733 2734#ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL 2735 chip->assp_kernel_image = &assp_kernel; 2736#else 2737 err = request_firmware(&chip->assp_kernel_image, 2738 "ess/maestro3_assp_kernel.fw", &pci->dev); 2739 if (err < 0) { 2740 snd_m3_free(chip); 2741 return err; 2742 } else 2743 snd_m3_convert_from_le(chip->assp_kernel_image); 2744#endif 2745 2746#ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL 2747 chip->assp_minisrc_image = &assp_minisrc; 2748#else 2749 err = request_firmware(&chip->assp_minisrc_image, 2750 "ess/maestro3_assp_minisrc.fw", &pci->dev); 2751 if (err < 0) { 2752 snd_m3_free(chip); 2753 return err; 2754 } else 2755 snd_m3_convert_from_le(chip->assp_minisrc_image); 2756#endif 2757 2758 if ((err = pci_request_regions(pci, card->driver)) < 0) { 2759 snd_m3_free(chip); 2760 return err; 2761 } 2762 chip->iobase = pci_resource_start(pci, 0); 2763 2764 /* just to be sure */ 2765 pci_set_master(pci); 2766 2767 snd_m3_chip_init(chip); 2768 snd_m3_assp_halt(chip); 2769 2770 snd_m3_ac97_reset(chip); 2771 2772 snd_m3_amp_enable(chip, 1); 2773 2774 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip); 2775 2776 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED, 2777 card->driver, chip)) { 2778 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2779 snd_m3_free(chip); 2780 return -ENOMEM; 2781 } 2782 chip->irq = pci->irq; 2783 2784#ifdef CONFIG_PM 2785 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH)); 2786 if (chip->suspend_mem == NULL) 2787 snd_printk(KERN_WARNING "can't allocate apm buffer\n"); 2788#endif 2789 2790 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2791 snd_m3_free(chip); 2792 return err; 2793 } 2794 2795 if ((err = snd_m3_mixer(chip)) < 0) 2796 return err; 2797 2798 for (i = 0; i < chip->num_substreams; i++) { 2799 struct m3_dma *s = &chip->substreams[i]; 2800 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0) 2801 return err; 2802 } 2803 2804 if ((err = snd_m3_pcm(chip, 0)) < 0) 2805 return err; 2806 2807 snd_m3_enable_ints(chip); 2808 snd_m3_assp_continue(chip); 2809 2810 snd_card_set_dev(card, &pci->dev); 2811 2812 *chip_ret = chip; 2813 2814 return 0; 2815} 2816 2817/* 2818 */ 2819static int __devinit 2820snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2821{ 2822 static int dev; 2823 struct snd_card *card; 2824 struct snd_m3 *chip; 2825 int err; 2826 2827 /* don't pick up modems */ 2828 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) 2829 return -ENODEV; 2830 2831 if (dev >= SNDRV_CARDS) 2832 return -ENODEV; 2833 if (!enable[dev]) { 2834 dev++; 2835 return -ENOENT; 2836 } 2837 2838 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2839 if (card == NULL) 2840 return -ENOMEM; 2841 2842 switch (pci->device) { 2843 case PCI_DEVICE_ID_ESS_ALLEGRO: 2844 case PCI_DEVICE_ID_ESS_ALLEGRO_1: 2845 strcpy(card->driver, "Allegro"); 2846 break; 2847 case PCI_DEVICE_ID_ESS_CANYON3D_2LE: 2848 case PCI_DEVICE_ID_ESS_CANYON3D_2: 2849 strcpy(card->driver, "Canyon3D-2"); 2850 break; 2851 default: 2852 strcpy(card->driver, "Maestro3"); 2853 break; 2854 } 2855 2856 if ((err = snd_m3_create(card, pci, 2857 external_amp[dev], 2858 amp_gpio[dev], 2859 &chip)) < 0) { 2860 snd_card_free(card); 2861 return err; 2862 } 2863 card->private_data = chip; 2864 2865 sprintf(card->shortname, "ESS %s PCI", card->driver); 2866 sprintf(card->longname, "%s at 0x%lx, irq %d", 2867 card->shortname, chip->iobase, chip->irq); 2868 2869 if ((err = snd_card_register(card)) < 0) { 2870 snd_card_free(card); 2871 return err; 2872 } 2873 2874 2875 pci_set_drvdata(pci, card); 2876 dev++; 2877 return 0; 2878} 2879 2880static void __devexit snd_m3_remove(struct pci_dev *pci) 2881{ 2882 snd_card_free(pci_get_drvdata(pci)); 2883 pci_set_drvdata(pci, NULL); 2884} 2885 2886static struct pci_driver driver = { 2887 .name = "Maestro3", 2888 .id_table = snd_m3_ids, 2889 .probe = snd_m3_probe, 2890 .remove = __devexit_p(snd_m3_remove), 2891#ifdef CONFIG_PM 2892 .suspend = m3_suspend, 2893 .resume = m3_resume, 2894#endif 2895}; 2896 2897static int __init alsa_card_m3_init(void) 2898{ 2899 return pci_register_driver(&driver); 2900} 2901 2902static void __exit alsa_card_m3_exit(void) 2903{ 2904 pci_unregister_driver(&driver); 2905} 2906 2907module_init(alsa_card_m3_init) 2908module_exit(alsa_card_m3_exit) 2909