1/* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio. 4 * 5 * Copyright(c) 2004 Intel Corporation. All rights reserved. 6 * 7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 8 * PeiSen Hou <pshou@realtek.com.tw> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the Free 12 * Software Foundation; either version 2 of the License, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along with 21 * this program; if not, write to the Free Software Foundation, Inc., 59 22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 23 * 24 * CONTACTS: 25 * 26 * Matt Jared matt.jared@intel.com 27 * Andy Kopp andy.kopp@intel.com 28 * Dan Kogan dan.d.kogan@intel.com 29 * 30 * CHANGES: 31 * 32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 33 * 34 */ 35 36#include <sound/driver.h> 37#include <asm/io.h> 38#include <linux/delay.h> 39#include <linux/interrupt.h> 40#include <linux/kernel.h> 41#include <linux/module.h> 42#include <linux/moduleparam.h> 43#include <linux/init.h> 44#include <linux/slab.h> 45#include <linux/pci.h> 46#include <linux/mutex.h> 47#include <sound/core.h> 48#include <sound/initval.h> 49#include "hda_codec.h" 50 51 52static int index = SNDRV_DEFAULT_IDX1; 53static char *id = SNDRV_DEFAULT_STR1; 54static char *model; 55static int position_fix; 56static int probe_mask = -1; 57static int single_cmd; 58static int enable_msi; 59 60module_param(index, int, 0444); 61MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 62module_param(id, charp, 0444); 63MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 64module_param(model, charp, 0444); 65MODULE_PARM_DESC(model, "Use the given board model."); 66module_param(position_fix, int, 0444); 67MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size)."); 68module_param(probe_mask, int, 0444); 69MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 70module_param(single_cmd, bool, 0444); 71MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only)."); 72module_param(enable_msi, int, 0); 73MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 74 75 76/* just for backward compatibility */ 77static int enable; 78module_param(enable, bool, 0444); 79 80MODULE_LICENSE("GPL"); 81MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 82 "{Intel, ICH6M}," 83 "{Intel, ICH7}," 84 "{Intel, ESB2}," 85 "{Intel, ICH8}," 86 "{Intel, ICH9}," 87 "{ATI, SB450}," 88 "{ATI, SB600}," 89 "{ATI, RS600}," 90 "{ATI, RS690}," 91 "{ATI, RS780}," 92 "{ATI, R600}," 93 "{VIA, VT8251}," 94 "{VIA, VT8237A}," 95 "{SiS, SIS966}," 96 "{ULI, M5461}}"); 97MODULE_DESCRIPTION("Intel HDA driver"); 98 99#define SFX "hda-intel: " 100 101/* 102 * registers 103 */ 104#define ICH6_REG_GCAP 0x00 105#define ICH6_REG_VMIN 0x02 106#define ICH6_REG_VMAJ 0x03 107#define ICH6_REG_OUTPAY 0x04 108#define ICH6_REG_INPAY 0x06 109#define ICH6_REG_GCTL 0x08 110#define ICH6_REG_WAKEEN 0x0c 111#define ICH6_REG_STATESTS 0x0e 112#define ICH6_REG_GSTS 0x10 113#define ICH6_REG_INTCTL 0x20 114#define ICH6_REG_INTSTS 0x24 115#define ICH6_REG_WALCLK 0x30 116#define ICH6_REG_SYNC 0x34 117#define ICH6_REG_CORBLBASE 0x40 118#define ICH6_REG_CORBUBASE 0x44 119#define ICH6_REG_CORBWP 0x48 120#define ICH6_REG_CORBRP 0x4A 121#define ICH6_REG_CORBCTL 0x4c 122#define ICH6_REG_CORBSTS 0x4d 123#define ICH6_REG_CORBSIZE 0x4e 124 125#define ICH6_REG_RIRBLBASE 0x50 126#define ICH6_REG_RIRBUBASE 0x54 127#define ICH6_REG_RIRBWP 0x58 128#define ICH6_REG_RINTCNT 0x5a 129#define ICH6_REG_RIRBCTL 0x5c 130#define ICH6_REG_RIRBSTS 0x5d 131#define ICH6_REG_RIRBSIZE 0x5e 132 133#define ICH6_REG_IC 0x60 134#define ICH6_REG_IR 0x64 135#define ICH6_REG_IRS 0x68 136#define ICH6_IRS_VALID (1<<1) 137#define ICH6_IRS_BUSY (1<<0) 138 139#define ICH6_REG_DPLBASE 0x70 140#define ICH6_REG_DPUBASE 0x74 141#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 142 143/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 144enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 145 146/* stream register offsets from stream base */ 147#define ICH6_REG_SD_CTL 0x00 148#define ICH6_REG_SD_STS 0x03 149#define ICH6_REG_SD_LPIB 0x04 150#define ICH6_REG_SD_CBL 0x08 151#define ICH6_REG_SD_LVI 0x0c 152#define ICH6_REG_SD_FIFOW 0x0e 153#define ICH6_REG_SD_FIFOSIZE 0x10 154#define ICH6_REG_SD_FORMAT 0x12 155#define ICH6_REG_SD_BDLPL 0x18 156#define ICH6_REG_SD_BDLPU 0x1c 157 158/* PCI space */ 159#define ICH6_PCIREG_TCSEL 0x44 160 161/* 162 * other constants 163 */ 164 165/* max number of SDs */ 166/* ICH, ATI and VIA have 4 playback and 4 capture */ 167#define ICH6_CAPTURE_INDEX 0 168#define ICH6_NUM_CAPTURE 4 169#define ICH6_PLAYBACK_INDEX 4 170#define ICH6_NUM_PLAYBACK 4 171 172/* ULI has 6 playback and 5 capture */ 173#define ULI_CAPTURE_INDEX 0 174#define ULI_NUM_CAPTURE 5 175#define ULI_PLAYBACK_INDEX 5 176#define ULI_NUM_PLAYBACK 6 177 178/* ATI HDMI has 1 playback and 0 capture */ 179#define ATIHDMI_CAPTURE_INDEX 0 180#define ATIHDMI_NUM_CAPTURE 0 181#define ATIHDMI_PLAYBACK_INDEX 0 182#define ATIHDMI_NUM_PLAYBACK 1 183 184/* this number is statically defined for simplicity */ 185#define MAX_AZX_DEV 16 186 187/* max number of fragments - we may use more if allocating more pages for BDL */ 188#define BDL_SIZE PAGE_ALIGN(8192) 189#define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16)) 190/* max buffer size - no h/w limit, you can increase as you like */ 191#define AZX_MAX_BUF_SIZE (1024*1024*1024) 192/* max number of PCM devics per card */ 193#define AZX_MAX_AUDIO_PCMS 6 194#define AZX_MAX_MODEM_PCMS 2 195#define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS) 196 197/* RIRB int mask: overrun[2], response[0] */ 198#define RIRB_INT_RESPONSE 0x01 199#define RIRB_INT_OVERRUN 0x04 200#define RIRB_INT_MASK 0x05 201 202/* STATESTS int mask: SD2,SD1,SD0 */ 203#define AZX_MAX_CODECS 3 204#define STATESTS_INT_MASK 0x07 205 206/* SD_CTL bits */ 207#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 208#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 209#define SD_CTL_STREAM_TAG_MASK (0xf << 20) 210#define SD_CTL_STREAM_TAG_SHIFT 20 211 212/* SD_CTL and SD_STS */ 213#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 214#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 215#define SD_INT_COMPLETE 0x04 /* completion interrupt */ 216#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE) 217 218/* SD_STS */ 219#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 220 221/* INTCTL and INTSTS */ 222#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 223#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 224#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 225 226/* GCTL unsolicited response enable bit */ 227#define ICH6_GCTL_UREN (1<<8) 228 229/* GCTL reset bit */ 230#define ICH6_GCTL_RESET (1<<0) 231 232/* CORB/RIRB control, read/write pointer */ 233#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ 234#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ 235#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ 236/* below are so far hardcoded - should read registers in future */ 237#define ICH6_MAX_CORB_ENTRIES 256 238#define ICH6_MAX_RIRB_ENTRIES 256 239 240/* position fix mode */ 241enum { 242 POS_FIX_AUTO, 243 POS_FIX_NONE, 244 POS_FIX_POSBUF, 245 POS_FIX_FIFO, 246}; 247 248/* Defines for ATI HD Audio support in SB450 south bridge */ 249#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 250#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 251 252/* Defines for Nvidia HDA support */ 253#define NVIDIA_HDA_TRANSREG_ADDR 0x4e 254#define NVIDIA_HDA_ENABLE_COHBITS 0x0f 255 256/* 257 */ 258 259struct azx_dev { 260 u32 *bdl; /* virtual address of the BDL */ 261 dma_addr_t bdl_addr; /* physical address of the BDL */ 262 u32 *posbuf; /* position buffer pointer */ 263 264 unsigned int bufsize; /* size of the play buffer in bytes */ 265 unsigned int fragsize; /* size of each period in bytes */ 266 unsigned int frags; /* number for period in the play buffer */ 267 unsigned int fifo_size; /* FIFO size */ 268 269 void __iomem *sd_addr; /* stream descriptor pointer */ 270 271 u32 sd_int_sta_mask; /* stream int status mask */ 272 273 /* pcm support */ 274 struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */ 275 unsigned int format_val; /* format value to be set in the controller and the codec */ 276 unsigned char stream_tag; /* assigned stream */ 277 unsigned char index; /* stream index */ 278 /* for sanity check of position buffer */ 279 unsigned int period_intr; 280 281 unsigned int opened :1; 282 unsigned int running :1; 283}; 284 285/* CORB/RIRB */ 286struct azx_rb { 287 u32 *buf; /* CORB/RIRB buffer 288 * Each CORB entry is 4byte, RIRB is 8byte 289 */ 290 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 291 /* for RIRB */ 292 unsigned short rp, wp; /* read/write pointers */ 293 int cmds; /* number of pending requests */ 294 u32 res; /* last read value */ 295}; 296 297struct azx { 298 struct snd_card *card; 299 struct pci_dev *pci; 300 301 /* chip type specific */ 302 int driver_type; 303 int playback_streams; 304 int playback_index_offset; 305 int capture_streams; 306 int capture_index_offset; 307 int num_streams; 308 309 /* pci resources */ 310 unsigned long addr; 311 void __iomem *remap_addr; 312 int irq; 313 314 /* locks */ 315 spinlock_t reg_lock; 316 struct mutex open_mutex; 317 318 /* streams (x num_streams) */ 319 struct azx_dev *azx_dev; 320 321 /* PCM */ 322 unsigned int pcm_devs; 323 struct snd_pcm *pcm[AZX_MAX_PCMS]; 324 325 /* HD codec */ 326 unsigned short codec_mask; 327 struct hda_bus *bus; 328 329 /* CORB/RIRB */ 330 struct azx_rb corb; 331 struct azx_rb rirb; 332 333 /* BDL, CORB/RIRB and position buffers */ 334 struct snd_dma_buffer bdl; 335 struct snd_dma_buffer rb; 336 struct snd_dma_buffer posbuf; 337 338 /* flags */ 339 int position_fix; 340 unsigned int initialized :1; 341 unsigned int single_cmd :1; 342 unsigned int polling_mode :1; 343 unsigned int msi :1; 344}; 345 346/* driver types */ 347enum { 348 AZX_DRIVER_ICH, 349 AZX_DRIVER_ATI, 350 AZX_DRIVER_ATIHDMI, 351 AZX_DRIVER_VIA, 352 AZX_DRIVER_SIS, 353 AZX_DRIVER_ULI, 354 AZX_DRIVER_NVIDIA, 355}; 356 357static char *driver_short_names[] __devinitdata = { 358 [AZX_DRIVER_ICH] = "HDA Intel", 359 [AZX_DRIVER_ATI] = "HDA ATI SB", 360 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 361 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 362 [AZX_DRIVER_SIS] = "HDA SIS966", 363 [AZX_DRIVER_ULI] = "HDA ULI M5461", 364 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 365}; 366 367/* 368 * macros for easy use 369 */ 370#define azx_writel(chip,reg,value) \ 371 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 372#define azx_readl(chip,reg) \ 373 readl((chip)->remap_addr + ICH6_REG_##reg) 374#define azx_writew(chip,reg,value) \ 375 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 376#define azx_readw(chip,reg) \ 377 readw((chip)->remap_addr + ICH6_REG_##reg) 378#define azx_writeb(chip,reg,value) \ 379 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 380#define azx_readb(chip,reg) \ 381 readb((chip)->remap_addr + ICH6_REG_##reg) 382 383#define azx_sd_writel(dev,reg,value) \ 384 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 385#define azx_sd_readl(dev,reg) \ 386 readl((dev)->sd_addr + ICH6_REG_##reg) 387#define azx_sd_writew(dev,reg,value) \ 388 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 389#define azx_sd_readw(dev,reg) \ 390 readw((dev)->sd_addr + ICH6_REG_##reg) 391#define azx_sd_writeb(dev,reg,value) \ 392 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 393#define azx_sd_readb(dev,reg) \ 394 readb((dev)->sd_addr + ICH6_REG_##reg) 395 396/* for pcm support */ 397#define get_azx_dev(substream) (substream->runtime->private_data) 398 399/* Get the upper 32bit of the given dma_addr_t 400 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit 401 */ 402#define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0) 403 404static int azx_acquire_irq(struct azx *chip, int do_disconnect); 405 406/* 407 * Interface for HD codec 408 */ 409 410/* 411 * CORB / RIRB interface 412 */ 413static int azx_alloc_cmd_io(struct azx *chip) 414{ 415 int err; 416 417 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 418 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 419 PAGE_SIZE, &chip->rb); 420 if (err < 0) { 421 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); 422 return err; 423 } 424 return 0; 425} 426 427static void azx_init_cmd_io(struct azx *chip) 428{ 429 /* CORB set up */ 430 chip->corb.addr = chip->rb.addr; 431 chip->corb.buf = (u32 *)chip->rb.area; 432 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 433 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr)); 434 435 /* set the corb size to 256 entries (ULI requires explicitly) */ 436 azx_writeb(chip, CORBSIZE, 0x02); 437 /* set the corb write pointer to 0 */ 438 azx_writew(chip, CORBWP, 0); 439 /* reset the corb hw read pointer */ 440 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); 441 /* enable corb dma */ 442 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); 443 444 /* RIRB set up */ 445 chip->rirb.addr = chip->rb.addr + 2048; 446 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 447 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 448 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr)); 449 450 /* set the rirb size to 256 entries (ULI requires explicitly) */ 451 azx_writeb(chip, RIRBSIZE, 0x02); 452 /* reset the rirb hw write pointer */ 453 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); 454 /* set N=1, get RIRB response interrupt for new entry */ 455 azx_writew(chip, RINTCNT, 1); 456 /* enable rirb dma and response irq */ 457 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 458 chip->rirb.rp = chip->rirb.cmds = 0; 459} 460 461static void azx_free_cmd_io(struct azx *chip) 462{ 463 /* disable ringbuffer DMAs */ 464 azx_writeb(chip, RIRBCTL, 0); 465 azx_writeb(chip, CORBCTL, 0); 466} 467 468/* send a command */ 469static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, 470 unsigned int verb, unsigned int para) 471{ 472 struct azx *chip = codec->bus->private_data; 473 unsigned int wp; 474 u32 val; 475 476 val = (u32)(codec->addr & 0x0f) << 28; 477 val |= (u32)direct << 27; 478 val |= (u32)nid << 20; 479 val |= verb << 8; 480 val |= para; 481 482 /* add command to corb */ 483 wp = azx_readb(chip, CORBWP); 484 wp++; 485 wp %= ICH6_MAX_CORB_ENTRIES; 486 487 spin_lock_irq(&chip->reg_lock); 488 chip->rirb.cmds++; 489 chip->corb.buf[wp] = cpu_to_le32(val); 490 azx_writel(chip, CORBWP, wp); 491 spin_unlock_irq(&chip->reg_lock); 492 493 return 0; 494} 495 496#define ICH6_RIRB_EX_UNSOL_EV (1<<4) 497 498/* retrieve RIRB entry - called from interrupt handler */ 499static void azx_update_rirb(struct azx *chip) 500{ 501 unsigned int rp, wp; 502 u32 res, res_ex; 503 504 wp = azx_readb(chip, RIRBWP); 505 if (wp == chip->rirb.wp) 506 return; 507 chip->rirb.wp = wp; 508 509 while (chip->rirb.rp != wp) { 510 chip->rirb.rp++; 511 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 512 513 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 514 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 515 res = le32_to_cpu(chip->rirb.buf[rp]); 516 if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 517 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 518 else if (chip->rirb.cmds) { 519 chip->rirb.cmds--; 520 chip->rirb.res = res; 521 } 522 } 523} 524 525/* receive a response */ 526static unsigned int azx_rirb_get_response(struct hda_codec *codec) 527{ 528 struct azx *chip = codec->bus->private_data; 529 unsigned long timeout; 530 531 again: 532 timeout = jiffies + msecs_to_jiffies(1000); 533 do { 534 if (chip->polling_mode) { 535 spin_lock_irq(&chip->reg_lock); 536 azx_update_rirb(chip); 537 spin_unlock_irq(&chip->reg_lock); 538 } 539 if (! chip->rirb.cmds) 540 return chip->rirb.res; /* the last value */ 541 schedule_timeout_interruptible(1); 542 } while (time_after_eq(timeout, jiffies)); 543 544 if (chip->msi) { 545 snd_printk(KERN_WARNING "hda_intel: No response from codec, " 546 "disabling MSI...\n"); 547 free_irq(chip->irq, chip); 548 chip->irq = -1; 549 pci_disable_msi(chip->pci); 550 chip->msi = 0; 551 if (azx_acquire_irq(chip, 1) < 0) 552 return -1; 553 goto again; 554 } 555 556 if (!chip->polling_mode) { 557 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, " 558 "switching to polling mode...\n"); 559 chip->polling_mode = 1; 560 goto again; 561 } 562 563 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 564 "switching to single_cmd mode...\n"); 565 chip->rirb.rp = azx_readb(chip, RIRBWP); 566 chip->rirb.cmds = 0; 567 /* switch to single_cmd mode */ 568 chip->single_cmd = 1; 569 azx_free_cmd_io(chip); 570 return -1; 571} 572 573/* 574 * Use the single immediate command instead of CORB/RIRB for simplicity 575 * 576 * Note: according to Intel, this is not preferred use. The command was 577 * intended for the BIOS only, and may get confused with unsolicited 578 * responses. So, we shouldn't use it for normal operation from the 579 * driver. 580 * I left the codes, however, for debugging/testing purposes. 581 */ 582 583/* send a command */ 584static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid, 585 int direct, unsigned int verb, 586 unsigned int para) 587{ 588 struct azx *chip = codec->bus->private_data; 589 u32 val; 590 int timeout = 50; 591 592 val = (u32)(codec->addr & 0x0f) << 28; 593 val |= (u32)direct << 27; 594 val |= (u32)nid << 20; 595 val |= verb << 8; 596 val |= para; 597 598 while (timeout--) { 599 /* check ICB busy bit */ 600 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) { 601 /* Clear IRV valid bit */ 602 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID); 603 azx_writel(chip, IC, val); 604 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY); 605 return 0; 606 } 607 udelay(1); 608 } 609 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val); 610 return -EIO; 611} 612 613/* receive a response */ 614static unsigned int azx_single_get_response(struct hda_codec *codec) 615{ 616 struct azx *chip = codec->bus->private_data; 617 int timeout = 50; 618 619 while (timeout--) { 620 /* check IRV busy bit */ 621 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) 622 return azx_readl(chip, IR); 623 udelay(1); 624 } 625 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS)); 626 return (unsigned int)-1; 627} 628 629/* 630 * The below are the main callbacks from hda_codec. 631 * 632 * They are just the skeleton to call sub-callbacks according to the 633 * current setting of chip->single_cmd. 634 */ 635 636/* send a command */ 637static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, 638 int direct, unsigned int verb, 639 unsigned int para) 640{ 641 struct azx *chip = codec->bus->private_data; 642 if (chip->single_cmd) 643 return azx_single_send_cmd(codec, nid, direct, verb, para); 644 else 645 return azx_corb_send_cmd(codec, nid, direct, verb, para); 646} 647 648/* get a response */ 649static unsigned int azx_get_response(struct hda_codec *codec) 650{ 651 struct azx *chip = codec->bus->private_data; 652 if (chip->single_cmd) 653 return azx_single_get_response(codec); 654 else 655 return azx_rirb_get_response(codec); 656} 657 658 659/* reset codec link */ 660static int azx_reset(struct azx *chip) 661{ 662 int count; 663 664 /* reset controller */ 665 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 666 667 count = 50; 668 while (azx_readb(chip, GCTL) && --count) 669 msleep(1); 670 671 /* delay for >= 100us for codec PLL to settle per spec 672 * Rev 0.9 section 5.5.1 673 */ 674 msleep(1); 675 676 /* Bring controller out of reset */ 677 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 678 679 count = 50; 680 while (!azx_readb(chip, GCTL) && --count) 681 msleep(1); 682 683 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 684 msleep(1); 685 686 /* check to see if controller is ready */ 687 if (!azx_readb(chip, GCTL)) { 688 snd_printd("azx_reset: controller not ready!\n"); 689 return -EBUSY; 690 } 691 692 /* Accept unsolicited responses */ 693 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN); 694 695 /* detect codecs */ 696 if (!chip->codec_mask) { 697 chip->codec_mask = azx_readw(chip, STATESTS); 698 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); 699 } 700 701 return 0; 702} 703 704 705/* 706 * Lowlevel interface 707 */ 708 709/* enable interrupts */ 710static void azx_int_enable(struct azx *chip) 711{ 712 /* enable controller CIE and GIE */ 713 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 714 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 715} 716 717/* disable interrupts */ 718static void azx_int_disable(struct azx *chip) 719{ 720 int i; 721 722 /* disable interrupts in stream descriptor */ 723 for (i = 0; i < chip->num_streams; i++) { 724 struct azx_dev *azx_dev = &chip->azx_dev[i]; 725 azx_sd_writeb(azx_dev, SD_CTL, 726 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 727 } 728 729 /* disable SIE for all streams */ 730 azx_writeb(chip, INTCTL, 0); 731 732 /* disable controller CIE and GIE */ 733 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 734 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 735} 736 737/* clear interrupts */ 738static void azx_int_clear(struct azx *chip) 739{ 740 int i; 741 742 /* clear stream status */ 743 for (i = 0; i < chip->num_streams; i++) { 744 struct azx_dev *azx_dev = &chip->azx_dev[i]; 745 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 746 } 747 748 /* clear STATESTS */ 749 azx_writeb(chip, STATESTS, STATESTS_INT_MASK); 750 751 /* clear rirb status */ 752 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 753 754 /* clear int status */ 755 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 756} 757 758/* start a stream */ 759static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 760{ 761 /* enable SIE */ 762 azx_writeb(chip, INTCTL, 763 azx_readb(chip, INTCTL) | (1 << azx_dev->index)); 764 /* set DMA start and interrupt mask */ 765 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 766 SD_CTL_DMA_START | SD_INT_MASK); 767} 768 769/* stop a stream */ 770static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 771{ 772 /* stop DMA */ 773 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 774 ~(SD_CTL_DMA_START | SD_INT_MASK)); 775 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 776 /* disable SIE */ 777 azx_writeb(chip, INTCTL, 778 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); 779} 780 781 782/* 783 * initialize the chip 784 */ 785static void azx_init_chip(struct azx *chip) 786{ 787 unsigned char reg; 788 789 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 790 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 791 * Ensuring these bits are 0 clears playback static on some HD Audio codecs 792 */ 793 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, ®); 794 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8); 795 796 /* reset controller */ 797 azx_reset(chip); 798 799 /* initialize interrupts */ 800 azx_int_clear(chip); 801 azx_int_enable(chip); 802 803 /* initialize the codec command I/O */ 804 if (!chip->single_cmd) 805 azx_init_cmd_io(chip); 806 807 /* program the position buffer */ 808 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 809 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr)); 810 811 switch (chip->driver_type) { 812 case AZX_DRIVER_ATI: 813 /* For ATI SB450 azalia HD audio, we need to enable snoop */ 814 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 815 ®); 816 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 817 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP); 818 break; 819 case AZX_DRIVER_NVIDIA: 820 /* For NVIDIA HDA, enable snoop */ 821 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, ®); 822 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, 823 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS); 824 break; 825 } 826} 827 828 829/* 830 * interrupt handler 831 */ 832static irqreturn_t azx_interrupt(int irq, void *dev_id) 833{ 834 struct azx *chip = dev_id; 835 struct azx_dev *azx_dev; 836 u32 status; 837 int i; 838 839 spin_lock(&chip->reg_lock); 840 841 status = azx_readl(chip, INTSTS); 842 if (status == 0) { 843 spin_unlock(&chip->reg_lock); 844 return IRQ_NONE; 845 } 846 847 for (i = 0; i < chip->num_streams; i++) { 848 azx_dev = &chip->azx_dev[i]; 849 if (status & azx_dev->sd_int_sta_mask) { 850 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 851 if (azx_dev->substream && azx_dev->running) { 852 azx_dev->period_intr++; 853 spin_unlock(&chip->reg_lock); 854 snd_pcm_period_elapsed(azx_dev->substream); 855 spin_lock(&chip->reg_lock); 856 } 857 } 858 } 859 860 /* clear rirb int */ 861 status = azx_readb(chip, RIRBSTS); 862 if (status & RIRB_INT_MASK) { 863 if (! chip->single_cmd && (status & RIRB_INT_RESPONSE)) 864 azx_update_rirb(chip); 865 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 866 } 867 868 spin_unlock(&chip->reg_lock); 869 870 return IRQ_HANDLED; 871} 872 873 874/* 875 * set up BDL entries 876 */ 877static void azx_setup_periods(struct azx_dev *azx_dev) 878{ 879 u32 *bdl = azx_dev->bdl; 880 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr; 881 int idx; 882 883 /* reset BDL address */ 884 azx_sd_writel(azx_dev, SD_BDLPL, 0); 885 azx_sd_writel(azx_dev, SD_BDLPU, 0); 886 887 /* program the initial BDL entries */ 888 for (idx = 0; idx < azx_dev->frags; idx++) { 889 unsigned int off = idx << 2; /* 4 dword step */ 890 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize; 891 /* program the address field of the BDL entry */ 892 bdl[off] = cpu_to_le32((u32)addr); 893 bdl[off+1] = cpu_to_le32(upper_32bit(addr)); 894 895 /* program the size field of the BDL entry */ 896 bdl[off+2] = cpu_to_le32(azx_dev->fragsize); 897 898 /* program the IOC to enable interrupt when buffer completes */ 899 bdl[off+3] = cpu_to_le32(0x01); 900 } 901} 902 903/* 904 * set up the SD for streaming 905 */ 906static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 907{ 908 unsigned char val; 909 int timeout; 910 911 /* make sure the run bit is zero for SD */ 912 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START); 913 /* reset stream */ 914 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET); 915 udelay(3); 916 timeout = 300; 917 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 918 --timeout) 919 ; 920 val &= ~SD_CTL_STREAM_RESET; 921 azx_sd_writeb(azx_dev, SD_CTL, val); 922 udelay(3); 923 924 timeout = 300; 925 /* waiting for hardware to report that the stream is out of reset */ 926 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 927 --timeout) 928 ; 929 930 /* program the stream_tag */ 931 azx_sd_writel(azx_dev, SD_CTL, 932 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) | 933 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); 934 935 /* program the length of samples in cyclic buffer */ 936 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 937 938 /* program the stream format */ 939 /* this value needs to be the same as the one programmed */ 940 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 941 942 /* program the stream LVI (last valid index) of the BDL */ 943 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 944 945 /* program the BDL address */ 946 /* lower BDL address */ 947 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr); 948 /* upper BDL address */ 949 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr)); 950 951 /* enable the position buffer */ 952 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 953 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 954 955 /* set the interrupt enable bits in the descriptor control register */ 956 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 957 958 return 0; 959} 960 961 962/* 963 * Codec initialization 964 */ 965 966static unsigned int azx_max_codecs[] __devinitdata = { 967 [AZX_DRIVER_ICH] = 3, 968 [AZX_DRIVER_ATI] = 4, 969 [AZX_DRIVER_ATIHDMI] = 4, 970 [AZX_DRIVER_VIA] = 3, 971 [AZX_DRIVER_SIS] = 3, 972 [AZX_DRIVER_ULI] = 3, 973 [AZX_DRIVER_NVIDIA] = 3, 974}; 975 976static int __devinit azx_codec_create(struct azx *chip, const char *model) 977{ 978 struct hda_bus_template bus_temp; 979 int c, codecs, audio_codecs, err; 980 981 memset(&bus_temp, 0, sizeof(bus_temp)); 982 bus_temp.private_data = chip; 983 bus_temp.modelname = model; 984 bus_temp.pci = chip->pci; 985 bus_temp.ops.command = azx_send_cmd; 986 bus_temp.ops.get_response = azx_get_response; 987 988 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0) 989 return err; 990 991 codecs = audio_codecs = 0; 992 for (c = 0; c < AZX_MAX_CODECS; c++) { 993 if ((chip->codec_mask & (1 << c)) & probe_mask) { 994 struct hda_codec *codec; 995 err = snd_hda_codec_new(chip->bus, c, &codec); 996 if (err < 0) 997 continue; 998 codecs++; 999 if (codec->afg) 1000 audio_codecs++; 1001 } 1002 } 1003 if (!audio_codecs) { 1004 /* probe additional slots if no codec is found */ 1005 for (; c < azx_max_codecs[chip->driver_type]; c++) { 1006 if ((chip->codec_mask & (1 << c)) & probe_mask) { 1007 err = snd_hda_codec_new(chip->bus, c, NULL); 1008 if (err < 0) 1009 continue; 1010 codecs++; 1011 } 1012 } 1013 } 1014 if (!codecs) { 1015 snd_printk(KERN_ERR SFX "no codecs initialized\n"); 1016 return -ENXIO; 1017 } 1018 1019 return 0; 1020} 1021 1022 1023/* 1024 * PCM support 1025 */ 1026 1027/* assign a stream for the PCM */ 1028static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream) 1029{ 1030 int dev, i, nums; 1031 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1032 dev = chip->playback_index_offset; 1033 nums = chip->playback_streams; 1034 } else { 1035 dev = chip->capture_index_offset; 1036 nums = chip->capture_streams; 1037 } 1038 for (i = 0; i < nums; i++, dev++) 1039 if (! chip->azx_dev[dev].opened) { 1040 chip->azx_dev[dev].opened = 1; 1041 return &chip->azx_dev[dev]; 1042 } 1043 return NULL; 1044} 1045 1046/* release the assigned stream */ 1047static inline void azx_release_device(struct azx_dev *azx_dev) 1048{ 1049 azx_dev->opened = 0; 1050} 1051 1052static struct snd_pcm_hardware azx_pcm_hw = { 1053 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1054 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1055 SNDRV_PCM_INFO_MMAP_VALID | 1056 /* No full-resume yet implemented */ 1057 /* SNDRV_PCM_INFO_RESUME |*/ 1058 SNDRV_PCM_INFO_PAUSE), 1059 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1060 .rates = SNDRV_PCM_RATE_48000, 1061 .rate_min = 48000, 1062 .rate_max = 48000, 1063 .channels_min = 2, 1064 .channels_max = 2, 1065 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1066 .period_bytes_min = 128, 1067 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1068 .periods_min = 2, 1069 .periods_max = AZX_MAX_FRAG, 1070 .fifo_size = 0, 1071}; 1072 1073struct azx_pcm { 1074 struct azx *chip; 1075 struct hda_codec *codec; 1076 struct hda_pcm_stream *hinfo[2]; 1077}; 1078 1079static int azx_pcm_open(struct snd_pcm_substream *substream) 1080{ 1081 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1082 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1083 struct azx *chip = apcm->chip; 1084 struct azx_dev *azx_dev; 1085 struct snd_pcm_runtime *runtime = substream->runtime; 1086 unsigned long flags; 1087 int err; 1088 1089 mutex_lock(&chip->open_mutex); 1090 azx_dev = azx_assign_device(chip, substream->stream); 1091 if (azx_dev == NULL) { 1092 mutex_unlock(&chip->open_mutex); 1093 return -EBUSY; 1094 } 1095 runtime->hw = azx_pcm_hw; 1096 runtime->hw.channels_min = hinfo->channels_min; 1097 runtime->hw.channels_max = hinfo->channels_max; 1098 runtime->hw.formats = hinfo->formats; 1099 runtime->hw.rates = hinfo->rates; 1100 snd_pcm_limit_hw_rates(runtime); 1101 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 1102 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1103 128); 1104 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1105 128); 1106 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { 1107 azx_release_device(azx_dev); 1108 mutex_unlock(&chip->open_mutex); 1109 return err; 1110 } 1111 spin_lock_irqsave(&chip->reg_lock, flags); 1112 azx_dev->substream = substream; 1113 azx_dev->running = 0; 1114 spin_unlock_irqrestore(&chip->reg_lock, flags); 1115 1116 runtime->private_data = azx_dev; 1117 mutex_unlock(&chip->open_mutex); 1118 return 0; 1119} 1120 1121static int azx_pcm_close(struct snd_pcm_substream *substream) 1122{ 1123 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1124 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1125 struct azx *chip = apcm->chip; 1126 struct azx_dev *azx_dev = get_azx_dev(substream); 1127 unsigned long flags; 1128 1129 mutex_lock(&chip->open_mutex); 1130 spin_lock_irqsave(&chip->reg_lock, flags); 1131 azx_dev->substream = NULL; 1132 azx_dev->running = 0; 1133 spin_unlock_irqrestore(&chip->reg_lock, flags); 1134 azx_release_device(azx_dev); 1135 hinfo->ops.close(hinfo, apcm->codec, substream); 1136 mutex_unlock(&chip->open_mutex); 1137 return 0; 1138} 1139 1140static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) 1141{ 1142 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 1143} 1144 1145static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 1146{ 1147 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1148 struct azx_dev *azx_dev = get_azx_dev(substream); 1149 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1150 1151 /* reset BDL address */ 1152 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1153 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1154 azx_sd_writel(azx_dev, SD_CTL, 0); 1155 1156 hinfo->ops.cleanup(hinfo, apcm->codec, substream); 1157 1158 return snd_pcm_lib_free_pages(substream); 1159} 1160 1161static int azx_pcm_prepare(struct snd_pcm_substream *substream) 1162{ 1163 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1164 struct azx *chip = apcm->chip; 1165 struct azx_dev *azx_dev = get_azx_dev(substream); 1166 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1167 struct snd_pcm_runtime *runtime = substream->runtime; 1168 1169 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); 1170 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream); 1171 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize; 1172 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, 1173 runtime->channels, 1174 runtime->format, 1175 hinfo->maxbps); 1176 if (! azx_dev->format_val) { 1177 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n", 1178 runtime->rate, runtime->channels, runtime->format); 1179 return -EINVAL; 1180 } 1181 1182 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n", 1183 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val); 1184 azx_setup_periods(azx_dev); 1185 azx_setup_controller(chip, azx_dev); 1186 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1187 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 1188 else 1189 azx_dev->fifo_size = 0; 1190 1191 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, 1192 azx_dev->format_val, substream); 1193} 1194 1195static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1196{ 1197 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1198 struct azx_dev *azx_dev = get_azx_dev(substream); 1199 struct azx *chip = apcm->chip; 1200 int err = 0; 1201 1202 spin_lock(&chip->reg_lock); 1203 switch (cmd) { 1204 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1205 case SNDRV_PCM_TRIGGER_RESUME: 1206 case SNDRV_PCM_TRIGGER_START: 1207 azx_stream_start(chip, azx_dev); 1208 azx_dev->running = 1; 1209 break; 1210 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1211 case SNDRV_PCM_TRIGGER_SUSPEND: 1212 case SNDRV_PCM_TRIGGER_STOP: 1213 azx_stream_stop(chip, azx_dev); 1214 azx_dev->running = 0; 1215 break; 1216 default: 1217 err = -EINVAL; 1218 } 1219 spin_unlock(&chip->reg_lock); 1220 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH || 1221 cmd == SNDRV_PCM_TRIGGER_SUSPEND || 1222 cmd == SNDRV_PCM_TRIGGER_STOP) { 1223 int timeout = 5000; 1224 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) 1225 ; 1226 } 1227 return err; 1228} 1229 1230static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 1231{ 1232 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1233 struct azx *chip = apcm->chip; 1234 struct azx_dev *azx_dev = get_azx_dev(substream); 1235 unsigned int pos; 1236 1237 if (chip->position_fix == POS_FIX_POSBUF || 1238 chip->position_fix == POS_FIX_AUTO) { 1239 /* use the position buffer */ 1240 pos = le32_to_cpu(*azx_dev->posbuf); 1241 if (chip->position_fix == POS_FIX_AUTO && 1242 azx_dev->period_intr == 1 && ! pos) { 1243 printk(KERN_WARNING 1244 "hda-intel: Invalid position buffer, " 1245 "using LPIB read method instead.\n"); 1246 chip->position_fix = POS_FIX_NONE; 1247 goto read_lpib; 1248 } 1249 } else { 1250 read_lpib: 1251 /* read LPIB */ 1252 pos = azx_sd_readl(azx_dev, SD_LPIB); 1253 if (chip->position_fix == POS_FIX_FIFO) 1254 pos += azx_dev->fifo_size; 1255 } 1256 if (pos >= azx_dev->bufsize) 1257 pos = 0; 1258 return bytes_to_frames(substream->runtime, pos); 1259} 1260 1261static struct snd_pcm_ops azx_pcm_ops = { 1262 .open = azx_pcm_open, 1263 .close = azx_pcm_close, 1264 .ioctl = snd_pcm_lib_ioctl, 1265 .hw_params = azx_pcm_hw_params, 1266 .hw_free = azx_pcm_hw_free, 1267 .prepare = azx_pcm_prepare, 1268 .trigger = azx_pcm_trigger, 1269 .pointer = azx_pcm_pointer, 1270}; 1271 1272static void azx_pcm_free(struct snd_pcm *pcm) 1273{ 1274 kfree(pcm->private_data); 1275} 1276 1277static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec, 1278 struct hda_pcm *cpcm, int pcm_dev) 1279{ 1280 int err; 1281 struct snd_pcm *pcm; 1282 struct azx_pcm *apcm; 1283 1284 /* if no substreams are defined for both playback and capture, 1285 * it's just a placeholder. ignore it. 1286 */ 1287 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams) 1288 return 0; 1289 1290 snd_assert(cpcm->name, return -EINVAL); 1291 1292 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 1293 cpcm->stream[0].substreams, cpcm->stream[1].substreams, 1294 &pcm); 1295 if (err < 0) 1296 return err; 1297 strcpy(pcm->name, cpcm->name); 1298 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); 1299 if (apcm == NULL) 1300 return -ENOMEM; 1301 apcm->chip = chip; 1302 apcm->codec = codec; 1303 apcm->hinfo[0] = &cpcm->stream[0]; 1304 apcm->hinfo[1] = &cpcm->stream[1]; 1305 pcm->private_data = apcm; 1306 pcm->private_free = azx_pcm_free; 1307 if (cpcm->stream[0].substreams) 1308 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); 1309 if (cpcm->stream[1].substreams) 1310 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); 1311 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1312 snd_dma_pci_data(chip->pci), 1313 1024 * 64, 1024 * 1024); 1314 chip->pcm[pcm_dev] = pcm; 1315 if (chip->pcm_devs < pcm_dev + 1) 1316 chip->pcm_devs = pcm_dev + 1; 1317 1318 return 0; 1319} 1320 1321static int __devinit azx_pcm_create(struct azx *chip) 1322{ 1323 struct list_head *p; 1324 struct hda_codec *codec; 1325 int c, err; 1326 int pcm_dev; 1327 1328 if ((err = snd_hda_build_pcms(chip->bus)) < 0) 1329 return err; 1330 1331 /* create audio PCMs */ 1332 pcm_dev = 0; 1333 list_for_each(p, &chip->bus->codec_list) { 1334 codec = list_entry(p, struct hda_codec, list); 1335 for (c = 0; c < codec->num_pcms; c++) { 1336 if (codec->pcm_info[c].is_modem) 1337 continue; /* create later */ 1338 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) { 1339 snd_printk(KERN_ERR SFX "Too many audio PCMs\n"); 1340 return -EINVAL; 1341 } 1342 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); 1343 if (err < 0) 1344 return err; 1345 pcm_dev++; 1346 } 1347 } 1348 1349 /* create modem PCMs */ 1350 pcm_dev = AZX_MAX_AUDIO_PCMS; 1351 list_for_each(p, &chip->bus->codec_list) { 1352 codec = list_entry(p, struct hda_codec, list); 1353 for (c = 0; c < codec->num_pcms; c++) { 1354 if (! codec->pcm_info[c].is_modem) 1355 continue; /* already created */ 1356 if (pcm_dev >= AZX_MAX_PCMS) { 1357 snd_printk(KERN_ERR SFX "Too many modem PCMs\n"); 1358 return -EINVAL; 1359 } 1360 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); 1361 if (err < 0) 1362 return err; 1363 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM; 1364 pcm_dev++; 1365 } 1366 } 1367 return 0; 1368} 1369 1370/* 1371 * mixer creation - all stuff is implemented in hda module 1372 */ 1373static int __devinit azx_mixer_create(struct azx *chip) 1374{ 1375 return snd_hda_build_controls(chip->bus); 1376} 1377 1378 1379/* 1380 * initialize SD streams 1381 */ 1382static int __devinit azx_init_stream(struct azx *chip) 1383{ 1384 int i; 1385 1386 /* initialize each stream (aka device) 1387 * assign the starting bdl address to each stream (device) and initialize 1388 */ 1389 for (i = 0; i < chip->num_streams; i++) { 1390 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4); 1391 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1392 azx_dev->bdl = (u32 *)(chip->bdl.area + off); 1393 azx_dev->bdl_addr = chip->bdl.addr + off; 1394 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 1395 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 1396 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 1397 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 1398 azx_dev->sd_int_sta_mask = 1 << i; 1399 /* stream tag: must be non-zero and unique */ 1400 azx_dev->index = i; 1401 azx_dev->stream_tag = i + 1; 1402 } 1403 1404 return 0; 1405} 1406 1407static int azx_acquire_irq(struct azx *chip, int do_disconnect) 1408{ 1409 if (request_irq(chip->pci->irq, azx_interrupt, 1410 chip->msi ? 0 : IRQF_SHARED, 1411 "HDA Intel", chip)) { 1412 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 1413 "disabling device\n", chip->pci->irq); 1414 if (do_disconnect) 1415 snd_card_disconnect(chip->card); 1416 return -1; 1417 } 1418 chip->irq = chip->pci->irq; 1419 pci_intx(chip->pci, !chip->msi); 1420 return 0; 1421} 1422 1423 1424#ifdef CONFIG_PM 1425/* 1426 * power management 1427 */ 1428static int azx_suspend(struct pci_dev *pci, pm_message_t state) 1429{ 1430 struct snd_card *card = pci_get_drvdata(pci); 1431 struct azx *chip = card->private_data; 1432 int i; 1433 1434 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1435 for (i = 0; i < chip->pcm_devs; i++) 1436 snd_pcm_suspend_all(chip->pcm[i]); 1437 snd_hda_suspend(chip->bus, state); 1438 azx_free_cmd_io(chip); 1439 if (chip->irq >= 0) { 1440 synchronize_irq(chip->irq); 1441 free_irq(chip->irq, chip); 1442 chip->irq = -1; 1443 } 1444 if (chip->msi) 1445 pci_disable_msi(chip->pci); 1446 pci_disable_device(pci); 1447 pci_save_state(pci); 1448 pci_set_power_state(pci, pci_choose_state(pci, state)); 1449 return 0; 1450} 1451 1452static int azx_resume(struct pci_dev *pci) 1453{ 1454 struct snd_card *card = pci_get_drvdata(pci); 1455 struct azx *chip = card->private_data; 1456 1457 pci_set_power_state(pci, PCI_D0); 1458 pci_restore_state(pci); 1459 if (pci_enable_device(pci) < 0) { 1460 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 1461 "disabling device\n"); 1462 snd_card_disconnect(card); 1463 return -EIO; 1464 } 1465 pci_set_master(pci); 1466 if (chip->msi) 1467 if (pci_enable_msi(pci) < 0) 1468 chip->msi = 0; 1469 if (azx_acquire_irq(chip, 1) < 0) 1470 return -EIO; 1471 azx_init_chip(chip); 1472 snd_hda_resume(chip->bus); 1473 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1474 return 0; 1475} 1476#endif /* CONFIG_PM */ 1477 1478 1479/* 1480 * destructor 1481 */ 1482static int azx_free(struct azx *chip) 1483{ 1484 if (chip->initialized) { 1485 int i; 1486 1487 for (i = 0; i < chip->num_streams; i++) 1488 azx_stream_stop(chip, &chip->azx_dev[i]); 1489 1490 /* disable interrupts */ 1491 azx_int_disable(chip); 1492 azx_int_clear(chip); 1493 1494 /* disable CORB/RIRB */ 1495 azx_free_cmd_io(chip); 1496 1497 /* disable position buffer */ 1498 azx_writel(chip, DPLBASE, 0); 1499 azx_writel(chip, DPUBASE, 0); 1500 } 1501 1502 if (chip->irq >= 0) { 1503 synchronize_irq(chip->irq); 1504 free_irq(chip->irq, (void*)chip); 1505 } 1506 if (chip->msi) 1507 pci_disable_msi(chip->pci); 1508 if (chip->remap_addr) 1509 iounmap(chip->remap_addr); 1510 1511 if (chip->bdl.area) 1512 snd_dma_free_pages(&chip->bdl); 1513 if (chip->rb.area) 1514 snd_dma_free_pages(&chip->rb); 1515 if (chip->posbuf.area) 1516 snd_dma_free_pages(&chip->posbuf); 1517 pci_release_regions(chip->pci); 1518 pci_disable_device(chip->pci); 1519 kfree(chip->azx_dev); 1520 kfree(chip); 1521 1522 return 0; 1523} 1524 1525static int azx_dev_free(struct snd_device *device) 1526{ 1527 return azx_free(device->device_data); 1528} 1529 1530/* 1531 * white/black-listing for position_fix 1532 */ 1533static struct snd_pci_quirk position_fix_list[] __devinitdata = { 1534 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE), 1535 {} 1536}; 1537 1538static int __devinit check_position_fix(struct azx *chip, int fix) 1539{ 1540 const struct snd_pci_quirk *q; 1541 1542 if (fix == POS_FIX_AUTO) { 1543 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1544 if (q) { 1545 snd_printdd(KERN_INFO 1546 "hda_intel: position_fix set to %d " 1547 "for device %04x:%04x\n", 1548 q->value, q->subvendor, q->subdevice); 1549 return q->value; 1550 } 1551 } 1552 return fix; 1553} 1554 1555/* 1556 * constructor 1557 */ 1558static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, 1559 int driver_type, 1560 struct azx **rchip) 1561{ 1562 struct azx *chip; 1563 int err; 1564 static struct snd_device_ops ops = { 1565 .dev_free = azx_dev_free, 1566 }; 1567 1568 *rchip = NULL; 1569 1570 err = pci_enable_device(pci); 1571 if (err < 0) 1572 return err; 1573 1574 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1575 if (!chip) { 1576 snd_printk(KERN_ERR SFX "cannot allocate chip\n"); 1577 pci_disable_device(pci); 1578 return -ENOMEM; 1579 } 1580 1581 spin_lock_init(&chip->reg_lock); 1582 mutex_init(&chip->open_mutex); 1583 chip->card = card; 1584 chip->pci = pci; 1585 chip->irq = -1; 1586 chip->driver_type = driver_type; 1587 chip->msi = enable_msi; 1588 1589 chip->position_fix = check_position_fix(chip, position_fix); 1590 1591 chip->single_cmd = single_cmd; 1592 1593#if BITS_PER_LONG != 64 1594 /* Fix up base address on ULI M5461 */ 1595 if (chip->driver_type == AZX_DRIVER_ULI) { 1596 u16 tmp3; 1597 pci_read_config_word(pci, 0x40, &tmp3); 1598 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1599 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1600 } 1601#endif 1602 1603 err = pci_request_regions(pci, "ICH HD audio"); 1604 if (err < 0) { 1605 kfree(chip); 1606 pci_disable_device(pci); 1607 return err; 1608 } 1609 1610 chip->addr = pci_resource_start(pci, 0); 1611 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); 1612 if (chip->remap_addr == NULL) { 1613 snd_printk(KERN_ERR SFX "ioremap error\n"); 1614 err = -ENXIO; 1615 goto errout; 1616 } 1617 1618 if (chip->msi) 1619 if (pci_enable_msi(pci) < 0) 1620 chip->msi = 0; 1621 1622 if (azx_acquire_irq(chip, 0) < 0) { 1623 err = -EBUSY; 1624 goto errout; 1625 } 1626 1627 pci_set_master(pci); 1628 synchronize_irq(chip->irq); 1629 1630 switch (chip->driver_type) { 1631 case AZX_DRIVER_ULI: 1632 chip->playback_streams = ULI_NUM_PLAYBACK; 1633 chip->capture_streams = ULI_NUM_CAPTURE; 1634 chip->playback_index_offset = ULI_PLAYBACK_INDEX; 1635 chip->capture_index_offset = ULI_CAPTURE_INDEX; 1636 break; 1637 case AZX_DRIVER_ATIHDMI: 1638 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1639 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1640 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX; 1641 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX; 1642 break; 1643 default: 1644 chip->playback_streams = ICH6_NUM_PLAYBACK; 1645 chip->capture_streams = ICH6_NUM_CAPTURE; 1646 chip->playback_index_offset = ICH6_PLAYBACK_INDEX; 1647 chip->capture_index_offset = ICH6_CAPTURE_INDEX; 1648 break; 1649 } 1650 chip->num_streams = chip->playback_streams + chip->capture_streams; 1651 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL); 1652 if (!chip->azx_dev) { 1653 snd_printk(KERN_ERR "cannot malloc azx_dev\n"); 1654 goto errout; 1655 } 1656 1657 /* allocate memory for the BDL for each stream */ 1658 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1659 BDL_SIZE, &chip->bdl)) < 0) { 1660 snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); 1661 goto errout; 1662 } 1663 /* allocate memory for the position buffer */ 1664 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1665 chip->num_streams * 8, &chip->posbuf)) < 0) { 1666 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); 1667 goto errout; 1668 } 1669 /* allocate CORB/RIRB */ 1670 if (! chip->single_cmd) 1671 if ((err = azx_alloc_cmd_io(chip)) < 0) 1672 goto errout; 1673 1674 /* initialize streams */ 1675 azx_init_stream(chip); 1676 1677 /* initialize chip */ 1678 azx_init_chip(chip); 1679 1680 chip->initialized = 1; 1681 1682 /* codec detection */ 1683 if (!chip->codec_mask) { 1684 snd_printk(KERN_ERR SFX "no codecs found!\n"); 1685 err = -ENODEV; 1686 goto errout; 1687 } 1688 1689 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) { 1690 snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); 1691 goto errout; 1692 } 1693 1694 strcpy(card->driver, "HDA-Intel"); 1695 strcpy(card->shortname, driver_short_names[chip->driver_type]); 1696 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq); 1697 1698 *rchip = chip; 1699 return 0; 1700 1701 errout: 1702 azx_free(chip); 1703 return err; 1704} 1705 1706static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1707{ 1708 struct snd_card *card; 1709 struct azx *chip; 1710 int err; 1711 1712 card = snd_card_new(index, id, THIS_MODULE, 0); 1713 if (!card) { 1714 snd_printk(KERN_ERR SFX "Error creating card!\n"); 1715 return -ENOMEM; 1716 } 1717 1718 err = azx_create(card, pci, pci_id->driver_data, &chip); 1719 if (err < 0) { 1720 snd_card_free(card); 1721 return err; 1722 } 1723 card->private_data = chip; 1724 1725 /* create codec instances */ 1726 if ((err = azx_codec_create(chip, model)) < 0) { 1727 snd_card_free(card); 1728 return err; 1729 } 1730 1731 /* create PCM streams */ 1732 if ((err = azx_pcm_create(chip)) < 0) { 1733 snd_card_free(card); 1734 return err; 1735 } 1736 1737 /* create mixer controls */ 1738 if ((err = azx_mixer_create(chip)) < 0) { 1739 snd_card_free(card); 1740 return err; 1741 } 1742 1743 snd_card_set_dev(card, &pci->dev); 1744 1745 if ((err = snd_card_register(card)) < 0) { 1746 snd_card_free(card); 1747 return err; 1748 } 1749 1750 pci_set_drvdata(pci, card); 1751 1752 return err; 1753} 1754 1755static void __devexit azx_remove(struct pci_dev *pci) 1756{ 1757 snd_card_free(pci_get_drvdata(pci)); 1758 pci_set_drvdata(pci, NULL); 1759} 1760 1761/* PCI IDs */ 1762static struct pci_device_id azx_ids[] = { 1763 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */ 1764 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */ 1765 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */ 1766 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */ 1767 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */ 1768 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */ 1769 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */ 1770 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */ 1771 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */ 1772 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */ 1773 { 0x1002, 0x960c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */ 1774 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */ 1775 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */ 1776 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */ 1777 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */ 1778 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */ 1779 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */ 1780 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */ 1781 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */ 1782 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */ 1783 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */ 1784 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */ 1785 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */ 1786 { 0, } 1787}; 1788MODULE_DEVICE_TABLE(pci, azx_ids); 1789 1790/* pci_driver definition */ 1791static struct pci_driver driver = { 1792 .name = "HDA Intel", 1793 .id_table = azx_ids, 1794 .probe = azx_probe, 1795 .remove = __devexit_p(azx_remove), 1796#ifdef CONFIG_PM 1797 .suspend = azx_suspend, 1798 .resume = azx_resume, 1799#endif 1800}; 1801 1802static int __init alsa_card_azx_init(void) 1803{ 1804 return pci_register_driver(&driver); 1805} 1806 1807static void __exit alsa_card_azx_exit(void) 1808{ 1809 pci_unregister_driver(&driver); 1810} 1811 1812module_init(alsa_card_azx_init) 1813module_exit(alsa_card_azx_exit) 1814