1#ifndef __SOUND_CS46XX_H 2#define __SOUND_CS46XX_H 3 4/* 5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, 6 * Cirrus Logic, Inc. 7 * Definitions for Cirrus Logic CS46xx chips 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26#include "pcm.h" 27#include "pcm-indirect.h" 28#include "rawmidi.h" 29#include "ac97_codec.h" 30#include "cs46xx_dsp_spos.h" 31 32/* 33 * Direct registers 34 */ 35 36/* 37 * The following define the offsets of the registers accessed via base address 38 * register zero on the CS46xx part. 39 */ 40#define BA0_HISR 0x00000000 41#define BA0_HSR0 0x00000004 42#define BA0_HICR 0x00000008 43#define BA0_DMSR 0x00000100 44#define BA0_HSAR 0x00000110 45#define BA0_HDAR 0x00000114 46#define BA0_HDMR 0x00000118 47#define BA0_HDCR 0x0000011C 48#define BA0_PFMC 0x00000200 49#define BA0_PFCV1 0x00000204 50#define BA0_PFCV2 0x00000208 51#define BA0_PCICFG00 0x00000300 52#define BA0_PCICFG04 0x00000304 53#define BA0_PCICFG08 0x00000308 54#define BA0_PCICFG0C 0x0000030C 55#define BA0_PCICFG10 0x00000310 56#define BA0_PCICFG14 0x00000314 57#define BA0_PCICFG18 0x00000318 58#define BA0_PCICFG1C 0x0000031C 59#define BA0_PCICFG20 0x00000320 60#define BA0_PCICFG24 0x00000324 61#define BA0_PCICFG28 0x00000328 62#define BA0_PCICFG2C 0x0000032C 63#define BA0_PCICFG30 0x00000330 64#define BA0_PCICFG34 0x00000334 65#define BA0_PCICFG38 0x00000338 66#define BA0_PCICFG3C 0x0000033C 67#define BA0_CLKCR1 0x00000400 68#define BA0_CLKCR2 0x00000404 69#define BA0_PLLM 0x00000408 70#define BA0_PLLCC 0x0000040C 71#define BA0_FRR 0x00000410 72#define BA0_CFL1 0x00000414 73#define BA0_CFL2 0x00000418 74#define BA0_SERMC1 0x00000420 75#define BA0_SERMC2 0x00000424 76#define BA0_SERC1 0x00000428 77#define BA0_SERC2 0x0000042C 78#define BA0_SERC3 0x00000430 79#define BA0_SERC4 0x00000434 80#define BA0_SERC5 0x00000438 81#define BA0_SERBSP 0x0000043C 82#define BA0_SERBST 0x00000440 83#define BA0_SERBCM 0x00000444 84#define BA0_SERBAD 0x00000448 85#define BA0_SERBCF 0x0000044C 86#define BA0_SERBWP 0x00000450 87#define BA0_SERBRP 0x00000454 88#ifndef NO_CS4612 89#define BA0_ASER_FADDR 0x00000458 90#endif 91#define BA0_ACCTL 0x00000460 92#define BA0_ACSTS 0x00000464 93#define BA0_ACOSV 0x00000468 94#define BA0_ACCAD 0x0000046C 95#define BA0_ACCDA 0x00000470 96#define BA0_ACISV 0x00000474 97#define BA0_ACSAD 0x00000478 98#define BA0_ACSDA 0x0000047C 99#define BA0_JSPT 0x00000480 100#define BA0_JSCTL 0x00000484 101#define BA0_JSC1 0x00000488 102#define BA0_JSC2 0x0000048C 103#define BA0_MIDCR 0x00000490 104#define BA0_MIDSR 0x00000494 105#define BA0_MIDWP 0x00000498 106#define BA0_MIDRP 0x0000049C 107#define BA0_JSIO 0x000004A0 108#ifndef NO_CS4612 109#define BA0_ASER_MASTER 0x000004A4 110#endif 111#define BA0_CFGI 0x000004B0 112#define BA0_SSVID 0x000004B4 113#define BA0_GPIOR 0x000004B8 114#ifndef NO_CS4612 115#define BA0_EGPIODR 0x000004BC 116#define BA0_EGPIOPTR 0x000004C0 117#define BA0_EGPIOTR 0x000004C4 118#define BA0_EGPIOWR 0x000004C8 119#define BA0_EGPIOSR 0x000004CC 120#define BA0_SERC6 0x000004D0 121#define BA0_SERC7 0x000004D4 122#define BA0_SERACC 0x000004D8 123#define BA0_ACCTL2 0x000004E0 124#define BA0_ACSTS2 0x000004E4 125#define BA0_ACOSV2 0x000004E8 126#define BA0_ACCAD2 0x000004EC 127#define BA0_ACCDA2 0x000004F0 128#define BA0_ACISV2 0x000004F4 129#define BA0_ACSAD2 0x000004F8 130#define BA0_ACSDA2 0x000004FC 131#define BA0_IOTAC0 0x00000500 132#define BA0_IOTAC1 0x00000504 133#define BA0_IOTAC2 0x00000508 134#define BA0_IOTAC3 0x0000050C 135#define BA0_IOTAC4 0x00000510 136#define BA0_IOTAC5 0x00000514 137#define BA0_IOTAC6 0x00000518 138#define BA0_IOTAC7 0x0000051C 139#define BA0_IOTAC8 0x00000520 140#define BA0_IOTAC9 0x00000524 141#define BA0_IOTAC10 0x00000528 142#define BA0_IOTAC11 0x0000052C 143#define BA0_IOTFR0 0x00000540 144#define BA0_IOTFR1 0x00000544 145#define BA0_IOTFR2 0x00000548 146#define BA0_IOTFR3 0x0000054C 147#define BA0_IOTFR4 0x00000550 148#define BA0_IOTFR5 0x00000554 149#define BA0_IOTFR6 0x00000558 150#define BA0_IOTFR7 0x0000055C 151#define BA0_IOTFIFO 0x00000580 152#define BA0_IOTRRD 0x00000584 153#define BA0_IOTFP 0x00000588 154#define BA0_IOTCR 0x0000058C 155#define BA0_DPCID 0x00000590 156#define BA0_DPCIA 0x00000594 157#define BA0_DPCIC 0x00000598 158#define BA0_PCPCIR 0x00000600 159#define BA0_PCPCIG 0x00000604 160#define BA0_PCPCIEN 0x00000608 161#define BA0_EPCIPMC 0x00000610 162#endif 163 164/* 165 * The following define the offsets of the registers and memories accessed via 166 * base address register one on the CS46xx part. 167 */ 168#define BA1_SP_DMEM0 0x00000000 169#define BA1_SP_DMEM1 0x00010000 170#define BA1_SP_PMEM 0x00020000 171#define BA1_SP_REG 0x00030000 172#define BA1_SPCR 0x00030000 173#define BA1_DREG 0x00030004 174#define BA1_DSRWP 0x00030008 175#define BA1_TWPR 0x0003000C 176#define BA1_SPWR 0x00030010 177#define BA1_SPIR 0x00030014 178#define BA1_FGR1 0x00030020 179#define BA1_SPCS 0x00030028 180#define BA1_SDSR 0x0003002C 181#define BA1_FRMT 0x00030030 182#define BA1_FRCC 0x00030034 183#define BA1_FRSC 0x00030038 184#define BA1_OMNI_MEM 0x000E0000 185 186 187/* 188 * The following defines are for the flags in the host interrupt status 189 * register. 190 */ 191#define HISR_VC_MASK 0x0000FFFF 192#define HISR_VC0 0x00000001 193#define HISR_VC1 0x00000002 194#define HISR_VC2 0x00000004 195#define HISR_VC3 0x00000008 196#define HISR_VC4 0x00000010 197#define HISR_VC5 0x00000020 198#define HISR_VC6 0x00000040 199#define HISR_VC7 0x00000080 200#define HISR_VC8 0x00000100 201#define HISR_VC9 0x00000200 202#define HISR_VC10 0x00000400 203#define HISR_VC11 0x00000800 204#define HISR_VC12 0x00001000 205#define HISR_VC13 0x00002000 206#define HISR_VC14 0x00004000 207#define HISR_VC15 0x00008000 208#define HISR_INT0 0x00010000 209#define HISR_INT1 0x00020000 210#define HISR_DMAI 0x00040000 211#define HISR_FROVR 0x00080000 212#define HISR_MIDI 0x00100000 213#ifdef NO_CS4612 214#define HISR_RESERVED 0x0FE00000 215#else 216#define HISR_SBINT 0x00200000 217#define HISR_RESERVED 0x0FC00000 218#endif 219#define HISR_H0P 0x40000000 220#define HISR_INTENA 0x80000000 221 222/* 223 * The following defines are for the flags in the host signal register 0. 224 */ 225#define HSR0_VC_MASK 0xFFFFFFFF 226#define HSR0_VC16 0x00000001 227#define HSR0_VC17 0x00000002 228#define HSR0_VC18 0x00000004 229#define HSR0_VC19 0x00000008 230#define HSR0_VC20 0x00000010 231#define HSR0_VC21 0x00000020 232#define HSR0_VC22 0x00000040 233#define HSR0_VC23 0x00000080 234#define HSR0_VC24 0x00000100 235#define HSR0_VC25 0x00000200 236#define HSR0_VC26 0x00000400 237#define HSR0_VC27 0x00000800 238#define HSR0_VC28 0x00001000 239#define HSR0_VC29 0x00002000 240#define HSR0_VC30 0x00004000 241#define HSR0_VC31 0x00008000 242#define HSR0_VC32 0x00010000 243#define HSR0_VC33 0x00020000 244#define HSR0_VC34 0x00040000 245#define HSR0_VC35 0x00080000 246#define HSR0_VC36 0x00100000 247#define HSR0_VC37 0x00200000 248#define HSR0_VC38 0x00400000 249#define HSR0_VC39 0x00800000 250#define HSR0_VC40 0x01000000 251#define HSR0_VC41 0x02000000 252#define HSR0_VC42 0x04000000 253#define HSR0_VC43 0x08000000 254#define HSR0_VC44 0x10000000 255#define HSR0_VC45 0x20000000 256#define HSR0_VC46 0x40000000 257#define HSR0_VC47 0x80000000 258 259/* 260 * The following defines are for the flags in the host interrupt control 261 * register. 262 */ 263#define HICR_IEV 0x00000001 264#define HICR_CHGM 0x00000002 265 266/* 267 * The following defines are for the flags in the DMA status register. 268 */ 269#define DMSR_HP 0x00000001 270#define DMSR_HR 0x00000002 271#define DMSR_SP 0x00000004 272#define DMSR_SR 0x00000008 273 274/* 275 * The following defines are for the flags in the host DMA source address 276 * register. 277 */ 278#define HSAR_HOST_ADDR_MASK 0xFFFFFFFF 279#define HSAR_DSP_ADDR_MASK 0x0000FFFF 280#define HSAR_MEMID_MASK 0x000F0000 281#define HSAR_MEMID_SP_DMEM0 0x00000000 282#define HSAR_MEMID_SP_DMEM1 0x00010000 283#define HSAR_MEMID_SP_PMEM 0x00020000 284#define HSAR_MEMID_SP_DEBUG 0x00030000 285#define HSAR_MEMID_OMNI_MEM 0x000E0000 286#define HSAR_END 0x40000000 287#define HSAR_ERR 0x80000000 288 289/* 290 * The following defines are for the flags in the host DMA destination address 291 * register. 292 */ 293#define HDAR_HOST_ADDR_MASK 0xFFFFFFFF 294#define HDAR_DSP_ADDR_MASK 0x0000FFFF 295#define HDAR_MEMID_MASK 0x000F0000 296#define HDAR_MEMID_SP_DMEM0 0x00000000 297#define HDAR_MEMID_SP_DMEM1 0x00010000 298#define HDAR_MEMID_SP_PMEM 0x00020000 299#define HDAR_MEMID_SP_DEBUG 0x00030000 300#define HDAR_MEMID_OMNI_MEM 0x000E0000 301#define HDAR_END 0x40000000 302#define HDAR_ERR 0x80000000 303 304/* 305 * The following defines are for the flags in the host DMA control register. 306 */ 307#define HDMR_AC_MASK 0x0000F000 308#define HDMR_AC_8_16 0x00001000 309#define HDMR_AC_M_S 0x00002000 310#define HDMR_AC_B_L 0x00004000 311#define HDMR_AC_S_U 0x00008000 312 313/* 314 * The following defines are for the flags in the host DMA control register. 315 */ 316#define HDCR_COUNT_MASK 0x000003FF 317#define HDCR_DONE 0x00004000 318#define HDCR_OPT 0x00008000 319#define HDCR_WBD 0x00400000 320#define HDCR_WBS 0x00800000 321#define HDCR_DMS_MASK 0x07000000 322#define HDCR_DMS_LINEAR 0x00000000 323#define HDCR_DMS_16_DWORDS 0x01000000 324#define HDCR_DMS_32_DWORDS 0x02000000 325#define HDCR_DMS_64_DWORDS 0x03000000 326#define HDCR_DMS_128_DWORDS 0x04000000 327#define HDCR_DMS_256_DWORDS 0x05000000 328#define HDCR_DMS_512_DWORDS 0x06000000 329#define HDCR_DMS_1024_DWORDS 0x07000000 330#define HDCR_DH 0x08000000 331#define HDCR_SMS_MASK 0x70000000 332#define HDCR_SMS_LINEAR 0x00000000 333#define HDCR_SMS_16_DWORDS 0x10000000 334#define HDCR_SMS_32_DWORDS 0x20000000 335#define HDCR_SMS_64_DWORDS 0x30000000 336#define HDCR_SMS_128_DWORDS 0x40000000 337#define HDCR_SMS_256_DWORDS 0x50000000 338#define HDCR_SMS_512_DWORDS 0x60000000 339#define HDCR_SMS_1024_DWORDS 0x70000000 340#define HDCR_SH 0x80000000 341#define HDCR_COUNT_SHIFT 0 342 343/* 344 * The following defines are for the flags in the performance monitor control 345 * register. 346 */ 347#define PFMC_C1SS_MASK 0x0000001F 348#define PFMC_C1EV 0x00000020 349#define PFMC_C1RS 0x00008000 350#define PFMC_C2SS_MASK 0x001F0000 351#define PFMC_C2EV 0x00200000 352#define PFMC_C2RS 0x80000000 353#define PFMC_C1SS_SHIFT 0 354#define PFMC_C2SS_SHIFT 16 355#define PFMC_BUS_GRANT 0 356#define PFMC_GRANT_AFTER_REQ 1 357#define PFMC_TRANSACTION 2 358#define PFMC_DWORD_TRANSFER 3 359#define PFMC_SLAVE_READ 4 360#define PFMC_SLAVE_WRITE 5 361#define PFMC_PREEMPTION 6 362#define PFMC_DISCONNECT_RETRY 7 363#define PFMC_INTERRUPT 8 364#define PFMC_BUS_OWNERSHIP 9 365#define PFMC_TRANSACTION_LAG 10 366#define PFMC_PCI_CLOCK 11 367#define PFMC_SERIAL_CLOCK 12 368#define PFMC_SP_CLOCK 13 369 370/* 371 * The following defines are for the flags in the performance counter value 1 372 * register. 373 */ 374#define PFCV1_PC1V_MASK 0xFFFFFFFF 375#define PFCV1_PC1V_SHIFT 0 376 377/* 378 * The following defines are for the flags in the performance counter value 2 379 * register. 380 */ 381#define PFCV2_PC2V_MASK 0xFFFFFFFF 382#define PFCV2_PC2V_SHIFT 0 383 384/* 385 * The following defines are for the flags in the clock control register 1. 386 */ 387#define CLKCR1_OSCS 0x00000001 388#define CLKCR1_OSCP 0x00000002 389#define CLKCR1_PLLSS_MASK 0x0000000C 390#define CLKCR1_PLLSS_SERIAL 0x00000000 391#define CLKCR1_PLLSS_CRYSTAL 0x00000004 392#define CLKCR1_PLLSS_PCI 0x00000008 393#define CLKCR1_PLLSS_RESERVED 0x0000000C 394#define CLKCR1_PLLP 0x00000010 395#define CLKCR1_SWCE 0x00000020 396#define CLKCR1_PLLOS 0x00000040 397 398/* 399 * The following defines are for the flags in the clock control register 2. 400 */ 401#define CLKCR2_PDIVS_MASK 0x0000000F 402#define CLKCR2_PDIVS_1 0x00000001 403#define CLKCR2_PDIVS_2 0x00000002 404#define CLKCR2_PDIVS_4 0x00000004 405#define CLKCR2_PDIVS_7 0x00000007 406#define CLKCR2_PDIVS_8 0x00000008 407#define CLKCR2_PDIVS_16 0x00000000 408 409/* 410 * The following defines are for the flags in the PLL multiplier register. 411 */ 412#define PLLM_MASK 0x000000FF 413#define PLLM_SHIFT 0 414 415/* 416 * The following defines are for the flags in the PLL capacitor coefficient 417 * register. 418 */ 419#define PLLCC_CDR_MASK 0x00000007 420#ifndef NO_CS4610 421#define PLLCC_CDR_240_350_MHZ 0x00000000 422#define PLLCC_CDR_184_265_MHZ 0x00000001 423#define PLLCC_CDR_144_205_MHZ 0x00000002 424#define PLLCC_CDR_111_160_MHZ 0x00000003 425#define PLLCC_CDR_87_123_MHZ 0x00000004 426#define PLLCC_CDR_67_96_MHZ 0x00000005 427#define PLLCC_CDR_52_74_MHZ 0x00000006 428#define PLLCC_CDR_45_58_MHZ 0x00000007 429#endif 430#ifndef NO_CS4612 431#define PLLCC_CDR_271_398_MHZ 0x00000000 432#define PLLCC_CDR_227_330_MHZ 0x00000001 433#define PLLCC_CDR_167_239_MHZ 0x00000002 434#define PLLCC_CDR_150_215_MHZ 0x00000003 435#define PLLCC_CDR_107_154_MHZ 0x00000004 436#define PLLCC_CDR_98_140_MHZ 0x00000005 437#define PLLCC_CDR_73_104_MHZ 0x00000006 438#define PLLCC_CDR_63_90_MHZ 0x00000007 439#endif 440#define PLLCC_LPF_MASK 0x000000F8 441#ifndef NO_CS4610 442#define PLLCC_LPF_23850_60000_KHZ 0x00000000 443#define PLLCC_LPF_7960_26290_KHZ 0x00000008 444#define PLLCC_LPF_4160_10980_KHZ 0x00000018 445#define PLLCC_LPF_1740_4580_KHZ 0x00000038 446#define PLLCC_LPF_724_1910_KHZ 0x00000078 447#define PLLCC_LPF_317_798_KHZ 0x000000F8 448#endif 449#ifndef NO_CS4612 450#define PLLCC_LPF_25580_64530_KHZ 0x00000000 451#define PLLCC_LPF_14360_37270_KHZ 0x00000008 452#define PLLCC_LPF_6100_16020_KHZ 0x00000018 453#define PLLCC_LPF_2540_6690_KHZ 0x00000038 454#define PLLCC_LPF_1050_2780_KHZ 0x00000078 455#define PLLCC_LPF_450_1160_KHZ 0x000000F8 456#endif 457 458/* 459 * The following defines are for the flags in the feature reporting register. 460 */ 461#define FRR_FAB_MASK 0x00000003 462#define FRR_MASK_MASK 0x0000001C 463#ifdef NO_CS4612 464#define FRR_CFOP_MASK 0x000000E0 465#else 466#define FRR_CFOP_MASK 0x00000FE0 467#endif 468#define FRR_CFOP_NOT_DVD 0x00000020 469#define FRR_CFOP_A3D 0x00000040 470#define FRR_CFOP_128_PIN 0x00000080 471#ifndef NO_CS4612 472#define FRR_CFOP_CS4280 0x00000800 473#endif 474#define FRR_FAB_SHIFT 0 475#define FRR_MASK_SHIFT 2 476#define FRR_CFOP_SHIFT 5 477 478/* 479 * The following defines are for the flags in the configuration load 1 480 * register. 481 */ 482#define CFL1_CLOCK_SOURCE_MASK 0x00000003 483#define CFL1_CLOCK_SOURCE_CS423X 0x00000000 484#define CFL1_CLOCK_SOURCE_AC97 0x00000001 485#define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002 486#define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003 487#define CFL1_VALID_DATA_MASK 0x000000FF 488 489/* 490 * The following defines are for the flags in the configuration load 2 491 * register. 492 */ 493#define CFL2_VALID_DATA_MASK 0x000000FF 494 495/* 496 * The following defines are for the flags in the serial port master control 497 * register 1. 498 */ 499#define SERMC1_MSPE 0x00000001 500#define SERMC1_PTC_MASK 0x0000000E 501#define SERMC1_PTC_CS423X 0x00000000 502#define SERMC1_PTC_AC97 0x00000002 503#define SERMC1_PTC_DAC 0x00000004 504#define SERMC1_PLB 0x00000010 505#define SERMC1_XLB 0x00000020 506 507/* 508 * The following defines are for the flags in the serial port master control 509 * register 2. 510 */ 511#define SERMC2_LROE 0x00000001 512#define SERMC2_MCOE 0x00000002 513#define SERMC2_MCDIV 0x00000004 514 515/* 516 * The following defines are for the flags in the serial port 1 configuration 517 * register. 518 */ 519#define SERC1_SO1EN 0x00000001 520#define SERC1_SO1F_MASK 0x0000000E 521#define SERC1_SO1F_CS423X 0x00000000 522#define SERC1_SO1F_AC97 0x00000002 523#define SERC1_SO1F_DAC 0x00000004 524#define SERC1_SO1F_SPDIF 0x00000006 525 526/* 527 * The following defines are for the flags in the serial port 2 configuration 528 * register. 529 */ 530#define SERC2_SI1EN 0x00000001 531#define SERC2_SI1F_MASK 0x0000000E 532#define SERC2_SI1F_CS423X 0x00000000 533#define SERC2_SI1F_AC97 0x00000002 534#define SERC2_SI1F_ADC 0x00000004 535#define SERC2_SI1F_SPDIF 0x00000006 536 537/* 538 * The following defines are for the flags in the serial port 3 configuration 539 * register. 540 */ 541#define SERC3_SO2EN 0x00000001 542#define SERC3_SO2F_MASK 0x00000006 543#define SERC3_SO2F_DAC 0x00000000 544#define SERC3_SO2F_SPDIF 0x00000002 545 546/* 547 * The following defines are for the flags in the serial port 4 configuration 548 * register. 549 */ 550#define SERC4_SO3EN 0x00000001 551#define SERC4_SO3F_MASK 0x00000006 552#define SERC4_SO3F_DAC 0x00000000 553#define SERC4_SO3F_SPDIF 0x00000002 554 555/* 556 * The following defines are for the flags in the serial port 5 configuration 557 * register. 558 */ 559#define SERC5_SI2EN 0x00000001 560#define SERC5_SI2F_MASK 0x00000006 561#define SERC5_SI2F_ADC 0x00000000 562#define SERC5_SI2F_SPDIF 0x00000002 563 564/* 565 * The following defines are for the flags in the serial port backdoor sample 566 * pointer register. 567 */ 568#define SERBSP_FSP_MASK 0x0000000F 569#define SERBSP_FSP_SHIFT 0 570 571/* 572 * The following defines are for the flags in the serial port backdoor status 573 * register. 574 */ 575#define SERBST_RRDY 0x00000001 576#define SERBST_WBSY 0x00000002 577 578/* 579 * The following defines are for the flags in the serial port backdoor command 580 * register. 581 */ 582#define SERBCM_RDC 0x00000001 583#define SERBCM_WRC 0x00000002 584 585/* 586 * The following defines are for the flags in the serial port backdoor address 587 * register. 588 */ 589#ifdef NO_CS4612 590#define SERBAD_FAD_MASK 0x000000FF 591#else 592#define SERBAD_FAD_MASK 0x000001FF 593#endif 594#define SERBAD_FAD_SHIFT 0 595 596/* 597 * The following defines are for the flags in the serial port backdoor 598 * configuration register. 599 */ 600#define SERBCF_HBP 0x00000001 601 602/* 603 * The following defines are for the flags in the serial port backdoor write 604 * port register. 605 */ 606#define SERBWP_FWD_MASK 0x000FFFFF 607#define SERBWP_FWD_SHIFT 0 608 609/* 610 * The following defines are for the flags in the serial port backdoor read 611 * port register. 612 */ 613#define SERBRP_FRD_MASK 0x000FFFFF 614#define SERBRP_FRD_SHIFT 0 615 616/* 617 * The following defines are for the flags in the async FIFO address register. 618 */ 619#ifndef NO_CS4612 620#define ASER_FADDR_A1_MASK 0x000001FF 621#define ASER_FADDR_EN1 0x00008000 622#define ASER_FADDR_A2_MASK 0x01FF0000 623#define ASER_FADDR_EN2 0x80000000 624#define ASER_FADDR_A1_SHIFT 0 625#define ASER_FADDR_A2_SHIFT 16 626#endif 627 628/* 629 * The following defines are for the flags in the AC97 control register. 630 */ 631#define ACCTL_RSTN 0x00000001 632#define ACCTL_ESYN 0x00000002 633#define ACCTL_VFRM 0x00000004 634#define ACCTL_DCV 0x00000008 635#define ACCTL_CRW 0x00000010 636#define ACCTL_ASYN 0x00000020 637#ifndef NO_CS4612 638#define ACCTL_TC 0x00000040 639#endif 640 641/* 642 * The following defines are for the flags in the AC97 status register. 643 */ 644#define ACSTS_CRDY 0x00000001 645#define ACSTS_VSTS 0x00000002 646#ifndef NO_CS4612 647#define ACSTS_WKUP 0x00000004 648#endif 649 650/* 651 * The following defines are for the flags in the AC97 output slot valid 652 * register. 653 */ 654#define ACOSV_SLV3 0x00000001 655#define ACOSV_SLV4 0x00000002 656#define ACOSV_SLV5 0x00000004 657#define ACOSV_SLV6 0x00000008 658#define ACOSV_SLV7 0x00000010 659#define ACOSV_SLV8 0x00000020 660#define ACOSV_SLV9 0x00000040 661#define ACOSV_SLV10 0x00000080 662#define ACOSV_SLV11 0x00000100 663#define ACOSV_SLV12 0x00000200 664 665/* 666 * The following defines are for the flags in the AC97 command address 667 * register. 668 */ 669#define ACCAD_CI_MASK 0x0000007F 670#define ACCAD_CI_SHIFT 0 671 672/* 673 * The following defines are for the flags in the AC97 command data register. 674 */ 675#define ACCDA_CD_MASK 0x0000FFFF 676#define ACCDA_CD_SHIFT 0 677 678/* 679 * The following defines are for the flags in the AC97 input slot valid 680 * register. 681 */ 682#define ACISV_ISV3 0x00000001 683#define ACISV_ISV4 0x00000002 684#define ACISV_ISV5 0x00000004 685#define ACISV_ISV6 0x00000008 686#define ACISV_ISV7 0x00000010 687#define ACISV_ISV8 0x00000020 688#define ACISV_ISV9 0x00000040 689#define ACISV_ISV10 0x00000080 690#define ACISV_ISV11 0x00000100 691#define ACISV_ISV12 0x00000200 692 693/* 694 * The following defines are for the flags in the AC97 status address 695 * register. 696 */ 697#define ACSAD_SI_MASK 0x0000007F 698#define ACSAD_SI_SHIFT 0 699 700/* 701 * The following defines are for the flags in the AC97 status data register. 702 */ 703#define ACSDA_SD_MASK 0x0000FFFF 704#define ACSDA_SD_SHIFT 0 705 706/* 707 * The following defines are for the flags in the joystick poll/trigger 708 * register. 709 */ 710#define JSPT_CAX 0x00000001 711#define JSPT_CAY 0x00000002 712#define JSPT_CBX 0x00000004 713#define JSPT_CBY 0x00000008 714#define JSPT_BA1 0x00000010 715#define JSPT_BA2 0x00000020 716#define JSPT_BB1 0x00000040 717#define JSPT_BB2 0x00000080 718 719/* 720 * The following defines are for the flags in the joystick control register. 721 */ 722#define JSCTL_SP_MASK 0x00000003 723#define JSCTL_SP_SLOW 0x00000000 724#define JSCTL_SP_MEDIUM_SLOW 0x00000001 725#define JSCTL_SP_MEDIUM_FAST 0x00000002 726#define JSCTL_SP_FAST 0x00000003 727#define JSCTL_ARE 0x00000004 728 729/* 730 * The following defines are for the flags in the joystick coordinate pair 1 731 * readback register. 732 */ 733#define JSC1_Y1V_MASK 0x0000FFFF 734#define JSC1_X1V_MASK 0xFFFF0000 735#define JSC1_Y1V_SHIFT 0 736#define JSC1_X1V_SHIFT 16 737 738/* 739 * The following defines are for the flags in the joystick coordinate pair 2 740 * readback register. 741 */ 742#define JSC2_Y2V_MASK 0x0000FFFF 743#define JSC2_X2V_MASK 0xFFFF0000 744#define JSC2_Y2V_SHIFT 0 745#define JSC2_X2V_SHIFT 16 746 747/* 748 * The following defines are for the flags in the MIDI control register. 749 */ 750#define MIDCR_TXE 0x00000001 /* Enable transmitting. */ 751#define MIDCR_RXE 0x00000002 /* Enable receiving. */ 752#define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */ 753#define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */ 754#define MIDCR_MLB 0x00000010 /* Enable midi loopback. */ 755#define MIDCR_MRST 0x00000020 /* Reset interface. */ 756 757/* 758 * The following defines are for the flags in the MIDI status register. 759 */ 760#define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */ 761#define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */ 762 763/* 764 * The following defines are for the flags in the MIDI write port register. 765 */ 766#define MIDWP_MWD_MASK 0x000000FF 767#define MIDWP_MWD_SHIFT 0 768 769/* 770 * The following defines are for the flags in the MIDI read port register. 771 */ 772#define MIDRP_MRD_MASK 0x000000FF 773#define MIDRP_MRD_SHIFT 0 774 775/* 776 * The following defines are for the flags in the joystick GPIO register. 777 */ 778#define JSIO_DAX 0x00000001 779#define JSIO_DAY 0x00000002 780#define JSIO_DBX 0x00000004 781#define JSIO_DBY 0x00000008 782#define JSIO_AXOE 0x00000010 783#define JSIO_AYOE 0x00000020 784#define JSIO_BXOE 0x00000040 785#define JSIO_BYOE 0x00000080 786 787/* 788 * The following defines are for the flags in the master async/sync serial 789 * port enable register. 790 */ 791#ifndef NO_CS4612 792#define ASER_MASTER_ME 0x00000001 793#endif 794 795/* 796 * The following defines are for the flags in the configuration interface 797 * register. 798 */ 799#define CFGI_CLK 0x00000001 800#define CFGI_DOUT 0x00000002 801#define CFGI_DIN_EEN 0x00000004 802#define CFGI_EELD 0x00000008 803 804/* 805 * The following defines are for the flags in the subsystem ID and vendor ID 806 * register. 807 */ 808#define SSVID_VID_MASK 0x0000FFFF 809#define SSVID_SID_MASK 0xFFFF0000 810#define SSVID_VID_SHIFT 0 811#define SSVID_SID_SHIFT 16 812 813/* 814 * The following defines are for the flags in the GPIO pin interface register. 815 */ 816#define GPIOR_VOLDN 0x00000001 817#define GPIOR_VOLUP 0x00000002 818#define GPIOR_SI2D 0x00000004 819#define GPIOR_SI2OE 0x00000008 820 821/* 822 * The following defines are for the flags in the extended GPIO pin direction 823 * register. 824 */ 825#ifndef NO_CS4612 826#define EGPIODR_GPOE0 0x00000001 827#define EGPIODR_GPOE1 0x00000002 828#define EGPIODR_GPOE2 0x00000004 829#define EGPIODR_GPOE3 0x00000008 830#define EGPIODR_GPOE4 0x00000010 831#define EGPIODR_GPOE5 0x00000020 832#define EGPIODR_GPOE6 0x00000040 833#define EGPIODR_GPOE7 0x00000080 834#define EGPIODR_GPOE8 0x00000100 835#endif 836 837/* 838 * The following defines are for the flags in the extended GPIO pin polarity/ 839 * type register. 840 */ 841#ifndef NO_CS4612 842#define EGPIOPTR_GPPT0 0x00000001 843#define EGPIOPTR_GPPT1 0x00000002 844#define EGPIOPTR_GPPT2 0x00000004 845#define EGPIOPTR_GPPT3 0x00000008 846#define EGPIOPTR_GPPT4 0x00000010 847#define EGPIOPTR_GPPT5 0x00000020 848#define EGPIOPTR_GPPT6 0x00000040 849#define EGPIOPTR_GPPT7 0x00000080 850#define EGPIOPTR_GPPT8 0x00000100 851#endif 852 853/* 854 * The following defines are for the flags in the extended GPIO pin sticky 855 * register. 856 */ 857#ifndef NO_CS4612 858#define EGPIOTR_GPS0 0x00000001 859#define EGPIOTR_GPS1 0x00000002 860#define EGPIOTR_GPS2 0x00000004 861#define EGPIOTR_GPS3 0x00000008 862#define EGPIOTR_GPS4 0x00000010 863#define EGPIOTR_GPS5 0x00000020 864#define EGPIOTR_GPS6 0x00000040 865#define EGPIOTR_GPS7 0x00000080 866#define EGPIOTR_GPS8 0x00000100 867#endif 868 869/* 870 * The following defines are for the flags in the extended GPIO ping wakeup 871 * register. 872 */ 873#ifndef NO_CS4612 874#define EGPIOWR_GPW0 0x00000001 875#define EGPIOWR_GPW1 0x00000002 876#define EGPIOWR_GPW2 0x00000004 877#define EGPIOWR_GPW3 0x00000008 878#define EGPIOWR_GPW4 0x00000010 879#define EGPIOWR_GPW5 0x00000020 880#define EGPIOWR_GPW6 0x00000040 881#define EGPIOWR_GPW7 0x00000080 882#define EGPIOWR_GPW8 0x00000100 883#endif 884 885/* 886 * The following defines are for the flags in the extended GPIO pin status 887 * register. 888 */ 889#ifndef NO_CS4612 890#define EGPIOSR_GPS0 0x00000001 891#define EGPIOSR_GPS1 0x00000002 892#define EGPIOSR_GPS2 0x00000004 893#define EGPIOSR_GPS3 0x00000008 894#define EGPIOSR_GPS4 0x00000010 895#define EGPIOSR_GPS5 0x00000020 896#define EGPIOSR_GPS6 0x00000040 897#define EGPIOSR_GPS7 0x00000080 898#define EGPIOSR_GPS8 0x00000100 899#endif 900 901/* 902 * The following defines are for the flags in the serial port 6 configuration 903 * register. 904 */ 905#ifndef NO_CS4612 906#define SERC6_ASDO2EN 0x00000001 907#endif 908 909/* 910 * The following defines are for the flags in the serial port 7 configuration 911 * register. 912 */ 913#ifndef NO_CS4612 914#define SERC7_ASDI2EN 0x00000001 915#define SERC7_POSILB 0x00000002 916#define SERC7_SIPOLB 0x00000004 917#define SERC7_SOSILB 0x00000008 918#define SERC7_SISOLB 0x00000010 919#endif 920 921/* 922 * The following defines are for the flags in the serial port AC link 923 * configuration register. 924 */ 925#ifndef NO_CS4612 926#define SERACC_CHIP_TYPE_MASK 0x00000001 927#define SERACC_CHIP_TYPE_1_03 0x00000000 928#define SERACC_CHIP_TYPE_2_0 0x00000001 929#define SERACC_TWO_CODECS 0x00000002 930#define SERACC_MDM 0x00000004 931#define SERACC_HSP 0x00000008 932#define SERACC_ODT 0x00000010 /* only CS4630 */ 933#endif 934 935/* 936 * The following defines are for the flags in the AC97 control register 2. 937 */ 938#ifndef NO_CS4612 939#define ACCTL2_RSTN 0x00000001 940#define ACCTL2_ESYN 0x00000002 941#define ACCTL2_VFRM 0x00000004 942#define ACCTL2_DCV 0x00000008 943#define ACCTL2_CRW 0x00000010 944#define ACCTL2_ASYN 0x00000020 945#endif 946 947/* 948 * The following defines are for the flags in the AC97 status register 2. 949 */ 950#ifndef NO_CS4612 951#define ACSTS2_CRDY 0x00000001 952#define ACSTS2_VSTS 0x00000002 953#endif 954 955/* 956 * The following defines are for the flags in the AC97 output slot valid 957 * register 2. 958 */ 959#ifndef NO_CS4612 960#define ACOSV2_SLV3 0x00000001 961#define ACOSV2_SLV4 0x00000002 962#define ACOSV2_SLV5 0x00000004 963#define ACOSV2_SLV6 0x00000008 964#define ACOSV2_SLV7 0x00000010 965#define ACOSV2_SLV8 0x00000020 966#define ACOSV2_SLV9 0x00000040 967#define ACOSV2_SLV10 0x00000080 968#define ACOSV2_SLV11 0x00000100 969#define ACOSV2_SLV12 0x00000200 970#endif 971 972/* 973 * The following defines are for the flags in the AC97 command address 974 * register 2. 975 */ 976#ifndef NO_CS4612 977#define ACCAD2_CI_MASK 0x0000007F 978#define ACCAD2_CI_SHIFT 0 979#endif 980 981/* 982 * The following defines are for the flags in the AC97 command data register 983 * 2. 984 */ 985#ifndef NO_CS4612 986#define ACCDA2_CD_MASK 0x0000FFFF 987#define ACCDA2_CD_SHIFT 0 988#endif 989 990/* 991 * The following defines are for the flags in the AC97 input slot valid 992 * register 2. 993 */ 994#ifndef NO_CS4612 995#define ACISV2_ISV3 0x00000001 996#define ACISV2_ISV4 0x00000002 997#define ACISV2_ISV5 0x00000004 998#define ACISV2_ISV6 0x00000008 999#define ACISV2_ISV7 0x00000010 1000#define ACISV2_ISV8 0x00000020 1001#define ACISV2_ISV9 0x00000040 1002#define ACISV2_ISV10 0x00000080 1003#define ACISV2_ISV11 0x00000100 1004#define ACISV2_ISV12 0x00000200 1005#endif 1006 1007/* 1008 * The following defines are for the flags in the AC97 status address 1009 * register 2. 1010 */ 1011#ifndef NO_CS4612 1012#define ACSAD2_SI_MASK 0x0000007F 1013#define ACSAD2_SI_SHIFT 0 1014#endif 1015 1016/* 1017 * The following defines are for the flags in the AC97 status data register 2. 1018 */ 1019#ifndef NO_CS4612 1020#define ACSDA2_SD_MASK 0x0000FFFF 1021#define ACSDA2_SD_SHIFT 0 1022#endif 1023 1024/* 1025 * The following defines are for the flags in the I/O trap address and control 1026 * registers (all 12). 1027 */ 1028#ifndef NO_CS4612 1029#define IOTAC_SA_MASK 0x0000FFFF 1030#define IOTAC_MSK_MASK 0x000F0000 1031#define IOTAC_IODC_MASK 0x06000000 1032#define IOTAC_IODC_16_BIT 0x00000000 1033#define IOTAC_IODC_10_BIT 0x02000000 1034#define IOTAC_IODC_12_BIT 0x04000000 1035#define IOTAC_WSPI 0x08000000 1036#define IOTAC_RSPI 0x10000000 1037#define IOTAC_WSE 0x20000000 1038#define IOTAC_WE 0x40000000 1039#define IOTAC_RE 0x80000000 1040#define IOTAC_SA_SHIFT 0 1041#define IOTAC_MSK_SHIFT 16 1042#endif 1043 1044/* 1045 * The following defines are for the flags in the I/O trap fast read registers 1046 * (all 8). 1047 */ 1048#ifndef NO_CS4612 1049#define IOTFR_D_MASK 0x0000FFFF 1050#define IOTFR_A_MASK 0x000F0000 1051#define IOTFR_R_MASK 0x0F000000 1052#define IOTFR_ALL 0x40000000 1053#define IOTFR_VL 0x80000000 1054#define IOTFR_D_SHIFT 0 1055#define IOTFR_A_SHIFT 16 1056#define IOTFR_R_SHIFT 24 1057#endif 1058 1059/* 1060 * The following defines are for the flags in the I/O trap FIFO register. 1061 */ 1062#ifndef NO_CS4612 1063#define IOTFIFO_BA_MASK 0x00003FFF 1064#define IOTFIFO_S_MASK 0x00FF0000 1065#define IOTFIFO_OF 0x40000000 1066#define IOTFIFO_SPIOF 0x80000000 1067#define IOTFIFO_BA_SHIFT 0 1068#define IOTFIFO_S_SHIFT 16 1069#endif 1070 1071/* 1072 * The following defines are for the flags in the I/O trap retry read data 1073 * register. 1074 */ 1075#ifndef NO_CS4612 1076#define IOTRRD_D_MASK 0x0000FFFF 1077#define IOTRRD_RDV 0x80000000 1078#define IOTRRD_D_SHIFT 0 1079#endif 1080 1081/* 1082 * The following defines are for the flags in the I/O trap FIFO pointer 1083 * register. 1084 */ 1085#ifndef NO_CS4612 1086#define IOTFP_CA_MASK 0x00003FFF 1087#define IOTFP_PA_MASK 0x3FFF0000 1088#define IOTFP_CA_SHIFT 0 1089#define IOTFP_PA_SHIFT 16 1090#endif 1091 1092/* 1093 * The following defines are for the flags in the I/O trap control register. 1094 */ 1095#ifndef NO_CS4612 1096#define IOTCR_ITD 0x00000001 1097#define IOTCR_HRV 0x00000002 1098#define IOTCR_SRV 0x00000004 1099#define IOTCR_DTI 0x00000008 1100#define IOTCR_DFI 0x00000010 1101#define IOTCR_DDP 0x00000020 1102#define IOTCR_JTE 0x00000040 1103#define IOTCR_PPE 0x00000080 1104#endif 1105 1106/* 1107 * The following defines are for the flags in the direct PCI data register. 1108 */ 1109#ifndef NO_CS4612 1110#define DPCID_D_MASK 0xFFFFFFFF 1111#define DPCID_D_SHIFT 0 1112#endif 1113 1114/* 1115 * The following defines are for the flags in the direct PCI address register. 1116 */ 1117#ifndef NO_CS4612 1118#define DPCIA_A_MASK 0xFFFFFFFF 1119#define DPCIA_A_SHIFT 0 1120#endif 1121 1122/* 1123 * The following defines are for the flags in the direct PCI command register. 1124 */ 1125#ifndef NO_CS4612 1126#define DPCIC_C_MASK 0x0000000F 1127#define DPCIC_C_IOREAD 0x00000002 1128#define DPCIC_C_IOWRITE 0x00000003 1129#define DPCIC_BE_MASK 0x000000F0 1130#endif 1131 1132/* 1133 * The following defines are for the flags in the PC/PCI request register. 1134 */ 1135#ifndef NO_CS4612 1136#define PCPCIR_RDC_MASK 0x00000007 1137#define PCPCIR_C_MASK 0x00007000 1138#define PCPCIR_REQ 0x00008000 1139#define PCPCIR_RDC_SHIFT 0 1140#define PCPCIR_C_SHIFT 12 1141#endif 1142 1143/* 1144 * The following defines are for the flags in the PC/PCI grant register. 1145 */ 1146#ifndef NO_CS4612 1147#define PCPCIG_GDC_MASK 0x00000007 1148#define PCPCIG_VL 0x00008000 1149#define PCPCIG_GDC_SHIFT 0 1150#endif 1151 1152/* 1153 * The following defines are for the flags in the PC/PCI master enable 1154 * register. 1155 */ 1156#ifndef NO_CS4612 1157#define PCPCIEN_EN 0x00000001 1158#endif 1159 1160/* 1161 * The following defines are for the flags in the extended PCI power 1162 * management control register. 1163 */ 1164#ifndef NO_CS4612 1165#define EPCIPMC_GWU 0x00000001 1166#define EPCIPMC_FSPC 0x00000002 1167#endif 1168 1169/* 1170 * The following defines are for the flags in the SP control register. 1171 */ 1172#define SPCR_RUN 0x00000001 1173#define SPCR_STPFR 0x00000002 1174#define SPCR_RUNFR 0x00000004 1175#define SPCR_TICK 0x00000008 1176#define SPCR_DRQEN 0x00000020 1177#define SPCR_RSTSP 0x00000040 1178#define SPCR_OREN 0x00000080 1179#ifndef NO_CS4612 1180#define SPCR_PCIINT 0x00000100 1181#define SPCR_OINTD 0x00000200 1182#define SPCR_CRE 0x00008000 1183#endif 1184 1185/* 1186 * The following defines are for the flags in the debug index register. 1187 */ 1188#define DREG_REGID_MASK 0x0000007F 1189#define DREG_DEBUG 0x00000080 1190#define DREG_RGBK_MASK 0x00000700 1191#define DREG_TRAP 0x00000800 1192#if !defined(NO_CS4612) 1193#if !defined(NO_CS4615) 1194#define DREG_TRAPX 0x00001000 1195#endif 1196#endif 1197#define DREG_REGID_SHIFT 0 1198#define DREG_RGBK_SHIFT 8 1199#define DREG_RGBK_REGID_MASK 0x0000077F 1200#define DREG_REGID_R0 0x00000010 1201#define DREG_REGID_R1 0x00000011 1202#define DREG_REGID_R2 0x00000012 1203#define DREG_REGID_R3 0x00000013 1204#define DREG_REGID_R4 0x00000014 1205#define DREG_REGID_R5 0x00000015 1206#define DREG_REGID_R6 0x00000016 1207#define DREG_REGID_R7 0x00000017 1208#define DREG_REGID_R8 0x00000018 1209#define DREG_REGID_R9 0x00000019 1210#define DREG_REGID_RA 0x0000001A 1211#define DREG_REGID_RB 0x0000001B 1212#define DREG_REGID_RC 0x0000001C 1213#define DREG_REGID_RD 0x0000001D 1214#define DREG_REGID_RE 0x0000001E 1215#define DREG_REGID_RF 0x0000001F 1216#define DREG_REGID_RA_BUS_LOW 0x00000020 1217#define DREG_REGID_RA_BUS_HIGH 0x00000038 1218#define DREG_REGID_YBUS_LOW 0x00000050 1219#define DREG_REGID_YBUS_HIGH 0x00000058 1220#define DREG_REGID_TRAP_0 0x00000100 1221#define DREG_REGID_TRAP_1 0x00000101 1222#define DREG_REGID_TRAP_2 0x00000102 1223#define DREG_REGID_TRAP_3 0x00000103 1224#define DREG_REGID_TRAP_4 0x00000104 1225#define DREG_REGID_TRAP_5 0x00000105 1226#define DREG_REGID_TRAP_6 0x00000106 1227#define DREG_REGID_TRAP_7 0x00000107 1228#define DREG_REGID_INDIRECT_ADDRESS 0x0000010E 1229#define DREG_REGID_TOP_OF_STACK 0x0000010F 1230#if !defined(NO_CS4612) 1231#if !defined(NO_CS4615) 1232#define DREG_REGID_TRAP_8 0x00000110 1233#define DREG_REGID_TRAP_9 0x00000111 1234#define DREG_REGID_TRAP_10 0x00000112 1235#define DREG_REGID_TRAP_11 0x00000113 1236#define DREG_REGID_TRAP_12 0x00000114 1237#define DREG_REGID_TRAP_13 0x00000115 1238#define DREG_REGID_TRAP_14 0x00000116 1239#define DREG_REGID_TRAP_15 0x00000117 1240#define DREG_REGID_TRAP_16 0x00000118 1241#define DREG_REGID_TRAP_17 0x00000119 1242#define DREG_REGID_TRAP_18 0x0000011A 1243#define DREG_REGID_TRAP_19 0x0000011B 1244#define DREG_REGID_TRAP_20 0x0000011C 1245#define DREG_REGID_TRAP_21 0x0000011D 1246#define DREG_REGID_TRAP_22 0x0000011E 1247#define DREG_REGID_TRAP_23 0x0000011F 1248#endif 1249#endif 1250#define DREG_REGID_RSA0_LOW 0x00000200 1251#define DREG_REGID_RSA0_HIGH 0x00000201 1252#define DREG_REGID_RSA1_LOW 0x00000202 1253#define DREG_REGID_RSA1_HIGH 0x00000203 1254#define DREG_REGID_RSA2 0x00000204 1255#define DREG_REGID_RSA3 0x00000205 1256#define DREG_REGID_RSI0_LOW 0x00000206 1257#define DREG_REGID_RSI0_HIGH 0x00000207 1258#define DREG_REGID_RSI1 0x00000208 1259#define DREG_REGID_RSI2 0x00000209 1260#define DREG_REGID_SAGUSTATUS 0x0000020A 1261#define DREG_REGID_RSCONFIG01_LOW 0x0000020B 1262#define DREG_REGID_RSCONFIG01_HIGH 0x0000020C 1263#define DREG_REGID_RSCONFIG23_LOW 0x0000020D 1264#define DREG_REGID_RSCONFIG23_HIGH 0x0000020E 1265#define DREG_REGID_RSDMA01E 0x0000020F 1266#define DREG_REGID_RSDMA23E 0x00000210 1267#define DREG_REGID_RSD0_LOW 0x00000211 1268#define DREG_REGID_RSD0_HIGH 0x00000212 1269#define DREG_REGID_RSD1_LOW 0x00000213 1270#define DREG_REGID_RSD1_HIGH 0x00000214 1271#define DREG_REGID_RSD2_LOW 0x00000215 1272#define DREG_REGID_RSD2_HIGH 0x00000216 1273#define DREG_REGID_RSD3_LOW 0x00000217 1274#define DREG_REGID_RSD3_HIGH 0x00000218 1275#define DREG_REGID_SRAR_HIGH 0x0000021A 1276#define DREG_REGID_SRAR_LOW 0x0000021B 1277#define DREG_REGID_DMA_STATE 0x0000021C 1278#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D 1279#define DREG_REGID_NEXT_DMA_STREAM 0x0000021E 1280#define DREG_REGID_CPU_STATUS 0x00000300 1281#define DREG_REGID_MAC_MODE 0x00000301 1282#define DREG_REGID_STACK_AND_REPEAT 0x00000302 1283#define DREG_REGID_INDEX0 0x00000304 1284#define DREG_REGID_INDEX1 0x00000305 1285#define DREG_REGID_DMA_STATE_0_3 0x00000400 1286#define DREG_REGID_DMA_STATE_4_7 0x00000404 1287#define DREG_REGID_DMA_STATE_8_11 0x00000408 1288#define DREG_REGID_DMA_STATE_12_15 0x0000040C 1289#define DREG_REGID_DMA_STATE_16_19 0x00000410 1290#define DREG_REGID_DMA_STATE_20_23 0x00000414 1291#define DREG_REGID_DMA_STATE_24_27 0x00000418 1292#define DREG_REGID_DMA_STATE_28_31 0x0000041C 1293#define DREG_REGID_DMA_STATE_32_35 0x00000420 1294#define DREG_REGID_DMA_STATE_36_39 0x00000424 1295#define DREG_REGID_DMA_STATE_40_43 0x00000428 1296#define DREG_REGID_DMA_STATE_44_47 0x0000042C 1297#define DREG_REGID_DMA_STATE_48_51 0x00000430 1298#define DREG_REGID_DMA_STATE_52_55 0x00000434 1299#define DREG_REGID_DMA_STATE_56_59 0x00000438 1300#define DREG_REGID_DMA_STATE_60_63 0x0000043C 1301#define DREG_REGID_DMA_STATE_64_67 0x00000440 1302#define DREG_REGID_DMA_STATE_68_71 0x00000444 1303#define DREG_REGID_DMA_STATE_72_75 0x00000448 1304#define DREG_REGID_DMA_STATE_76_79 0x0000044C 1305#define DREG_REGID_DMA_STATE_80_83 0x00000450 1306#define DREG_REGID_DMA_STATE_84_87 0x00000454 1307#define DREG_REGID_DMA_STATE_88_91 0x00000458 1308#define DREG_REGID_DMA_STATE_92_95 0x0000045C 1309#define DREG_REGID_TRAP_SELECT 0x00000500 1310#define DREG_REGID_TRAP_WRITE_0 0x00000500 1311#define DREG_REGID_TRAP_WRITE_1 0x00000501 1312#define DREG_REGID_TRAP_WRITE_2 0x00000502 1313#define DREG_REGID_TRAP_WRITE_3 0x00000503 1314#define DREG_REGID_TRAP_WRITE_4 0x00000504 1315#define DREG_REGID_TRAP_WRITE_5 0x00000505 1316#define DREG_REGID_TRAP_WRITE_6 0x00000506 1317#define DREG_REGID_TRAP_WRITE_7 0x00000507 1318#if !defined(NO_CS4612) 1319#if !defined(NO_CS4615) 1320#define DREG_REGID_TRAP_WRITE_8 0x00000510 1321#define DREG_REGID_TRAP_WRITE_9 0x00000511 1322#define DREG_REGID_TRAP_WRITE_10 0x00000512 1323#define DREG_REGID_TRAP_WRITE_11 0x00000513 1324#define DREG_REGID_TRAP_WRITE_12 0x00000514 1325#define DREG_REGID_TRAP_WRITE_13 0x00000515 1326#define DREG_REGID_TRAP_WRITE_14 0x00000516 1327#define DREG_REGID_TRAP_WRITE_15 0x00000517 1328#define DREG_REGID_TRAP_WRITE_16 0x00000518 1329#define DREG_REGID_TRAP_WRITE_17 0x00000519 1330#define DREG_REGID_TRAP_WRITE_18 0x0000051A 1331#define DREG_REGID_TRAP_WRITE_19 0x0000051B 1332#define DREG_REGID_TRAP_WRITE_20 0x0000051C 1333#define DREG_REGID_TRAP_WRITE_21 0x0000051D 1334#define DREG_REGID_TRAP_WRITE_22 0x0000051E 1335#define DREG_REGID_TRAP_WRITE_23 0x0000051F 1336#endif 1337#endif 1338#define DREG_REGID_MAC0_ACC0_LOW 0x00000600 1339#define DREG_REGID_MAC0_ACC1_LOW 0x00000601 1340#define DREG_REGID_MAC0_ACC2_LOW 0x00000602 1341#define DREG_REGID_MAC0_ACC3_LOW 0x00000603 1342#define DREG_REGID_MAC1_ACC0_LOW 0x00000604 1343#define DREG_REGID_MAC1_ACC1_LOW 0x00000605 1344#define DREG_REGID_MAC1_ACC2_LOW 0x00000606 1345#define DREG_REGID_MAC1_ACC3_LOW 0x00000607 1346#define DREG_REGID_MAC0_ACC0_MID 0x00000608 1347#define DREG_REGID_MAC0_ACC1_MID 0x00000609 1348#define DREG_REGID_MAC0_ACC2_MID 0x0000060A 1349#define DREG_REGID_MAC0_ACC3_MID 0x0000060B 1350#define DREG_REGID_MAC1_ACC0_MID 0x0000060C 1351#define DREG_REGID_MAC1_ACC1_MID 0x0000060D 1352#define DREG_REGID_MAC1_ACC2_MID 0x0000060E 1353#define DREG_REGID_MAC1_ACC3_MID 0x0000060F 1354#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610 1355#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611 1356#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612 1357#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613 1358#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614 1359#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615 1360#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616 1361#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617 1362#define DREG_REGID_RSHOUT_LOW 0x00000620 1363#define DREG_REGID_RSHOUT_MID 0x00000628 1364#define DREG_REGID_RSHOUT_HIGH 0x00000630 1365 1366/* 1367 * The following defines are for the flags in the DMA stream requestor write 1368 */ 1369#define DSRWP_DSR_MASK 0x0000000F 1370#define DSRWP_DSR_BG_RQ 0x00000001 1371#define DSRWP_DSR_PRIORITY_MASK 0x00000006 1372#define DSRWP_DSR_PRIORITY_0 0x00000000 1373#define DSRWP_DSR_PRIORITY_1 0x00000002 1374#define DSRWP_DSR_PRIORITY_2 0x00000004 1375#define DSRWP_DSR_PRIORITY_3 0x00000006 1376#define DSRWP_DSR_RQ_PENDING 0x00000008 1377 1378/* 1379 * The following defines are for the flags in the trap write port register. 1380 */ 1381#define TWPR_TW_MASK 0x0000FFFF 1382#define TWPR_TW_SHIFT 0 1383 1384/* 1385 * The following defines are for the flags in the stack pointer write 1386 * register. 1387 */ 1388#define SPWR_STKP_MASK 0x0000000F 1389#define SPWR_STKP_SHIFT 0 1390 1391/* 1392 * The following defines are for the flags in the SP interrupt register. 1393 */ 1394#define SPIR_FRI 0x00000001 1395#define SPIR_DOI 0x00000002 1396#define SPIR_GPI2 0x00000004 1397#define SPIR_GPI3 0x00000008 1398#define SPIR_IP0 0x00000010 1399#define SPIR_IP1 0x00000020 1400#define SPIR_IP2 0x00000040 1401#define SPIR_IP3 0x00000080 1402 1403/* 1404 * The following defines are for the flags in the functional group 1 register. 1405 */ 1406#define FGR1_F1S_MASK 0x0000FFFF 1407#define FGR1_F1S_SHIFT 0 1408 1409/* 1410 * The following defines are for the flags in the SP clock status register. 1411 */ 1412#define SPCS_FRI 0x00000001 1413#define SPCS_DOI 0x00000002 1414#define SPCS_GPI2 0x00000004 1415#define SPCS_GPI3 0x00000008 1416#define SPCS_IP0 0x00000010 1417#define SPCS_IP1 0x00000020 1418#define SPCS_IP2 0x00000040 1419#define SPCS_IP3 0x00000080 1420#define SPCS_SPRUN 0x00000100 1421#define SPCS_SLEEP 0x00000200 1422#define SPCS_FG 0x00000400 1423#define SPCS_ORUN 0x00000800 1424#define SPCS_IRQ 0x00001000 1425#define SPCS_FGN_MASK 0x0000E000 1426#define SPCS_FGN_SHIFT 13 1427 1428/* 1429 * The following defines are for the flags in the SP DMA requestor status 1430 * register. 1431 */ 1432#define SDSR_DCS_MASK 0x000000FF 1433#define SDSR_DCS_SHIFT 0 1434#define SDSR_DCS_NONE 0x00000007 1435 1436/* 1437 * The following defines are for the flags in the frame timer register. 1438 */ 1439#define FRMT_FTV_MASK 0x0000FFFF 1440#define FRMT_FTV_SHIFT 0 1441 1442/* 1443 * The following defines are for the flags in the frame timer current count 1444 * register. 1445 */ 1446#define FRCC_FCC_MASK 0x0000FFFF 1447#define FRCC_FCC_SHIFT 0 1448 1449/* 1450 * The following defines are for the flags in the frame timer save count 1451 * register. 1452 */ 1453#define FRSC_FCS_MASK 0x0000FFFF 1454#define FRSC_FCS_SHIFT 0 1455 1456/* 1457 * The following define the various flags stored in the scatter/gather 1458 * descriptors. 1459 */ 1460#define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8 1461#define DMA_SG_SAMPLE_END_MASK 0x0FFF0000 1462#define DMA_SG_SAMPLE_END_FLAG 0x10000000 1463#define DMA_SG_LOOP_END_FLAG 0x20000000 1464#define DMA_SG_SIGNAL_END_FLAG 0x40000000 1465#define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000 1466#define DMA_SG_NEXT_ENTRY_SHIFT 3 1467#define DMA_SG_SAMPLE_END_SHIFT 16 1468 1469/* 1470 * The following define the offsets of the fields within the on-chip generic 1471 * DMA requestor. 1472 */ 1473#define DMA_RQ_CONTROL1 0x00000000 1474#define DMA_RQ_CONTROL2 0x00000004 1475#define DMA_RQ_SOURCE_ADDR 0x00000008 1476#define DMA_RQ_DESTINATION_ADDR 0x0000000C 1477#define DMA_RQ_NEXT_PAGE_ADDR 0x00000010 1478#define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014 1479#define DMA_RQ_LOOP_START_ADDR 0x00000018 1480#define DMA_RQ_POST_LOOP_ADDR 0x0000001C 1481#define DMA_RQ_PAGE_MAP_ADDR 0x00000020 1482 1483/* 1484 * The following defines are for the flags in the first control word of the 1485 * on-chip generic DMA requestor. 1486 */ 1487#define DMA_RQ_C1_COUNT_MASK 0x000003FF 1488#define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000 1489#define DMA_RQ_C1_SOURCE_GATHER 0x00002000 1490#define DMA_RQ_C1_DONE_FLAG 0x00004000 1491#define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000 1492#define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000 1493#define DMA_RQ_C1_FULL_PAGE 0x00000000 1494#define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000 1495#define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000 1496#define DMA_RQ_C1_AT_SAMPLE_END 0x00030000 1497#define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000 1498#define DMA_RQ_C1_NOT_LOOP_END 0x00000000 1499#define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000 1500#define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000 1501#define DMA_RQ_C1_LOOP_BEGIN 0x000C0000 1502#define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000 1503#define DMA_RQ_C1_PM_NONE_PENDING 0x00000000 1504#define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000 1505#define DMA_RQ_C1_PM_RESERVED 0x00200000 1506#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000 1507#define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000 1508#define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000 1509#define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000 1510#define DMA_RQ_C1_DEST_LINEAR 0x00000000 1511#define DMA_RQ_C1_DEST_MOD16 0x01000000 1512#define DMA_RQ_C1_DEST_MOD32 0x02000000 1513#define DMA_RQ_C1_DEST_MOD64 0x03000000 1514#define DMA_RQ_C1_DEST_MOD128 0x04000000 1515#define DMA_RQ_C1_DEST_MOD256 0x05000000 1516#define DMA_RQ_C1_DEST_MOD512 0x06000000 1517#define DMA_RQ_C1_DEST_MOD1024 0x07000000 1518#define DMA_RQ_C1_DEST_ON_HOST 0x08000000 1519#define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000 1520#define DMA_RQ_C1_SOURCE_LINEAR 0x00000000 1521#define DMA_RQ_C1_SOURCE_MOD16 0x10000000 1522#define DMA_RQ_C1_SOURCE_MOD32 0x20000000 1523#define DMA_RQ_C1_SOURCE_MOD64 0x30000000 1524#define DMA_RQ_C1_SOURCE_MOD128 0x40000000 1525#define DMA_RQ_C1_SOURCE_MOD256 0x50000000 1526#define DMA_RQ_C1_SOURCE_MOD512 0x60000000 1527#define DMA_RQ_C1_SOURCE_MOD1024 0x70000000 1528#define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000 1529#define DMA_RQ_C1_COUNT_SHIFT 0 1530 1531/* 1532 * The following defines are for the flags in the second control word of the 1533 * on-chip generic DMA requestor. 1534 */ 1535#define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F 1536#define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300 1537#define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000 1538#define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100 1539#define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200 1540#define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300 1541#define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000 1542#define DMA_RQ_C2_AC_NONE 0x00000000 1543#define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000 1544#define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000 1545#define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000 1546#define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000 1547#define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000 1548#define DMA_RQ_C2_LOOP_MASK 0x30000000 1549#define DMA_RQ_C2_NO_LOOP 0x00000000 1550#define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000 1551#define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000 1552#define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000 1553#define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000 1554#define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000 1555#define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0 1556#define DMA_RQ_C2_LOOP_END_SHIFT 16 1557 1558/* 1559 * The following defines are for the flags in the source and destination words 1560 * of the on-chip generic DMA requestor. 1561 */ 1562#define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF 1563#define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000 1564#define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000 1565#define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000 1566#define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000 1567#define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000 1568#define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000 1569#define DMA_RQ_SD_END_FLAG 0x40000000 1570#define DMA_RQ_SD_ERROR_FLAG 0x80000000 1571#define DMA_RQ_SD_ADDRESS_SHIFT 0 1572 1573/* 1574 * The following defines are for the flags in the page map address word of the 1575 * on-chip generic DMA requestor. 1576 */ 1577#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8 1578#define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000 1579#define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3 1580#define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12 1581 1582#define BA1_VARIDEC_BUF_1 0x000 1583 1584#define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */ 1585#define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */ 1586#define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */ 1587#define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */ 1588#define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */ 1589#define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */ 1590#define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */ 1591 1592#define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */ 1593#define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */ 1594#define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */ 1595#define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */ 1596#define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */ 1597#define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */ 1598#define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */ 1599#define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */ 1600 1601#define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */ 1602#define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */ 1603#define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */ 1604#define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */ 1605 1606/* 1607 * 1608 */ 1609 1610#define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */ 1611#define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */ 1612 1613/* 1614 * 1615 */ 1616 1617#define SAVE_REG_MAX 0x10 1618#define POWER_DOWN_ALL 0x7f0f 1619 1620/* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */ 1621#define MAX_NR_AC97 4 1622#define CS46XX_PRIMARY_CODEC_INDEX 0 1623#define CS46XX_SECONDARY_CODEC_INDEX 1 1624#define CS46XX_SECONDARY_CODEC_OFFSET 0x80 1625#define CS46XX_DSP_CAPTURE_CHANNEL 1 1626 1627/* capture */ 1628#define CS46XX_DSP_CAPTURE_CHANNEL 1 1629 1630/* mixer */ 1631#define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 1 1632#define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 2 1633 1634 1635struct snd_cs46xx_pcm { 1636 struct snd_dma_buffer hw_buf; 1637 1638 unsigned int ctl; 1639 unsigned int shift; /* Shift count to trasform frames in bytes */ 1640 struct snd_pcm_indirect pcm_rec; 1641 struct snd_pcm_substream *substream; 1642 1643 struct dsp_pcm_channel_descriptor * pcm_channel; 1644 1645 int pcm_channel_id; /* Fron Rear, Center Lfe ... */ 1646}; 1647 1648struct snd_cs46xx_region { 1649 char name[24]; 1650 unsigned long base; 1651 void __iomem *remap_addr; 1652 unsigned long size; 1653 struct resource *resource; 1654}; 1655 1656struct snd_cs46xx { 1657 int irq; 1658 unsigned long ba0_addr; 1659 unsigned long ba1_addr; 1660 union { 1661 struct { 1662 struct snd_cs46xx_region ba0; 1663 struct snd_cs46xx_region data0; 1664 struct snd_cs46xx_region data1; 1665 struct snd_cs46xx_region pmem; 1666 struct snd_cs46xx_region reg; 1667 } name; 1668 struct snd_cs46xx_region idx[5]; 1669 } region; 1670 1671 unsigned int mode; 1672 1673 struct { 1674 struct snd_dma_buffer hw_buf; 1675 1676 unsigned int ctl; 1677 unsigned int shift; /* Shift count to trasform frames in bytes */ 1678 struct snd_pcm_indirect pcm_rec; 1679 struct snd_pcm_substream *substream; 1680 } capt; 1681 1682 1683 int nr_ac97_codecs; 1684 struct snd_ac97_bus *ac97_bus; 1685 struct snd_ac97 *ac97[MAX_NR_AC97]; 1686 1687 struct pci_dev *pci; 1688 struct snd_card *card; 1689 struct snd_pcm *pcm; 1690 1691 struct snd_rawmidi *rmidi; 1692 struct snd_rawmidi_substream *midi_input; 1693 struct snd_rawmidi_substream *midi_output; 1694 1695 spinlock_t reg_lock; 1696 unsigned int midcr; 1697 unsigned int uartm; 1698 1699 int amplifier; 1700 void (*amplifier_ctrl)(struct snd_cs46xx *, int); 1701 void (*active_ctrl)(struct snd_cs46xx *, int); 1702 void (*mixer_init)(struct snd_cs46xx *); 1703 1704 int acpi_port; 1705 struct snd_kcontrol *eapd_switch; /* for amplifier hack */ 1706 int accept_valid; /* accept mmap valid (for OSS) */ 1707 int in_suspend; 1708 1709 struct gameport *gameport; 1710 1711#ifdef CONFIG_SND_CS46XX_DEBUG_GPIO 1712 int current_gpio; 1713#endif 1714#ifdef CONFIG_SND_CS46XX_NEW_DSP 1715 struct mutex spos_mutex; 1716 1717 struct dsp_spos_instance * dsp_spos_instance; 1718 1719 struct snd_pcm *pcm_rear; 1720 struct snd_pcm *pcm_center_lfe; 1721 struct snd_pcm *pcm_iec958; 1722#else /* for compatibility */ 1723 struct snd_cs46xx_pcm *playback_pcm; 1724 unsigned int play_ctl; 1725#endif 1726}; 1727 1728int snd_cs46xx_create(struct snd_card *card, 1729 struct pci_dev *pci, 1730 int external_amp, int thinkpad, 1731 struct snd_cs46xx **rcodec); 1732int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state); 1733int snd_cs46xx_resume(struct pci_dev *pci); 1734 1735int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); 1736int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); 1737int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); 1738int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); 1739int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device); 1740int snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rmidi); 1741int snd_cs46xx_start_dsp(struct snd_cs46xx *chip); 1742int snd_cs46xx_gameport(struct snd_cs46xx *chip); 1743 1744#endif /* __SOUND_CS46XX_H */ 1745