1/* 2 * linux/include/asm-arm/hardware/serial_amba.h 3 * 4 * Internal header file for AMBA serial ports 5 * 6 * Copyright (C) ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H 24#define ASM_ARM_HARDWARE_SERIAL_AMBA_H 25 26/* ------------------------------------------------------------------------------- 27 * From AMBA UART (PL010) Block Specification 28 * ------------------------------------------------------------------------------- 29 * UART Register Offsets. 30 */ 31#define UART01x_DR 0x00 /* Data read or written from the interface. */ 32#define UART01x_RSR 0x04 /* Receive status register (Read). */ 33#define UART01x_ECR 0x04 /* Error clear register (Write). */ 34#define UART010_LCRH 0x08 /* Line control register, high byte. */ 35#define UART010_LCRM 0x0C /* Line control register, middle byte. */ 36#define UART010_LCRL 0x10 /* Line control register, low byte. */ 37#define UART010_CR 0x14 /* Control register. */ 38#define UART01x_FR 0x18 /* Flag register (Read only). */ 39#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */ 40#define UART010_ICR 0x1C /* Interrupt clear register (Write). */ 41#define UART01x_ILPR 0x20 /* IrDA low power counter register. */ 42#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ 43#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ 44#define UART011_LCRH 0x2c /* Line control register. */ 45#define UART011_CR 0x30 /* Control register. */ 46#define UART011_IFLS 0x34 /* Interrupt fifo level select. */ 47#define UART011_IMSC 0x38 /* Interrupt mask. */ 48#define UART011_RIS 0x3c /* Raw interrupt status. */ 49#define UART011_MIS 0x40 /* Masked interrupt status. */ 50#define UART011_ICR 0x44 /* Interrupt clear register. */ 51#define UART011_DMACR 0x48 /* DMA control register. */ 52 53#define UART011_DR_OE (1 << 11) 54#define UART011_DR_BE (1 << 10) 55#define UART011_DR_PE (1 << 9) 56#define UART011_DR_FE (1 << 8) 57 58#define UART01x_RSR_OE 0x08 59#define UART01x_RSR_BE 0x04 60#define UART01x_RSR_PE 0x02 61#define UART01x_RSR_FE 0x01 62 63#define UART011_FR_RI 0x100 64#define UART011_FR_TXFE 0x080 65#define UART011_FR_RXFF 0x040 66#define UART01x_FR_TXFF 0x020 67#define UART01x_FR_RXFE 0x010 68#define UART01x_FR_BUSY 0x008 69#define UART01x_FR_DCD 0x004 70#define UART01x_FR_DSR 0x002 71#define UART01x_FR_CTS 0x001 72#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY) 73 74#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */ 75#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */ 76#define UART011_CR_OUT2 0x2000 /* OUT2 */ 77#define UART011_CR_OUT1 0x1000 /* OUT1 */ 78#define UART011_CR_RTS 0x0800 /* RTS */ 79#define UART011_CR_DTR 0x0400 /* DTR */ 80#define UART011_CR_RXE 0x0200 /* receive enable */ 81#define UART011_CR_TXE 0x0100 /* transmit enable */ 82#define UART011_CR_LBE 0x0080 /* loopback enable */ 83#define UART010_CR_RTIE 0x0040 84#define UART010_CR_TIE 0x0020 85#define UART010_CR_RIE 0x0010 86#define UART010_CR_MSIE 0x0008 87#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ 88#define UART01x_CR_SIREN 0x0002 /* SIR enable */ 89#define UART01x_CR_UARTEN 0x0001 /* UART enable */ 90 91#define UART011_LCRH_SPS 0x80 92#define UART01x_LCRH_WLEN_8 0x60 93#define UART01x_LCRH_WLEN_7 0x40 94#define UART01x_LCRH_WLEN_6 0x20 95#define UART01x_LCRH_WLEN_5 0x00 96#define UART01x_LCRH_FEN 0x10 97#define UART01x_LCRH_STP2 0x08 98#define UART01x_LCRH_EPS 0x04 99#define UART01x_LCRH_PEN 0x02 100#define UART01x_LCRH_BRK 0x01 101 102#define UART010_IIR_RTIS 0x08 103#define UART010_IIR_TIS 0x04 104#define UART010_IIR_RIS 0x02 105#define UART010_IIR_MIS 0x01 106 107#define UART011_IFLS_RX1_8 (0 << 3) 108#define UART011_IFLS_RX2_8 (1 << 3) 109#define UART011_IFLS_RX4_8 (2 << 3) 110#define UART011_IFLS_RX6_8 (3 << 3) 111#define UART011_IFLS_RX7_8 (4 << 3) 112#define UART011_IFLS_TX1_8 (0 << 0) 113#define UART011_IFLS_TX2_8 (1 << 0) 114#define UART011_IFLS_TX4_8 (2 << 0) 115#define UART011_IFLS_TX6_8 (3 << 0) 116#define UART011_IFLS_TX7_8 (4 << 0) 117 118#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */ 119#define UART011_BEIM (1 << 9) /* break error interrupt mask */ 120#define UART011_PEIM (1 << 8) /* parity error interrupt mask */ 121#define UART011_FEIM (1 << 7) /* framing error interrupt mask */ 122#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */ 123#define UART011_TXIM (1 << 5) /* transmit interrupt mask */ 124#define UART011_RXIM (1 << 4) /* receive interrupt mask */ 125#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */ 126#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */ 127#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */ 128#define UART011_RIMIM (1 << 0) /* RI interrupt mask */ 129 130#define UART011_OEIS (1 << 10) /* overrun error interrupt status */ 131#define UART011_BEIS (1 << 9) /* break error interrupt status */ 132#define UART011_PEIS (1 << 8) /* parity error interrupt status */ 133#define UART011_FEIS (1 << 7) /* framing error interrupt status */ 134#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */ 135#define UART011_TXIS (1 << 5) /* transmit interrupt status */ 136#define UART011_RXIS (1 << 4) /* receive interrupt status */ 137#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */ 138#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */ 139#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */ 140#define UART011_RIMIS (1 << 0) /* RI interrupt status */ 141 142#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */ 143#define UART011_BEIC (1 << 9) /* break error interrupt clear */ 144#define UART011_PEIC (1 << 8) /* parity error interrupt clear */ 145#define UART011_FEIC (1 << 7) /* framing error interrupt clear */ 146#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */ 147#define UART011_TXIC (1 << 5) /* transmit interrupt clear */ 148#define UART011_RXIC (1 << 4) /* receive interrupt clear */ 149#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */ 150#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */ 151#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */ 152#define UART011_RIMIC (1 << 0) /* RI interrupt clear */ 153 154#define UART011_DMAONERR (1 << 2) /* disable dma on error */ 155#define UART011_TXDMAE (1 << 1) /* enable transmit dma */ 156#define UART011_RXDMAE (1 << 0) /* enable receive dma */ 157 158#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE) 159#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS) 160 161#ifndef __ASSEMBLY__ 162struct amba_pl010_data { 163 void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl); 164}; 165#endif 166 167#endif 168