1/* 2 * include/asm-mips/emma2rh/emma2rh.h 3 * This file is EMMA2RH common header. 4 * 5 * Copyright (C) NEC Electronics Corporation 2005-2006 6 * 7 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h 8 * Copyright 2001 MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24#ifndef __ASM_EMMA2RH_EMMA2RH_H 25#define __ASM_EMMA2RH_EMMA2RH_H 26 27#include <irq.h> 28 29/* 30 * EMMA2RH registers 31 */ 32#define REGBASE 0x10000000 33 34#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE) 35#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE) 36#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE) 37#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE) 38#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE) 39#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE) 40#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE) 41#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE) 42#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE) 43#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE) 44#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE) 45#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE) 46#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) 47#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE) 48#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE) 49#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE) 50#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE) 51#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE) 52#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE) 53#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE) 54#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE) 55#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE) 56#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE) 57#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE) 58#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE) 59#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE) 60#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE) 61#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE) 62#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE) 63#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE) 64#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE) 65#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE) 66#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE) 67#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE) 68#define EMMA2RH_PCI_INT (0x200020+REGBASE) 69#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE) 70#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE) 71#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE) 72#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE) 73#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE) 74 75/* 76 * Memory map (physical address) 77 * 78 * Note most of the following address must be properly aligned by the 79 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then 80 * PCI_IO_BASE must be aligned along 16MB boundary. 81 */ 82 83/* the actual ram size is detected at run-time */ 84#define EMMA2RH_RAM_BASE 0x00000000 85#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */ 86 87#define EMMA2RH_IO_BASE 0x10000000 88#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */ 89 90#define EMMA2RH_GENERALIO_BASE 0x11000000 91#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */ 92 93#define EMMA2RH_PCI_IO_BASE 0x12000000 94#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */ 95 96#define EMMA2RH_PCI_MEM_BASE 0x14000000 97#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */ 98 99#define EMMA2RH_ROM_BASE 0x1c000000 100#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */ 101 102#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE 103#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE 104 105#define NUM_CPU_IRQ 8 106#define NUM_EMMA2RH_IRQ 96 107 108#define CPU_EMMA2RH_CASCADE 2 109#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE 110#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) 111 112/* 113 * emma2rh irq defs 114 */ 115 116#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE) 117#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE) 118#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE) 119#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE) 120#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE) 121#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE) 122#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE) 123#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE) 124#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE) 125#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE) 126#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE) 127#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE) 128#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE) 129#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE) 130#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE) 131#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE) 132#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE) 133#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE) 134#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE) 135#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE) 136#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE) 137#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE) 138#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE) 139#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE) 140#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE) 141#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE) 142#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE) 143#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE) 144#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE) 145#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE) 146#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE) 147#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE) 148#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE) 149#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE) 150#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE) 151#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE) 152#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE) 153#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE) 154#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE) 155#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE) 156#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE) 157#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE) 158#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE) 159#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE) 160#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE) 161#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE) 162#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE) 163#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE) 164#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE) 165#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE) 166#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE) 167#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE) 168#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE) 169#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE) 170#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE) 171#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE) 172#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE) 173#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE) 174#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE) 175#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE) 176#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE) 177#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE) 178#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE) 179#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE) 180 181#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49 182#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50 183#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51 184#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56 185#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57 186#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58 187 188/* 189 * EMMA2RH Register Access 190 */ 191 192#define EMMA2RH_BASE (0xa0000000) 193 194static inline void emma2rh_sync(void) 195{ 196 volatile u32 *p = (volatile u32 *)0xbfc00000; 197 (void)(*p); 198} 199 200static inline void emma2rh_out32(u32 offset, u32 val) 201{ 202 *(volatile u32 *)(EMMA2RH_BASE | offset) = val; 203 emma2rh_sync(); 204} 205 206static inline u32 emma2rh_in32(u32 offset) 207{ 208 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset); 209 emma2rh_sync(); 210 return val; 211} 212 213static inline void emma2rh_out16(u32 offset, u16 val) 214{ 215 *(volatile u16 *)(EMMA2RH_BASE | offset) = val; 216 emma2rh_sync(); 217} 218 219static inline u16 emma2rh_in16(u32 offset) 220{ 221 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset); 222 emma2rh_sync(); 223 return val; 224} 225 226static inline void emma2rh_out8(u32 offset, u8 val) 227{ 228 *(volatile u8 *)(EMMA2RH_BASE | offset) = val; 229 emma2rh_sync(); 230} 231 232static inline u8 emma2rh_in8(u32 offset) 233{ 234 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset); 235 emma2rh_sync(); 236 return val; 237} 238 239/** 240 * IIC registers map 241 **/ 242 243/*---------------------------------------------------------------------------*/ 244/* CNT - Control register (00H R/W) */ 245/*---------------------------------------------------------------------------*/ 246#define SPT 0x00000001 247#define STT 0x00000002 248#define ACKE 0x00000004 249#define WTIM 0x00000008 250#define SPIE 0x00000010 251#define WREL 0x00000020 252#define LREL 0x00000040 253#define IICE 0x00000080 254#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ 255 256#define I2C_EMMA_START (IICE | STT) 257#define I2C_EMMA_STOP (IICE | SPT) 258#define I2C_EMMA_REPSTART I2C_EMMA_START 259 260/*---------------------------------------------------------------------------*/ 261/* STA - Status register (10H Read) */ 262/*---------------------------------------------------------------------------*/ 263#define MSTS 0x00000080 264#define ALD 0x00000040 265#define EXC 0x00000020 266#define COI 0x00000010 267#define TRC 0x00000008 268#define ACKD 0x00000004 269#define STD 0x00000002 270#define SPD 0x00000001 271 272/*---------------------------------------------------------------------------*/ 273/* CSEL - Clock select register (20H R/W) */ 274/*---------------------------------------------------------------------------*/ 275#define FCL 0x00000080 276#define ND50 0x00000040 277#define CLD 0x00000020 278#define DAD 0x00000010 279#define SMC 0x00000008 280#define DFC 0x00000004 281#define CL 0x00000003 282#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ 283 284#define FAST397 0x0000008b 285#define FAST297 0x0000008a 286#define FAST347 0x0000000b 287#define FAST260 0x0000000a 288#define FAST130 0x00000008 289#define STANDARD108 0x00000083 290#define STANDARD83 0x00000082 291#define STANDARD95 0x00000003 292#define STANDARD73 0x00000002 293#define STANDARD36 0x00000001 294#define STANDARD71 0x00000000 295 296/*---------------------------------------------------------------------------*/ 297/* SVA - Slave address register (30H R/W) */ 298/*---------------------------------------------------------------------------*/ 299#define SVA 0x000000fe 300 301/*---------------------------------------------------------------------------*/ 302/* SHR - Shift register (40H R/W) */ 303/*---------------------------------------------------------------------------*/ 304#define SR 0x000000ff 305 306/*---------------------------------------------------------------------------*/ 307/* INT - Interrupt register (50H R/W) */ 308/* INTM - Interrupt mask register (60H R/W) */ 309/*---------------------------------------------------------------------------*/ 310#define INTE0 0x00000001 311 312/*********************************************************************** 313 * I2C registers 314 *********************************************************************** 315 */ 316#define I2C_EMMA_CNT 0x00 317#define I2C_EMMA_STA 0x10 318#define I2C_EMMA_CSEL 0x20 319#define I2C_EMMA_SVA 0x30 320#define I2C_EMMA_SHR 0x40 321#define I2C_EMMA_INT 0x50 322#define I2C_EMMA_INTM 0x60 323 324/* 325 * include the board dependent part 326 */ 327#if defined(CONFIG_MARKEINS) 328#include <asm/emma2rh/markeins.h> 329#else 330#error "Unknown EMMA2RH board!" 331#endif 332 333#endif /* __ASM_EMMA2RH_EMMA2RH_H */ 334