1/* $Id: io.h,v 1.1.1.1 2007/08/03 18:53:36 Exp $ */ 2#ifndef __SPARC64_IO_H 3#define __SPARC64_IO_H 4 5#include <linux/kernel.h> 6#include <linux/compiler.h> 7#include <linux/types.h> 8 9#include <asm/page.h> /* IO address mapping routines need this */ 10#include <asm/system.h> 11#include <asm/asi.h> 12 13/* PC crapola... */ 14#define __SLOW_DOWN_IO do { } while (0) 15#define SLOW_DOWN_IO do { } while (0) 16 17extern unsigned long virt_to_bus_not_defined_use_pci_map(volatile void *addr); 18#define virt_to_bus virt_to_bus_not_defined_use_pci_map 19extern unsigned long bus_to_virt_not_defined_use_pci_map(volatile void *addr); 20#define bus_to_virt bus_to_virt_not_defined_use_pci_map 21 22/* BIO layer definitions. */ 23extern unsigned long kern_base, kern_size; 24#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) 25#define BIO_VMERGE_BOUNDARY 8192 26 27static __inline__ u8 _inb(unsigned long addr) 28{ 29 u8 ret; 30 31 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */" 32 : "=r" (ret) 33 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 34 35 return ret; 36} 37 38static __inline__ u16 _inw(unsigned long addr) 39{ 40 u16 ret; 41 42 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */" 43 : "=r" (ret) 44 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 45 46 return ret; 47} 48 49static __inline__ u32 _inl(unsigned long addr) 50{ 51 u32 ret; 52 53 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */" 54 : "=r" (ret) 55 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 56 57 return ret; 58} 59 60static __inline__ void _outb(u8 b, unsigned long addr) 61{ 62 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */" 63 : /* no outputs */ 64 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 65} 66 67static __inline__ void _outw(u16 w, unsigned long addr) 68{ 69 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */" 70 : /* no outputs */ 71 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 72} 73 74static __inline__ void _outl(u32 l, unsigned long addr) 75{ 76 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */" 77 : /* no outputs */ 78 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 79} 80 81#define inb(__addr) (_inb((unsigned long)(__addr))) 82#define inw(__addr) (_inw((unsigned long)(__addr))) 83#define inl(__addr) (_inl((unsigned long)(__addr))) 84#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr))) 85#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr))) 86#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr))) 87 88#define inb_p(__addr) inb(__addr) 89#define outb_p(__b, __addr) outb(__b, __addr) 90#define inw_p(__addr) inw(__addr) 91#define outw_p(__w, __addr) outw(__w, __addr) 92#define inl_p(__addr) inl(__addr) 93#define outl_p(__l, __addr) outl(__l, __addr) 94 95extern void outsb(unsigned long, const void *, unsigned long); 96extern void outsw(unsigned long, const void *, unsigned long); 97extern void outsl(unsigned long, const void *, unsigned long); 98extern void insb(unsigned long, void *, unsigned long); 99extern void insw(unsigned long, void *, unsigned long); 100extern void insl(unsigned long, void *, unsigned long); 101 102static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count) 103{ 104 insb((unsigned long __force)port, buf, count); 105} 106static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count) 107{ 108 insw((unsigned long __force)port, buf, count); 109} 110 111static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count) 112{ 113 insl((unsigned long __force)port, buf, count); 114} 115 116static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count) 117{ 118 outsb((unsigned long __force)port, buf, count); 119} 120 121static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count) 122{ 123 outsw((unsigned long __force)port, buf, count); 124} 125 126static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count) 127{ 128 outsl((unsigned long __force)port, buf, count); 129} 130 131/* Memory functions, same as I/O accesses on Ultra. */ 132static inline u8 _readb(const volatile void __iomem *addr) 133{ u8 ret; 134 135 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */" 136 : "=r" (ret) 137 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 138 return ret; 139} 140 141static inline u16 _readw(const volatile void __iomem *addr) 142{ u16 ret; 143 144 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */" 145 : "=r" (ret) 146 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 147 148 return ret; 149} 150 151static inline u32 _readl(const volatile void __iomem *addr) 152{ u32 ret; 153 154 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */" 155 : "=r" (ret) 156 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 157 158 return ret; 159} 160 161static inline u64 _readq(const volatile void __iomem *addr) 162{ u64 ret; 163 164 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */" 165 : "=r" (ret) 166 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 167 168 return ret; 169} 170 171static inline void _writeb(u8 b, volatile void __iomem *addr) 172{ 173 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" 174 : /* no outputs */ 175 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 176} 177 178static inline void _writew(u16 w, volatile void __iomem *addr) 179{ 180 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" 181 : /* no outputs */ 182 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 183} 184 185static inline void _writel(u32 l, volatile void __iomem *addr) 186{ 187 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" 188 : /* no outputs */ 189 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 190} 191 192static inline void _writeq(u64 q, volatile void __iomem *addr) 193{ 194 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" 195 : /* no outputs */ 196 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); 197} 198 199#define readb(__addr) _readb(__addr) 200#define readw(__addr) _readw(__addr) 201#define readl(__addr) _readl(__addr) 202#define readq(__addr) _readq(__addr) 203#define readb_relaxed(__addr) _readb(__addr) 204#define readw_relaxed(__addr) _readw(__addr) 205#define readl_relaxed(__addr) _readl(__addr) 206#define readq_relaxed(__addr) _readq(__addr) 207#define writeb(__b, __addr) _writeb(__b, __addr) 208#define writew(__w, __addr) _writew(__w, __addr) 209#define writel(__l, __addr) _writel(__l, __addr) 210#define writeq(__q, __addr) _writeq(__q, __addr) 211 212/* Now versions without byte-swapping. */ 213static __inline__ u8 _raw_readb(unsigned long addr) 214{ 215 u8 ret; 216 217 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */" 218 : "=r" (ret) 219 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 220 221 return ret; 222} 223 224static __inline__ u16 _raw_readw(unsigned long addr) 225{ 226 u16 ret; 227 228 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */" 229 : "=r" (ret) 230 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 231 232 return ret; 233} 234 235static __inline__ u32 _raw_readl(unsigned long addr) 236{ 237 u32 ret; 238 239 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */" 240 : "=r" (ret) 241 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 242 243 return ret; 244} 245 246static __inline__ u64 _raw_readq(unsigned long addr) 247{ 248 u64 ret; 249 250 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */" 251 : "=r" (ret) 252 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 253 254 return ret; 255} 256 257static __inline__ void _raw_writeb(u8 b, unsigned long addr) 258{ 259 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */" 260 : /* no outputs */ 261 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 262} 263 264static __inline__ void _raw_writew(u16 w, unsigned long addr) 265{ 266 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */" 267 : /* no outputs */ 268 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 269} 270 271static __inline__ void _raw_writel(u32 l, unsigned long addr) 272{ 273 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */" 274 : /* no outputs */ 275 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 276} 277 278static __inline__ void _raw_writeq(u64 q, unsigned long addr) 279{ 280 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */" 281 : /* no outputs */ 282 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 283} 284 285#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr))) 286#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr))) 287#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr))) 288#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr))) 289#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr))) 290#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr))) 291#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr))) 292#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr))) 293 294/* Valid I/O Space regions are anywhere, because each PCI bus supported 295 * can live in an arbitrary area of the physical address range. 296 */ 297#define IO_SPACE_LIMIT 0xffffffffffffffffUL 298 299/* Now, SBUS variants, only difference from PCI is that we do 300 * not use little-endian ASIs. 301 */ 302static inline u8 _sbus_readb(const volatile void __iomem *addr) 303{ 304 u8 ret; 305 306 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */" 307 : "=r" (ret) 308 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 309 310 return ret; 311} 312 313static inline u16 _sbus_readw(const volatile void __iomem *addr) 314{ 315 u16 ret; 316 317 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */" 318 : "=r" (ret) 319 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 320 321 return ret; 322} 323 324static inline u32 _sbus_readl(const volatile void __iomem *addr) 325{ 326 u32 ret; 327 328 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */" 329 : "=r" (ret) 330 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 331 332 return ret; 333} 334 335static inline u64 _sbus_readq(const volatile void __iomem *addr) 336{ 337 u64 ret; 338 339 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */" 340 : "=r" (ret) 341 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 342 343 return ret; 344} 345 346static inline void _sbus_writeb(u8 b, volatile void __iomem *addr) 347{ 348 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */" 349 : /* no outputs */ 350 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 351} 352 353static inline void _sbus_writew(u16 w, volatile void __iomem *addr) 354{ 355 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */" 356 : /* no outputs */ 357 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 358} 359 360static inline void _sbus_writel(u32 l, volatile void __iomem *addr) 361{ 362 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */" 363 : /* no outputs */ 364 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 365} 366 367static inline void _sbus_writeq(u64 l, volatile void __iomem *addr) 368{ 369 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */" 370 : /* no outputs */ 371 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 372} 373 374#define sbus_readb(__addr) _sbus_readb(__addr) 375#define sbus_readw(__addr) _sbus_readw(__addr) 376#define sbus_readl(__addr) _sbus_readl(__addr) 377#define sbus_readq(__addr) _sbus_readq(__addr) 378#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr) 379#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr) 380#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr) 381#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr) 382 383static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n) 384{ 385 while(n--) { 386 sbus_writeb(c, dst); 387 dst++; 388 } 389} 390 391#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz) 392 393static inline void 394_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n) 395{ 396 volatile void __iomem *d = dst; 397 398 while (n--) { 399 writeb(c, d); 400 d++; 401 } 402} 403 404#define memset_io(d,c,sz) _memset_io(d,c,sz) 405 406static inline void 407_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n) 408{ 409 char *d = dst; 410 411 while (n--) { 412 char tmp = readb(src); 413 *d++ = tmp; 414 src++; 415 } 416} 417 418#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz) 419 420static inline void 421_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n) 422{ 423 const char *s = src; 424 volatile void __iomem *d = dst; 425 426 while (n--) { 427 char tmp = *s++; 428 writeb(tmp, d); 429 d++; 430 } 431} 432 433#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz) 434 435#define mmiowb() 436 437#ifdef __KERNEL__ 438 439/* On sparc64 we have the whole physical IO address space accessible 440 * using physically addressed loads and stores, so this does nothing. 441 */ 442static inline void __iomem *ioremap(unsigned long offset, unsigned long size) 443{ 444 return (void __iomem *)offset; 445} 446 447#define ioremap_nocache(X,Y) ioremap((X),(Y)) 448 449static inline void iounmap(volatile void __iomem *addr) 450{ 451} 452 453#define ioread8(X) readb(X) 454#define ioread16(X) readw(X) 455#define ioread32(X) readl(X) 456#define iowrite8(val,X) writeb(val,X) 457#define iowrite16(val,X) writew(val,X) 458#define iowrite32(val,X) writel(val,X) 459 460/* Create a virtual mapping cookie for an IO port range */ 461extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 462extern void ioport_unmap(void __iomem *); 463 464/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ 465struct pci_dev; 466extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); 467extern void pci_iounmap(struct pci_dev *dev, void __iomem *); 468 469/* Similarly for SBUS. */ 470#define sbus_ioremap(__res, __offset, __size, __name) \ 471({ unsigned long __ret; \ 472 __ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \ 473 __ret += (unsigned long) (__offset); \ 474 if (! request_region((__ret), (__size), (__name))) \ 475 __ret = 0UL; \ 476 (void __iomem *) __ret; \ 477}) 478 479#define sbus_iounmap(__addr, __size) \ 480 release_region((unsigned long)(__addr), (__size)) 481 482/* Nothing to do */ 483 484#define dma_cache_inv(_start,_size) do { } while (0) 485#define dma_cache_wback(_start,_size) do { } while (0) 486#define dma_cache_wback_inv(_start,_size) do { } while (0) 487 488/* 489 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 490 * access 491 */ 492#define xlate_dev_mem_ptr(p) __va(p) 493 494/* 495 * Convert a virtual cached pointer to an uncached pointer 496 */ 497#define xlate_dev_kmem_ptr(p) p 498 499#endif 500 501#endif /* !(__SPARC64_IO_H) */ 502