1#ifndef _ASM_POWERPC_MMU_44X_H_ 2#define _ASM_POWERPC_MMU_44X_H_ 3/* 4 * PPC440 support 5 */ 6 7#define PPC44x_MMUCR_TID 0x000000ff 8#define PPC44x_MMUCR_STS 0x00010000 9 10#define PPC44x_TLB_PAGEID 0 11#define PPC44x_TLB_XLAT 1 12#define PPC44x_TLB_ATTRIB 2 13 14/* Page identification fields */ 15#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ 16#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ 17#define PPC44x_TLB_TS 0x00000100 /* Translation address space */ 18#define PPC44x_TLB_1K 0x00000000 /* Page sizes */ 19#define PPC44x_TLB_4K 0x00000010 20#define PPC44x_TLB_16K 0x00000020 21#define PPC44x_TLB_64K 0x00000030 22#define PPC44x_TLB_256K 0x00000040 23#define PPC44x_TLB_1M 0x00000050 24#define PPC44x_TLB_16M 0x00000070 25#define PPC44x_TLB_256M 0x00000090 26 27/* Translation fields */ 28#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ 29#define PPC44x_TLB_ERPN_MASK 0x0000000f 30 31/* Storage attribute and access control fields */ 32#define PPC44x_TLB_ATTR_MASK 0x0000ff80 33#define PPC44x_TLB_U0 0x00008000 /* User 0 */ 34#define PPC44x_TLB_U1 0x00004000 /* User 1 */ 35#define PPC44x_TLB_U2 0x00002000 /* User 2 */ 36#define PPC44x_TLB_U3 0x00001000 /* User 3 */ 37#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ 38#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ 39#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ 40#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ 41#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ 42 43#define PPC44x_TLB_PERM_MASK 0x0000003f 44#define PPC44x_TLB_UX 0x00000020 /* User execution */ 45#define PPC44x_TLB_UW 0x00000010 /* User write */ 46#define PPC44x_TLB_UR 0x00000008 /* User read */ 47#define PPC44x_TLB_SX 0x00000004 /* Super execution */ 48#define PPC44x_TLB_SW 0x00000002 /* Super write */ 49#define PPC44x_TLB_SR 0x00000001 /* Super read */ 50 51/* Number of TLB entries */ 52#define PPC44x_TLB_SIZE 64 53 54#ifndef __ASSEMBLY__ 55 56typedef unsigned long long phys_addr_t; 57 58typedef struct { 59 unsigned long id; 60 unsigned long vdso_base; 61} mm_context_t; 62 63#endif /* !__ASSEMBLY__ */ 64 65#ifndef CONFIG_PPC_EARLY_DEBUG_44x 66#define PPC44x_EARLY_TLBS 1 67#else 68#define PPC44x_EARLY_TLBS 2 69#define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \ 70 | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff)) 71#endif 72 73/* Size of the TLBs used for pinning in lowmem */ 74#define PPC_PIN_SIZE (1 << 28) /* 256M */ 75 76#endif /* _ASM_POWERPC_MMU_44X_H_ */ 77