1#ifndef _PARISC_PDC_H 2#define _PARISC_PDC_H 3 4 5/* 6 * PDC return values ... 7 * All PDC calls return a subset of these errors. 8 */ 9 10#define PDC_WARN 3 /* Call completed with a warning */ 11#define PDC_REQ_ERR_1 2 /* See above */ 12#define PDC_REQ_ERR_0 1 /* Call would generate a requestor error */ 13#define PDC_OK 0 /* Call completed successfully */ 14#define PDC_BAD_PROC -1 /* Called non-existent procedure*/ 15#define PDC_BAD_OPTION -2 /* Called with non-existent option */ 16#define PDC_ERROR -3 /* Call could not complete without an error */ 17#define PDC_NE_MOD -5 /* Module not found */ 18#define PDC_NE_CELL_MOD -7 /* Cell module not found */ 19#define PDC_INVALID_ARG -10 /* Called with an invalid argument */ 20#define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */ 21#define PDC_NOT_NARROW -17 /* Narrow mode not supported */ 22 23 24/* 25 * PDC entry points... 26 */ 27 28#define PDC_POW_FAIL 1 /* perform a power-fail */ 29#define PDC_POW_FAIL_PREPARE 0 /* prepare for powerfail */ 30 31#define PDC_CHASSIS 2 /* PDC-chassis functions */ 32#define PDC_CHASSIS_DISP 0 /* update chassis display */ 33#define PDC_CHASSIS_WARN 1 /* return chassis warnings */ 34#define PDC_CHASSIS_DISPWARN 2 /* update&return chassis status */ 35#define PDC_RETURN_CHASSIS_INFO 128 /* HVERSION dependent: return chassis LED/LCD info */ 36 37#define PDC_PIM 3 /* Get PIM data */ 38#define PDC_PIM_HPMC 0 /* Transfer HPMC data */ 39#define PDC_PIM_RETURN_SIZE 1 /* Get Max buffer needed for PIM*/ 40#define PDC_PIM_LPMC 2 /* Transfer HPMC data */ 41#define PDC_PIM_SOFT_BOOT 3 /* Transfer Soft Boot data */ 42#define PDC_PIM_TOC 4 /* Transfer TOC data */ 43 44#define PDC_MODEL 4 /* PDC model information call */ 45#define PDC_MODEL_INFO 0 /* returns information */ 46#define PDC_MODEL_BOOTID 1 /* set the BOOT_ID */ 47#define PDC_MODEL_VERSIONS 2 /* returns cpu-internal versions*/ 48#define PDC_MODEL_SYSMODEL 3 /* return system model info */ 49#define PDC_MODEL_ENSPEC 4 /* enable specific option */ 50#define PDC_MODEL_DISPEC 5 /* disable specific option */ 51#define PDC_MODEL_CPU_ID 6 /* returns cpu-id (only newer machines!) */ 52#define PDC_MODEL_CAPABILITIES 7 /* returns OS32/OS64-flags */ 53#define PDC_MODEL_GET_BOOT__OP 8 /* returns boot test options */ 54#define PDC_MODEL_SET_BOOT__OP 9 /* set boot test options */ 55 56#define PA89_INSTRUCTION_SET 0x4 /* capatibilies returned */ 57#define PA90_INSTRUCTION_SET 0x8 58 59#define PDC_CACHE 5 /* return/set cache (& TLB) info*/ 60#define PDC_CACHE_INFO 0 /* returns information */ 61#define PDC_CACHE_SET_COH 1 /* set coherence state */ 62#define PDC_CACHE_RET_SPID 2 /* returns space-ID bits */ 63 64#define PDC_HPA 6 /* return HPA of processor */ 65#define PDC_HPA_PROCESSOR 0 66#define PDC_HPA_MODULES 1 67 68#define PDC_COPROC 7 /* Co-Processor (usually FP unit(s)) */ 69#define PDC_COPROC_CFG 0 /* Co-Processor Cfg (FP unit(s) enabled?) */ 70 71#define PDC_IODC 8 /* talk to IODC */ 72#define PDC_IODC_READ 0 /* read IODC entry point */ 73/* PDC_IODC_RI_ * INDEX parameter of PDC_IODC_READ */ 74#define PDC_IODC_RI_DATA_BYTES 0 /* IODC Data Bytes */ 75/* 1, 2 obsolete - HVERSION dependent*/ 76#define PDC_IODC_RI_INIT 3 /* Initialize module */ 77#define PDC_IODC_RI_IO 4 /* Module input/output */ 78#define PDC_IODC_RI_SPA 5 /* Module input/output */ 79#define PDC_IODC_RI_CONFIG 6 /* Module input/output */ 80/* 7 obsolete - HVERSION dependent */ 81#define PDC_IODC_RI_TEST 8 /* Module input/output */ 82#define PDC_IODC_RI_TLB 9 /* Module input/output */ 83#define PDC_IODC_NINIT 2 /* non-destructive init */ 84#define PDC_IODC_DINIT 3 /* destructive init */ 85#define PDC_IODC_MEMERR 4 /* check for memory errors */ 86#define PDC_IODC_INDEX_DATA 0 /* get first 16 bytes from mod IODC */ 87#define PDC_IODC_BUS_ERROR -4 /* bus error return value */ 88#define PDC_IODC_INVALID_INDEX -5 /* invalid index return value */ 89#define PDC_IODC_COUNT -6 /* count is too small */ 90 91#define PDC_TOD 9 /* time-of-day clock (TOD) */ 92#define PDC_TOD_READ 0 /* read TOD */ 93#define PDC_TOD_WRITE 1 /* write TOD */ 94#define PDC_TOD_ITIMER 2 /* calibrate Interval Timer (CR16) */ 95 96#define PDC_STABLE 10 /* stable storage (sprockets) */ 97#define PDC_STABLE_READ 0 98#define PDC_STABLE_WRITE 1 99#define PDC_STABLE_RETURN_SIZE 2 100#define PDC_STABLE_VERIFY_CONTENTS 3 101#define PDC_STABLE_INITIALIZE 4 102 103#define PDC_NVOLATILE 11 /* often not implemented */ 104 105#define PDC_ADD_VALID 12 /* Memory validation PDC call */ 106#define PDC_ADD_VALID_VERIFY 0 /* Make PDC_ADD_VALID verify region */ 107 108#define PDC_INSTR 15 /* get instr to invoke PDCE_CHECK() */ 109 110#define PDC_PROC 16 /* (sprockets) */ 111 112#define PDC_CONFIG 16 /* (sprockets) */ 113#define PDC_CONFIG_DECONFIG 0 114#define PDC_CONFIG_DRECONFIG 1 115#define PDC_CONFIG_DRETURN_CONFIG 2 116 117#define PDC_BLOCK_TLB 18 /* manage hardware block-TLB */ 118#define PDC_BTLB_INFO 0 /* returns parameter */ 119#define PDC_BTLB_INSERT 1 /* insert BTLB entry */ 120#define PDC_BTLB_PURGE 2 /* purge BTLB entries */ 121#define PDC_BTLB_PURGE_ALL 3 /* purge all BTLB entries */ 122 123#define PDC_TLB 19 /* manage hardware TLB miss handling */ 124#define PDC_TLB_INFO 0 /* returns parameter */ 125#define PDC_TLB_SETUP 1 /* set up miss handling */ 126 127#define PDC_MEM 20 /* Manage memory */ 128#define PDC_MEM_MEMINFO 0 129#define PDC_MEM_ADD_PAGE 1 130#define PDC_MEM_CLEAR_PDT 2 131#define PDC_MEM_READ_PDT 3 132#define PDC_MEM_RESET_CLEAR 4 133#define PDC_MEM_GOODMEM 5 134#define PDC_MEM_TABLE 128 /* Non contig mem map (sprockets) */ 135#define PDC_MEM_RETURN_ADDRESS_TABLE PDC_MEM_TABLE 136#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE 131 137#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES 132 138#define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133 139 140#define PDC_MEM_RET_SBE_REPLACED 5 /* PDC_MEM return values */ 141#define PDC_MEM_RET_DUPLICATE_ENTRY 4 142#define PDC_MEM_RET_BUF_SIZE_SMALL 1 143#define PDC_MEM_RET_PDT_FULL -11 144#define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL 145 146#ifndef __ASSEMBLY__ 147typedef struct { 148 unsigned long long baseAddr; 149 unsigned int pages; 150 unsigned int reserved; 151} MemAddrTable_t; 152#endif 153 154 155#define PDC_PSW 21 /* Get/Set default System Mask */ 156#define PDC_PSW_MASK 0 /* Return mask */ 157#define PDC_PSW_GET_DEFAULTS 1 /* Return defaults */ 158#define PDC_PSW_SET_DEFAULTS 2 /* Set default */ 159#define PDC_PSW_ENDIAN_BIT 1 /* set for big endian */ 160#define PDC_PSW_WIDE_BIT 2 /* set for wide mode */ 161 162#define PDC_SYSTEM_MAP 22 /* find system modules */ 163#define PDC_FIND_MODULE 0 164#define PDC_FIND_ADDRESS 1 165#define PDC_TRANSLATE_PATH 2 166 167#define PDC_SOFT_POWER 23 /* soft power switch */ 168#define PDC_SOFT_POWER_INFO 0 /* return info about the soft power switch */ 169#define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */ 170 171 172/* HVERSION dependent */ 173 174/* The PDC_MEM_MAP calls */ 175#define PDC_MEM_MAP 128 /* on s700: return page info */ 176#define PDC_MEM_MAP_HPA 0 /* returns hpa of a module */ 177 178#define PDC_EEPROM 129 /* EEPROM access */ 179#define PDC_EEPROM_READ_WORD 0 180#define PDC_EEPROM_WRITE_WORD 1 181#define PDC_EEPROM_READ_BYTE 2 182#define PDC_EEPROM_WRITE_BYTE 3 183#define PDC_EEPROM_EEPROM_PASSWORD -1000 184 185#define PDC_NVM 130 /* NVM (non-volatile memory) access */ 186#define PDC_NVM_READ_WORD 0 187#define PDC_NVM_WRITE_WORD 1 188#define PDC_NVM_READ_BYTE 2 189#define PDC_NVM_WRITE_BYTE 3 190 191#define PDC_SEED_ERROR 132 /* (sprockets) */ 192 193#define PDC_IO 135 /* log error info, reset IO system */ 194#define PDC_IO_READ_AND_CLEAR_ERRORS 0 195#define PDC_IO_RESET 1 196#define PDC_IO_RESET_DEVICES 2 197/* sets bits 6&7 (little endian) of the HcControl Register */ 198#define PDC_IO_USB_SUSPEND 0xC000000000000000 199#define PDC_IO_EEPROM_IO_ERR_TABLE_FULL -5 /* return value */ 200#define PDC_IO_NO_SUSPEND -6 /* return value */ 201 202#define PDC_BROADCAST_RESET 136 /* reset all processors */ 203#define PDC_DO_RESET 0 /* option: perform a broadcast reset */ 204#define PDC_DO_FIRM_TEST_RESET 1 /* Do broadcast reset with bitmap */ 205#define PDC_BR_RECONFIGURATION 2 /* reset w/reconfiguration */ 206#define PDC_FIRM_TEST_MAGIC 0xab9ec36fUL /* for this reboot only */ 207 208#define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */ 209#define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */ 210 211#define PDC_LAN_STATION_ID_SIZE 6 212 213#define PDC_CHECK_RANGES 139 /* (sprockets) */ 214 215#define PDC_NV_SECTIONS 141 /* (sprockets) */ 216 217#define PDC_PERFORMANCE 142 /* performance monitoring */ 218 219#define PDC_SYSTEM_INFO 143 /* system information */ 220#define PDC_SYSINFO_RETURN_INFO_SIZE 0 221#define PDC_SYSINFO_RRETURN_SYS_INFO 1 222#define PDC_SYSINFO_RRETURN_ERRORS 2 223#define PDC_SYSINFO_RRETURN_WARNINGS 3 224#define PDC_SYSINFO_RETURN_REVISIONS 4 225#define PDC_SYSINFO_RRETURN_DIAGNOSE 5 226#define PDC_SYSINFO_RRETURN_HV_DIAGNOSE 1005 227 228#define PDC_RDR 144 /* (sprockets) */ 229#define PDC_RDR_READ_BUFFER 0 230#define PDC_RDR_READ_SINGLE 1 231#define PDC_RDR_WRITE_SINGLE 2 232 233#define PDC_INTRIGUE 145 /* (sprockets) */ 234#define PDC_INTRIGUE_WRITE_BUFFER 0 235#define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1 236#define PDC_INTRIGUE_START_CPU_COUNTERS 2 237#define PDC_INTRIGUE_STOP_CPU_COUNTERS 3 238 239#define PDC_STI 146 /* STI access */ 240/* same as PDC_PCI_XXX values (see below) */ 241 242/* Legacy PDC definitions for same stuff */ 243#define PDC_PCI_INDEX 147 244#define PDC_PCI_INTERFACE_INFO 0 245#define PDC_PCI_SLOT_INFO 1 246#define PDC_PCI_INFLIGHT_BYTES 2 247#define PDC_PCI_READ_CONFIG 3 248#define PDC_PCI_WRITE_CONFIG 4 249#define PDC_PCI_READ_PCI_IO 5 250#define PDC_PCI_WRITE_PCI_IO 6 251#define PDC_PCI_READ_CONFIG_DELAY 7 252#define PDC_PCI_UPDATE_CONFIG_DELAY 8 253#define PDC_PCI_PCI_PATH_TO_PCI_HPA 9 254#define PDC_PCI_PCI_HPA_TO_PCI_PATH 10 255#define PDC_PCI_PCI_PATH_TO_PCI_BUS 11 256#define PDC_PCI_PCI_RESERVED 12 257#define PDC_PCI_PCI_INT_ROUTE_SIZE 13 258#define PDC_PCI_GET_INT_TBL_SIZE PDC_PCI_PCI_INT_ROUTE_SIZE 259#define PDC_PCI_PCI_INT_ROUTE 14 260#define PDC_PCI_GET_INT_TBL PDC_PCI_PCI_INT_ROUTE 261#define PDC_PCI_READ_MON_TYPE 15 262#define PDC_PCI_WRITE_MON_TYPE 16 263 264 265/* Get SCSI Interface Card info: SDTR, SCSI ID, mode (SE vs LVD) */ 266#define PDC_INITIATOR 163 267#define PDC_GET_INITIATOR 0 268#define PDC_SET_INITIATOR 1 269#define PDC_DELETE_INITIATOR 2 270#define PDC_RETURN_TABLE_SIZE 3 271#define PDC_RETURN_TABLE 4 272 273#define PDC_LINK 165 /* (sprockets) */ 274#define PDC_LINK_PCI_ENTRY_POINTS 0 /* list (Arg1) = 0 */ 275#define PDC_LINK_USB_ENTRY_POINTS 1 /* list (Arg1) = 1 */ 276 277 278/* constants for OS (NVM...) */ 279#define OS_ID_NONE 0 /* Undefined OS ID */ 280#define OS_ID_HPUX 1 /* HP-UX OS */ 281#define OS_ID_MPEXL 2 /* MPE XL OS */ 282#define OS_ID_OSF 3 /* OSF OS */ 283#define OS_ID_HPRT 4 /* HP-RT OS */ 284#define OS_ID_NOVEL 5 /* NOVELL OS */ 285#define OS_ID_LINUX 6 /* Linux */ 286 287 288/* constants for PDC_CHASSIS */ 289#define OSTAT_OFF 0 290#define OSTAT_FLT 1 291#define OSTAT_TEST 2 292#define OSTAT_INIT 3 293#define OSTAT_SHUT 4 294#define OSTAT_WARN 5 295#define OSTAT_RUN 6 296#define OSTAT_ON 7 297 298#ifndef __ASSEMBLY__ 299 300#include <linux/types.h> 301 302extern int pdc_type; 303 304/* Values for pdc_type */ 305#define PDC_TYPE_ILLEGAL -1 306#define PDC_TYPE_PAT 0 /* 64-bit PAT-PDC */ 307#define PDC_TYPE_SYSTEM_MAP 1 /* 32-bit, but supports PDC_SYSTEM_MAP */ 308#define PDC_TYPE_SNAKE 2 /* Doesn't support SYSTEM_MAP */ 309 310struct pdc_chassis_info { /* for PDC_CHASSIS_INFO */ 311 unsigned long actcnt; /* actual number of bytes returned */ 312 unsigned long maxcnt; /* maximum number of bytes that could be returned */ 313}; 314 315struct pdc_coproc_cfg { /* for PDC_COPROC_CFG */ 316 unsigned long ccr_functional; 317 unsigned long ccr_present; 318 unsigned long revision; 319 unsigned long model; 320}; 321 322struct pdc_model { /* for PDC_MODEL */ 323 unsigned long hversion; 324 unsigned long sversion; 325 unsigned long hw_id; 326 unsigned long boot_id; 327 unsigned long sw_id; 328 unsigned long sw_cap; 329 unsigned long arch_rev; 330 unsigned long pot_key; 331 unsigned long curr_key; 332}; 333 334/* Values for PDC_MODEL_CAPABILITIES non-equivalent virtual aliasing support */ 335 336#define PDC_MODEL_IOPDIR_FDC (1 << 2) /* see sba_iommu.c */ 337#define PDC_MODEL_NVA_MASK (3 << 4) 338#define PDC_MODEL_NVA_SUPPORTED (0 << 4) 339#define PDC_MODEL_NVA_SLOW (1 << 4) 340#define PDC_MODEL_NVA_UNSUPPORTED (3 << 4) 341 342struct pdc_cache_cf { /* for PDC_CACHE (I/D-caches) */ 343 unsigned long 344#ifdef CONFIG_64BIT 345 cc_padW:32, 346#endif 347 cc_alias: 4, /* alias boundaries for virtual addresses */ 348 cc_block: 4, /* to determine most efficient stride */ 349 cc_line : 3, /* maximum amount written back as a result of store (multiple of 16 bytes) */ 350 cc_shift: 2, /* how much to shift cc_block left */ 351 cc_wt : 1, /* 0 = WT-Dcache, 1 = WB-Dcache */ 352 cc_sh : 2, /* 0 = separate I/D-cache, else shared I/D-cache */ 353 cc_cst : 3, /* 0 = incoherent D-cache, 1=coherent D-cache */ 354 cc_pad1 : 10, /* reserved */ 355 cc_hv : 3; /* hversion dependent */ 356}; 357 358struct pdc_tlb_cf { /* for PDC_CACHE (I/D-TLB's) */ 359 unsigned long tc_pad0:12, /* reserved */ 360#ifdef CONFIG_64BIT 361 tc_padW:32, 362#endif 363 tc_sh : 2, /* 0 = separate I/D-TLB, else shared I/D-TLB */ 364 tc_hv : 1, /* HV */ 365 tc_page : 1, /* 0 = 2K page-size-machine, 1 = 4k page size */ 366 tc_cst : 3, /* 0 = incoherent operations, else coherent operations */ 367 tc_aid : 5, /* ITLB: width of access ids of processor (encoded!) */ 368 tc_pad1 : 8; /* ITLB: width of space-registers (encoded) */ 369}; 370 371struct pdc_cache_info { /* main-PDC_CACHE-structure (caches & TLB's) */ 372 /* I-cache */ 373 unsigned long ic_size; /* size in bytes */ 374 struct pdc_cache_cf ic_conf; /* configuration */ 375 unsigned long ic_base; /* base-addr */ 376 unsigned long ic_stride; 377 unsigned long ic_count; 378 unsigned long ic_loop; 379 /* D-cache */ 380 unsigned long dc_size; /* size in bytes */ 381 struct pdc_cache_cf dc_conf; /* configuration */ 382 unsigned long dc_base; /* base-addr */ 383 unsigned long dc_stride; 384 unsigned long dc_count; 385 unsigned long dc_loop; 386 /* Instruction-TLB */ 387 unsigned long it_size; /* number of entries in I-TLB */ 388 struct pdc_tlb_cf it_conf; /* I-TLB-configuration */ 389 unsigned long it_sp_base; 390 unsigned long it_sp_stride; 391 unsigned long it_sp_count; 392 unsigned long it_off_base; 393 unsigned long it_off_stride; 394 unsigned long it_off_count; 395 unsigned long it_loop; 396 /* data-TLB */ 397 unsigned long dt_size; /* number of entries in D-TLB */ 398 struct pdc_tlb_cf dt_conf; /* D-TLB-configuration */ 399 unsigned long dt_sp_base; 400 unsigned long dt_sp_stride; 401 unsigned long dt_sp_count; 402 unsigned long dt_off_base; 403 unsigned long dt_off_stride; 404 unsigned long dt_off_count; 405 unsigned long dt_loop; 406}; 407 408 409#ifndef CONFIG_PA20 410/* no BLTBs in pa2.0 processors */ 411struct pdc_btlb_info_range { 412 __u8 res00; 413 __u8 num_i; 414 __u8 num_d; 415 __u8 num_comb; 416}; 417 418struct pdc_btlb_info { /* PDC_BLOCK_TLB, return of PDC_BTLB_INFO */ 419 unsigned int min_size; /* minimum size of BTLB in pages */ 420 unsigned int max_size; /* maximum size of BTLB in pages */ 421 struct pdc_btlb_info_range fixed_range_info; 422 struct pdc_btlb_info_range variable_range_info; 423}; 424 425#endif /* !CONFIG_PA20 */ 426 427#ifdef CONFIG_64BIT 428struct pdc_memory_table_raddr { /* PDC_MEM/PDC_MEM_TABLE (return info) */ 429 unsigned long entries_returned; 430 unsigned long entries_total; 431}; 432 433struct pdc_memory_table { /* PDC_MEM/PDC_MEM_TABLE (arguments) */ 434 unsigned long paddr; 435 unsigned int pages; 436 unsigned int reserved; 437}; 438#endif /* CONFIG_64BIT */ 439 440struct pdc_system_map_mod_info { /* PDC_SYSTEM_MAP/FIND_MODULE */ 441 unsigned long mod_addr; 442 unsigned long mod_pgs; 443 unsigned long add_addrs; 444}; 445 446struct pdc_system_map_addr_info { /* PDC_SYSTEM_MAP/FIND_ADDRESS */ 447 unsigned long mod_addr; 448 unsigned long mod_pgs; 449}; 450 451struct pdc_initiator { /* PDC_INITIATOR */ 452 int host_id; 453 int factor; 454 int width; 455 int mode; 456}; 457 458struct hardware_path { 459 char flags; /* see bit definitions below */ 460 char bc[6]; /* Bus Converter routing info to a specific */ 461 /* I/O adaptor (< 0 means none, > 63 resvd) */ 462 char mod; /* fixed field of specified module */ 463}; 464 465/* 466 * Device path specifications used by PDC. 467 */ 468struct pdc_module_path { 469 struct hardware_path path; 470 unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */ 471}; 472 473#ifndef CONFIG_PA20 474/* Only used on some pre-PA2.0 boxes */ 475struct pdc_memory_map { /* PDC_MEMORY_MAP */ 476 unsigned long hpa; /* mod's register set address */ 477 unsigned long more_pgs; /* number of additional I/O pgs */ 478}; 479#endif 480 481struct pdc_tod { 482 unsigned long tod_sec; 483 unsigned long tod_usec; 484}; 485 486/* architected results from PDC_PIM/transfer hpmc on a PA1.1 machine */ 487 488struct pdc_hpmc_pim_11 { /* PDC_PIM */ 489 __u32 gr[32]; 490 __u32 cr[32]; 491 __u32 sr[8]; 492 __u32 iasq_back; 493 __u32 iaoq_back; 494 __u32 check_type; 495 __u32 cpu_state; 496 __u32 rsvd1; 497 __u32 cache_check; 498 __u32 tlb_check; 499 __u32 bus_check; 500 __u32 assists_check; 501 __u32 rsvd2; 502 __u32 assist_state; 503 __u32 responder_addr; 504 __u32 requestor_addr; 505 __u32 path_info; 506 __u64 fr[32]; 507}; 508 509/* 510 * architected results from PDC_PIM/transfer hpmc on a PA2.0 machine 511 * 512 * Note that PDC_PIM doesn't care whether or not wide mode was enabled 513 * so the results are different on PA1.1 vs. PA2.0 when in narrow mode. 514 * 515 * Note also that there are unarchitected results available, which 516 * are hversion dependent. Do a "ser pim 0 hpmc" after rebooting, since 517 * the firmware is probably the best way of printing hversion dependent 518 * data. 519 */ 520 521struct pdc_hpmc_pim_20 { /* PDC_PIM */ 522 __u64 gr[32]; 523 __u64 cr[32]; 524 __u64 sr[8]; 525 __u64 iasq_back; 526 __u64 iaoq_back; 527 __u32 check_type; 528 __u32 cpu_state; 529 __u32 cache_check; 530 __u32 tlb_check; 531 __u32 bus_check; 532 __u32 assists_check; 533 __u32 assist_state; 534 __u32 path_info; 535 __u64 responder_addr; 536 __u64 requestor_addr; 537 __u64 fr[32]; 538}; 539 540#endif /* __ASSEMBLY__ */ 541 542/* flags of the device_path (see below) */ 543#define PF_AUTOBOOT 0x80 544#define PF_AUTOSEARCH 0x40 545#define PF_TIMER 0x0F 546 547#ifndef __ASSEMBLY__ 548 549struct device_path { /* page 1-69 */ 550 unsigned char flags; /* flags see above! */ 551 unsigned char bc[6]; /* bus converter routing info */ 552 unsigned char mod; 553 unsigned int layers[6];/* device-specific layer-info */ 554} __attribute__((aligned(8))) ; 555 556struct pz_device { 557 struct device_path dp; /* see above */ 558 /* struct iomod *hpa; */ 559 unsigned int hpa; /* HPA base address */ 560 /* char *spa; */ 561 unsigned int spa; /* SPA base address */ 562 /* int (*iodc_io)(struct iomod*, ...); */ 563 unsigned int iodc_io; /* device entry point */ 564 short pad; /* reserved */ 565 unsigned short cl_class;/* see below */ 566} __attribute__((aligned(8))) ; 567 568#endif /* __ASSEMBLY__ */ 569 570/* cl_class 571 * page 3-33 of IO-Firmware ARS 572 * IODC ENTRY_INIT(Search first) RET[1] 573 */ 574#define CL_NULL 0 /* invalid */ 575#define CL_RANDOM 1 /* random access (as disk) */ 576#define CL_SEQU 2 /* sequential access (as tape) */ 577#define CL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */ 578#define CL_KEYBD 8 /* half-duplex console (HIL Keyboard) */ 579#define CL_DISPL 9 /* half-duplex console (display) */ 580#define CL_FC 10 /* FiberChannel access media */ 581 582 583/* IODC ENTRY_INIT() */ 584#define ENTRY_INIT_SRCH_FRST 2 585#define ENTRY_INIT_SRCH_NEXT 3 586#define ENTRY_INIT_MOD_DEV 4 587#define ENTRY_INIT_DEV 5 588#define ENTRY_INIT_MOD 6 589#define ENTRY_INIT_MSG 9 590 591/* IODC ENTRY_IO() */ 592#define ENTRY_IO_BOOTIN 0 593#define ENTRY_IO_BOOTOUT 1 594#define ENTRY_IO_CIN 2 595#define ENTRY_IO_COUT 3 596#define ENTRY_IO_CLOSE 4 597#define ENTRY_IO_GETMSG 9 598#define ENTRY_IO_BBLOCK_IN 16 599#define ENTRY_IO_BBLOCK_OUT 17 600 601/* IODC ENTRY_SPA() */ 602 603/* IODC ENTRY_CONFIG() */ 604 605/* IODC ENTRY_TEST() */ 606 607/* IODC ENTRY_TLB() */ 608 609 610/* DEFINITION OF THE ZERO-PAGE (PAG0) */ 611/* based on work by Jason Eckhardt (jason@equator.com) */ 612 613#ifndef __ASSEMBLY__ 614 615#define PAGE0 ((struct zeropage *)__PAGE_OFFSET) 616 617struct zeropage { 618 /* [0x000] initialize vectors (VEC) */ 619 unsigned int vec_special; /* must be zero */ 620 /* int (*vec_pow_fail)(void);*/ 621 unsigned int vec_pow_fail; /* power failure handler */ 622 /* int (*vec_toc)(void); */ 623 unsigned int vec_toc; 624 unsigned int vec_toclen; 625 /* int (*vec_rendz)(void); */ 626 unsigned int vec_rendz; 627 int vec_pow_fail_flen; 628 int vec_pad[10]; 629 630 /* [0x040] reserved processor dependent */ 631 int pad0[112]; 632 633 /* [0x200] reserved */ 634 int pad1[84]; 635 636 /* [0x350] memory configuration (MC) */ 637 int memc_cont; /* contiguous mem size (bytes) */ 638 int memc_phsize; /* physical memory size */ 639 int memc_adsize; /* additional mem size, bytes of SPA space used by PDC */ 640 unsigned int mem_pdc_hi; /* used for 64-bit */ 641 642 /* [0x360] various parameters for the boot-CPU */ 643 /* unsigned int *mem_booterr[8]; */ 644 unsigned int mem_booterr[8]; /* ptr to boot errors */ 645 unsigned int mem_free; /* first location, where OS can be loaded */ 646 /* struct iomod *mem_hpa; */ 647 unsigned int mem_hpa; /* HPA of the boot-CPU */ 648 /* int (*mem_pdc)(int, ...); */ 649 unsigned int mem_pdc; /* PDC entry point */ 650 unsigned int mem_10msec; /* number of clock ticks in 10msec */ 651 652 /* [0x390] initial memory module (IMM) */ 653 /* struct iomod *imm_hpa; */ 654 unsigned int imm_hpa; /* HPA of the IMM */ 655 int imm_soft_boot; /* 0 = was hard boot, 1 = was soft boot */ 656 unsigned int imm_spa_size; /* SPA size of the IMM in bytes */ 657 unsigned int imm_max_mem; /* bytes of mem in IMM */ 658 659 /* [0x3A0] boot console, display device and keyboard */ 660 struct pz_device mem_cons; /* description of console device */ 661 struct pz_device mem_boot; /* description of boot device */ 662 struct pz_device mem_kbd; /* description of keyboard device */ 663 664 /* [0x430] reserved */ 665 int pad430[116]; 666 667 /* [0x600] processor dependent */ 668 __u32 pad600[1]; 669 __u32 proc_sti; /* pointer to STI ROM */ 670 __u32 pad608[126]; 671}; 672 673#endif /* __ASSEMBLY__ */ 674 675/* Page Zero constant offsets used by the HPMC handler */ 676 677#define BOOT_CONSOLE_HPA_OFFSET 0x3c0 678#define BOOT_CONSOLE_SPA_OFFSET 0x3c4 679#define BOOT_CONSOLE_PATH_OFFSET 0x3a8 680 681#ifndef __ASSEMBLY__ 682void pdc_console_init(void); /* in pdc_console.c */ 683void pdc_console_restart(void); 684 685void setup_pdc(void); /* in inventory.c */ 686 687/* wrapper-functions from pdc.c */ 688 689int pdc_add_valid(unsigned long address); 690int pdc_chassis_info(struct pdc_chassis_info *chassis_info, void *led_info, unsigned long len); 691int pdc_chassis_disp(unsigned long disp); 692int pdc_chassis_warn(unsigned long *warn); 693int pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info); 694int pdc_iodc_read(unsigned long *actcnt, unsigned long hpa, unsigned int index, 695 void *iodc_data, unsigned int iodc_data_size); 696int pdc_system_map_find_mods(struct pdc_system_map_mod_info *pdc_mod_info, 697 struct pdc_module_path *mod_path, long mod_index); 698int pdc_system_map_find_addrs(struct pdc_system_map_addr_info *pdc_addr_info, 699 long mod_index, long addr_index); 700int pdc_model_info(struct pdc_model *model); 701int pdc_model_sysmodel(char *name); 702int pdc_model_cpuid(unsigned long *cpu_id); 703int pdc_model_versions(unsigned long *versions, int id); 704int pdc_model_capabilities(unsigned long *capabilities); 705int pdc_cache_info(struct pdc_cache_info *cache); 706int pdc_spaceid_bits(unsigned long *space_bits); 707#ifndef CONFIG_PA20 708int pdc_btlb_info(struct pdc_btlb_info *btlb); 709int pdc_mem_map_hpa(struct pdc_memory_map *r_addr, struct pdc_module_path *mod_path); 710#endif /* !CONFIG_PA20 */ 711int pdc_lan_station_id(char *lan_addr, unsigned long net_hpa); 712 713int pdc_stable_read(unsigned long staddr, void *memaddr, unsigned long count); 714int pdc_stable_write(unsigned long staddr, void *memaddr, unsigned long count); 715int pdc_stable_get_size(unsigned long *size); 716int pdc_stable_verify_contents(void); 717int pdc_stable_initialize(void); 718 719int pdc_pci_irt_size(unsigned long *num_entries, unsigned long hpa); 720int pdc_pci_irt(unsigned long num_entries, unsigned long hpa, void *tbl); 721 722int pdc_get_initiator(struct hardware_path *, struct pdc_initiator *); 723int pdc_tod_read(struct pdc_tod *tod); 724int pdc_tod_set(unsigned long sec, unsigned long usec); 725 726#ifdef CONFIG_64BIT 727int pdc_mem_mem_table(struct pdc_memory_table_raddr *r_addr, 728 struct pdc_memory_table *tbl, unsigned long entries); 729#endif 730 731void set_firmware_width(void); 732int pdc_do_firm_test_reset(unsigned long ftc_bitmap); 733int pdc_do_reset(void); 734int pdc_soft_power_info(unsigned long *power_reg); 735int pdc_soft_power_button(int sw_control); 736void pdc_io_reset(void); 737void pdc_io_reset_devices(void); 738int pdc_iodc_getc(void); 739void pdc_iodc_putc(unsigned char c); 740void pdc_iodc_outc(unsigned char c); 741void pdc_printf(const char *fmt, ...); 742 743void pdc_emergency_unlock(void); 744int pdc_sti_call(unsigned long func, unsigned long flags, 745 unsigned long inptr, unsigned long outputr, 746 unsigned long glob_cfg); 747 748static inline char * os_id_to_string(u16 os_id) { 749 switch(os_id) { 750 case OS_ID_NONE: return "No OS"; 751 case OS_ID_HPUX: return "HP-UX"; 752 case OS_ID_MPEXL: return "MPE-iX"; 753 case OS_ID_OSF: return "OSF"; 754 case OS_ID_HPRT: return "HP-RT"; 755 case OS_ID_NOVEL: return "Novell Netware"; 756 case OS_ID_LINUX: return "Linux"; 757 default: return "Unknown"; 758 } 759} 760#endif /* __ASSEMBLY__ */ 761 762#endif /* _PARISC_PDC_H */ 763