1#ifndef X86_INTEL_ARCH_PERFMON_H 2#define X86_INTEL_ARCH_PERFMON_H 1 3 4#define MSR_ARCH_PERFMON_PERFCTR0 0xc1 5#define MSR_ARCH_PERFMON_PERFCTR1 0xc2 6 7#define MSR_ARCH_PERFMON_EVENTSEL0 0x186 8#define MSR_ARCH_PERFMON_EVENTSEL1 0x187 9 10#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22) 11#define ARCH_PERFMON_EVENTSEL_INT (1 << 20) 12#define ARCH_PERFMON_EVENTSEL_OS (1 << 17) 13#define ARCH_PERFMON_EVENTSEL_USR (1 << 16) 14 15#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL (0x3c) 16#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) 17#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX (0) 18#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ 19 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) 20 21union cpuid10_eax { 22 struct { 23 unsigned int version_id:8; 24 unsigned int num_counters:8; 25 unsigned int bit_width:8; 26 unsigned int mask_length:8; 27 } split; 28 unsigned int full; 29}; 30 31#endif /* X86_INTEL_ARCH_PERFMON_H */ 32