1#ifndef __iop_sw_mpu_defs_asm_h 2#define __iop_sw_mpu_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:10:19 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r 11 * id: $Id: iop_sw_mpu_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ 57#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 58#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 59#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 60 61/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ 62#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 63#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 64#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 65#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 66#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 67#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 68#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 69#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 70#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 71#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 72#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 73#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 74#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 75#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 76 77/* Register rw_mc_data, scope iop_sw_mpu, type rw */ 78#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 79#define reg_iop_sw_mpu_rw_mc_data___val___width 32 80#define reg_iop_sw_mpu_rw_mc_data_offset 8 81 82/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ 83#define reg_iop_sw_mpu_rw_mc_addr_offset 12 84 85/* Register rs_mc_data, scope iop_sw_mpu, type rs */ 86#define reg_iop_sw_mpu_rs_mc_data_offset 16 87 88/* Register r_mc_data, scope iop_sw_mpu, type r */ 89#define reg_iop_sw_mpu_r_mc_data_offset 20 90 91/* Register r_mc_stat, scope iop_sw_mpu, type r */ 92#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 93#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 94#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 95#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 96#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 97#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 98#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 99#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 100#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 101#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 102#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 103#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 104#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 105#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 106#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 107#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 108#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 109#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 110#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 111#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 112#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 113#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 114#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 115#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 116#define reg_iop_sw_mpu_r_mc_stat_offset 24 117 118/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ 119#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 120#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 121#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 122#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 123#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 124#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 125#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 126#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 127#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 128 129/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ 130#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 131#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 132#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 133#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 134#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 135#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 136#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 137#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 138#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 139 140/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ 141#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 142#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 143#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 144#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 145#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 146#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 147#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 148#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 149#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 150#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 151#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 152#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 153#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 154 155/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ 156#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 157#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 158#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 159#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 160#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 161#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 162#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 163#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 164#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 165#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 166#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 167#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 168#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 169 170/* Register r_bus0_in, scope iop_sw_mpu, type r */ 171#define reg_iop_sw_mpu_r_bus0_in_offset 44 172 173/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ 174#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 175#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 176#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 177#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 178#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 179#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 180#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 181#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 182#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 183 184/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ 185#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 186#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 187#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 188#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 189#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 190#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 191#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 192#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 193#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 194 195/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ 196#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 197#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 198#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 199#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 200#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 201#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 202#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 203#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 204#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 205#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 206#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 207#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 208#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 209 210/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ 211#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 212#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 213#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 214#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 215#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 216#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 217#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 218#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 219#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 220#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 221#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 222#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 223#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 224 225/* Register r_bus1_in, scope iop_sw_mpu, type r */ 226#define reg_iop_sw_mpu_r_bus1_in_offset 64 227 228/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ 229#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 230#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 231#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 232 233/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ 234#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 235#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 236#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 237 238/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ 239#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 240#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 241#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 242 243/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ 244#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 245#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 246#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 247 248/* Register r_gio_in, scope iop_sw_mpu, type r */ 249#define reg_iop_sw_mpu_r_gio_in_offset 84 250 251/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ 252#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 253#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 254#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 255#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 256#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 257#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 258#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 259#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 260#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 261#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 262#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 263#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 264#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 265#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 266#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 267#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 268#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 269#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 270#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 271#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 272#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 273#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 274#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 275#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 276#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 277#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 278#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 279#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 280#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 281#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 282#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 283#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 284#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 285#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 286#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 287#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 288#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 289#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 290#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 291#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 292#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 293#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 294#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 295#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 296#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 297#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 298#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 299#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 300#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 301#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 302#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 303#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 304#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 305#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 306#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 307#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 308#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 309#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 310#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 311#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 312#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 313#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 314#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 315#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 316#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 317#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 318#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 319#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 320#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 321#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 322#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 323#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 324#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 325#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 326#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 327#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 328#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 329#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 330#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 331#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 332#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 333#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 334#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 335#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 336#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 337#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 338#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 339#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 340#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 341#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 342#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 343#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 344#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 345#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 346#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 347#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 348#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 349 350/* Register r_cpu_intr, scope iop_sw_mpu, type r */ 351#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 352#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 353#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 354#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 355#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 356#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 357#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 358#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 359#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 360#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 361#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 362#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 363#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 364#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 365#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 366#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 367#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 368#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 369#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 370#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 371#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 372#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 373#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 374#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 375#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 376#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 377#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 378#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 379#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 380#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 381#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 382#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 383#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 384#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 385#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 386#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 387#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 388#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 389#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 390#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 391#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 392#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 393#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 394#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 395#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 396#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 397#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 398#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 399#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 400#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 401#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 402#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 403#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 404#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 405#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 406#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 407#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 408#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 409#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 410#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 411#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 412#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 413#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 414#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 415#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 416#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 417#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 418#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 419#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 420#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 421#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 422#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 423#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 424#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 425#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 426#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 427#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 428#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 429#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 430#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 431#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 432#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 433#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 434#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 435#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 436#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 437#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 438#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 439#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 440#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 441#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 442#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 443#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 444#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 445#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 446#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 447#define reg_iop_sw_mpu_r_cpu_intr_offset 92 448 449/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ 450#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 451#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 452#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 453#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 454#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 455#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 456#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 457#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 458#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 459#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 460#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 461#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 462#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 463#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 464#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 465#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 466#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 467#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 468#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 469#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 470#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 471#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 472#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 473#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 474#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 475#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 476#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 477#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 478#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 479#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 480#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 481#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 482#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 483#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 484#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 485#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 486#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 487#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 488#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 489#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 490#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 491#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 492#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 493#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 494#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 495#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 496#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 497#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 498#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 499#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 500#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 501#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 502#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 503#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 504#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 505#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 506#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 507#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 508#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 509#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 510#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 511#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 512#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 513#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 514#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 515#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 516#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 517#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 518#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 519#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 520#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 521#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 522#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 523#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 524#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 525#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 526#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 527#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 528#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 529#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 530#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 531#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 532#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 533#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 534#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 535#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 536#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 537#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 538#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 539#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 540#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 541#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 542#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 543#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 544#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 545#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 546#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 547 548/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ 549#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 550#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 551#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 552#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 553#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 554#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 555#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 556#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 557#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 558#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 559#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 560#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 561#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 562#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 563#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 564#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 565#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 566#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 567#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 568#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 569#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 570#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 571#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 572#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 573#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 574 575/* Register r_intr_grp0, scope iop_sw_mpu, type r */ 576#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 577#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 578#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 579#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 580#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 581#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 582#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 583#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 584#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 585#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 586#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 587#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 588#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 589#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 590#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 591#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 592#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 593#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 594#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 595#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 596#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 597#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 598#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 599#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 600#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 601#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 602#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 603#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 604#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 605#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 606#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 607#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 608#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 609#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 610#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 611#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 612#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 613#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 614#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 615#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 616#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 617#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 618#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 619#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 620#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 621#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 622#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 623#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 624#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 625#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 626#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 627#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 628#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 629#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 630#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 631#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 632#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 633#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 634#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 635#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 636#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 637#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 638#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 639#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 640#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 641#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 642#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 643#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 644#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 645#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 646#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 647#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 648#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 649#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 650#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 651#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 652#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 653#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 654#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 655#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 656#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 657#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 658#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 659#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 660#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 661#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 662#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 663#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 664#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 665#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 666#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 667#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 668#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 669#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 670#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 671#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 672#define reg_iop_sw_mpu_r_intr_grp0_offset 104 673 674/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ 675#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 676#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 677#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 678#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 679#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 680#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 681#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 682#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 683#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 684#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 685#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 686#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 687#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 688#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 689#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 690#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 691#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 692#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 693#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 694#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 695#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 696#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 697#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 698#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 699#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 700#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 701#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 702#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 703#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 704#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 705#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 706#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 707#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 708#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 709#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 710#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 711#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 712#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 713#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 714#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 715#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 716#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 717#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 718#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 719#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 720#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 721#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 722#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 723#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 724#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 725#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 726#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 727#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 728#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 729#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 730#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 731#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 732#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 733#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 734#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 735#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 736#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 737#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 738#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 739#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 740#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 741#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 742#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 743#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 744#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 745#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 746#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 747#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 748#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 749#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 750#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 751#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 752#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 753#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 754#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 755#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 756#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 757#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 758#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 759#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 760#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 761#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 762#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 763#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 764#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 765#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 766#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 767#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 768#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 769#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 770#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 771#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 772 773/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ 774#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 775#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 776#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 777#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 778#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 779#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 780#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 781#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 782#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 783#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 784#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 785#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 786#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 787#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 788#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 789#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 790#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 791#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 792#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 793#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 794#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 795#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 796#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 797#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 798#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 799#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 800#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 801#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 802#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 803#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 804#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 805#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 806#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 807#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 808#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 809#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 810#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 811#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 812#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 813#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 814#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 815#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 816#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 817#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 818#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 819#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 820#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 821#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 822#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 823#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 824#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 825#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 826#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 827#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 828#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 829#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 830#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 831#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 832#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 833#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 834#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 835#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 836#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 837#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 838#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 839#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 840#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 841#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 842#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 843#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 844#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 845#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 846#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 847#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 848#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 849#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 850#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 851#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 852#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 853#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 854#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 855#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 856#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 857#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 858#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 859#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 860#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 861#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 862#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 863#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 864#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 865#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 866#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 867#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 868#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 869#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 870#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 871 872/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ 873#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 874#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 875#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 876#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 877#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 878#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 879#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 880#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 881#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 882#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 883#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 884#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 885#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 886#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 887#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 888#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 889#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 890#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 891#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 892#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 893#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 894#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 895#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 896#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 897#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 898 899/* Register r_intr_grp1, scope iop_sw_mpu, type r */ 900#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 901#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 902#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 903#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 904#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 905#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 906#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 907#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 908#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 909#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 910#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 911#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 912#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 913#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 914#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 915#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 916#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 917#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 918#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 919#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 920#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 921#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 922#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 923#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 924#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 925#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 926#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 927#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 928#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 929#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 930#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 931#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 932#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 933#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 934#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 935#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 936#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 937#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 938#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 939#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 940#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 941#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 942#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 943#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 944#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 945#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 946#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 947#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 948#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 949#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 950#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 951#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 952#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 953#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 954#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 955#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 956#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 957#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 958#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 959#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 960#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 961#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 962#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 963#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 964#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 965#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 966#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 967#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 968#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 969#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 970#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 971#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 972#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 973#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 974#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 975#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 976#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 977#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 978#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 979#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 980#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 981#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 982#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 983#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 984#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 985#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 986#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 987#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 988#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 989#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 990#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 991#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 992#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 993#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 994#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 995#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 996#define reg_iop_sw_mpu_r_intr_grp1_offset 120 997 998/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ 999#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 1000#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 1001#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 1002#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 1003#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 1004#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 1005#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 1006#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 1007#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 1008#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 1009#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 1010#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 1011#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 1012#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 1013#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 1014#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 1015#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 1016#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 1017#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 1018#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 1019#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 1020#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 1021#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 1022#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 1023#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 1024#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 1025#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 1026#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 1027#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 1028#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 1029#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 1030#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 1031#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 1032#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 1033#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 1034#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 1035#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 1036#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 1037#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 1038#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 1039#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 1040#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 1041#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 1042#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 1043#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 1044#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 1045#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 1046#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 1047#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 1048#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 1049#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 1050#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 1051#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 1052#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 1053#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 1054#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 1055#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 1056#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 1057#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 1058#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 1059#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 1060#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 1061#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 1062#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 1063#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 1064#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 1065#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 1066#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 1067#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 1068#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 1069#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 1070#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 1071#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 1072#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 1073#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 1074#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 1075#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 1076#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 1077#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 1078#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 1079#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 1080#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 1081#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 1082#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 1083#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 1084#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 1085#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 1086#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 1087#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 1088#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 1089#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 1090#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 1091#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 1092#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 1093#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 1094#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 1095#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 1096 1097/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ 1098#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 1099#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 1100#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 1101#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 1102#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 1103#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 1104#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 1105#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 1106#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 1107#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 1108#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 1109#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 1110#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 1111#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 1112#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 1113#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 1114#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 1115#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 1116#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 1117#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 1118#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 1119#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 1120#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 1121#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 1122#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 1123#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 1124#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 1125#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 1126#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 1127#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 1128#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 1129#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 1130#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 1131#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 1132#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 1133#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 1134#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 1135#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 1136#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 1137#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 1138#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 1139#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 1140#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 1141#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 1142#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 1143#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 1144#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 1145#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 1146#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 1147#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 1148#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 1149#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 1150#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 1151#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 1152#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 1153#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 1154#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 1155#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 1156#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 1157#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 1158#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 1159#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 1160#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 1161#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 1162#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 1163#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 1164#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 1165#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 1166#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 1167#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 1168#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 1169#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 1170#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 1171#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 1172#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 1173#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 1174#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 1175#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 1176#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 1177#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 1178#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 1179#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 1180#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 1181#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 1182#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 1183#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 1184#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 1185#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 1186#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 1187#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 1188#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 1189#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 1190#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 1191#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 1192#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 1193#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 1194#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 1195 1196/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ 1197#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 1198#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 1199#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 1200#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 1201#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 1202#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 1203#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 1204#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 1205#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 1206#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 1207#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 1208#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 1209#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 1210#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 1211#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 1212#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 1213#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 1214#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 1215#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 1216#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 1217#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 1218#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 1219#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 1220#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 1221#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 1222 1223/* Register r_intr_grp2, scope iop_sw_mpu, type r */ 1224#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 1225#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 1226#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 1227#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 1228#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 1229#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 1230#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 1231#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 1232#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 1233#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 1234#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 1235#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 1236#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 1237#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 1238#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 1239#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 1240#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 1241#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 1242#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 1243#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 1244#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 1245#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 1246#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 1247#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 1248#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 1249#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 1250#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 1251#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 1252#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 1253#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 1254#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 1255#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 1256#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 1257#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 1258#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 1259#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 1260#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 1261#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 1262#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 1263#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 1264#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 1265#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 1266#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 1267#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 1268#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 1269#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 1270#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 1271#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 1272#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 1273#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 1274#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 1275#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 1276#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 1277#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 1278#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 1279#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 1280#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 1281#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 1282#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 1283#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 1284#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 1285#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 1286#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 1287#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 1288#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 1289#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 1290#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 1291#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 1292#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 1293#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 1294#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 1295#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 1296#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 1297#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 1298#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 1299#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 1300#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 1301#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 1302#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 1303#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 1304#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 1305#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 1306#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 1307#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 1308#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 1309#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 1310#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 1311#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 1312#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 1313#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 1314#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 1315#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 1316#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 1317#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 1318#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 1319#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 1320#define reg_iop_sw_mpu_r_intr_grp2_offset 136 1321 1322/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ 1323#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 1324#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 1325#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 1326#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 1327#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 1328#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 1329#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 1330#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 1331#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 1332#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 1333#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 1334#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 1335#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 1336#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 1337#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 1338#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 1339#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 1340#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 1341#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 1342#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 1343#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 1344#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 1345#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 1346#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 1347#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 1348#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 1349#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 1350#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 1351#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 1352#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 1353#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 1354#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 1355#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 1356#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 1357#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 1358#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 1359#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 1360#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 1361#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 1362#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 1363#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 1364#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 1365#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 1366#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 1367#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 1368#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 1369#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 1370#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 1371#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 1372#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 1373#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 1374#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 1375#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 1376#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 1377#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 1378#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 1379#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 1380#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 1381#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 1382#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 1383#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 1384#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 1385#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 1386#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 1387#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 1388#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 1389#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 1390#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 1391#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 1392#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 1393#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 1394#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 1395#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 1396#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 1397#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 1398#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 1399#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 1400#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 1401#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 1402#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 1403#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 1404#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 1405#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 1406#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 1407#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 1408#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 1409#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 1410#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 1411#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 1412#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 1413#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 1414#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 1415#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 1416#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 1417#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 1418#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 1419#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 1420 1421/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ 1422#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 1423#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 1424#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 1425#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 1426#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 1427#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 1428#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 1429#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 1430#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 1431#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 1432#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 1433#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 1434#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 1435#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 1436#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 1437#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 1438#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 1439#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 1440#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 1441#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 1442#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 1443#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 1444#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 1445#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 1446#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 1447#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 1448#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 1449#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 1450#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 1451#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 1452#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 1453#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 1454#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 1455#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 1456#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 1457#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 1458#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 1459#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 1460#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 1461#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 1462#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 1463#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 1464#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 1465#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 1466#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 1467#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 1468#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 1469#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 1470#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 1471#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 1472#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 1473#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 1474#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 1475#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 1476#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 1477#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 1478#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 1479#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 1480#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 1481#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 1482#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 1483#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 1484#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 1485#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 1486#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 1487#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 1488#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 1489#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 1490#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 1491#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 1492#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 1493#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 1494#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 1495#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 1496#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 1497#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 1498#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 1499#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 1500#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 1501#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 1502#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 1503#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 1504#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 1505#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 1506#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 1507#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 1508#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 1509#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 1510#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 1511#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 1512#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 1513#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 1514#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 1515#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 1516#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 1517#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 1518#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 1519 1520/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ 1521#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 1522#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 1523#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 1524#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 1525#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 1526#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 1527#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 1528#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 1529#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 1530#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 1531#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 1532#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 1533#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 1534#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 1535#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 1536#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 1537#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 1538#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 1539#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 1540#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 1541#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 1542#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 1543#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 1544#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 1545#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 1546 1547/* Register r_intr_grp3, scope iop_sw_mpu, type r */ 1548#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 1549#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 1550#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 1551#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 1552#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 1553#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 1554#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 1555#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 1556#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 1557#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 1558#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 1559#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 1560#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 1561#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 1562#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 1563#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 1564#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 1565#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 1566#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 1567#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 1568#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 1569#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 1570#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 1571#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 1572#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 1573#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 1574#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 1575#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 1576#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 1577#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 1578#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 1579#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 1580#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 1581#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 1582#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 1583#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 1584#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 1585#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 1586#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 1587#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 1588#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 1589#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 1590#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 1591#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 1592#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 1593#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 1594#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 1595#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 1596#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 1597#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 1598#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 1599#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 1600#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 1601#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 1602#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 1603#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 1604#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 1605#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 1606#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 1607#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 1608#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 1609#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 1610#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 1611#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 1612#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 1613#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 1614#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 1615#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 1616#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 1617#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 1618#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 1619#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 1620#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 1621#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 1622#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 1623#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 1624#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 1625#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 1626#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 1627#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 1628#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 1629#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 1630#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 1631#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 1632#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 1633#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 1634#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 1635#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 1636#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 1637#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 1638#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 1639#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 1640#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 1641#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 1642#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 1643#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 1644#define reg_iop_sw_mpu_r_intr_grp3_offset 152 1645 1646/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ 1647#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 1648#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 1649#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 1650#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 1651#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 1652#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 1653#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 1654#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 1655#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 1656#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 1657#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 1658#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 1659#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 1660#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 1661#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 1662#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 1663#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 1664#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 1665#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 1666#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 1667#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 1668#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 1669#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 1670#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 1671#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 1672#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 1673#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 1674#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 1675#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 1676#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 1677#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 1678#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 1679#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 1680#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 1681#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 1682#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 1683#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 1684#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 1685#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 1686#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 1687#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 1688#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 1689#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 1690#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 1691#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 1692#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 1693#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 1694#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 1695#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 1696#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 1697#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 1698#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 1699#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 1700#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 1701#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 1702#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 1703#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 1704#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 1705#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 1706#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 1707#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 1708#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 1709#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 1710#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 1711#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 1712#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 1713#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 1714#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 1715#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 1716#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 1717#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 1718#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 1719#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 1720#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 1721#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 1722#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 1723#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 1724#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 1725#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 1726#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 1727#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 1728#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 1729#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 1730#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 1731#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 1732#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 1733#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 1734#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 1735#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 1736#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 1737#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 1738#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 1739#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 1740#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 1741#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 1742#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 1743#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 1744 1745 1746/* Constants */ 1747#define regk_iop_sw_mpu_copy 0x00000000 1748#define regk_iop_sw_mpu_cpu 0x00000000 1749#define regk_iop_sw_mpu_mpu 0x00000001 1750#define regk_iop_sw_mpu_no 0x00000000 1751#define regk_iop_sw_mpu_nop 0x00000000 1752#define regk_iop_sw_mpu_rd 0x00000002 1753#define regk_iop_sw_mpu_reg_copy 0x00000001 1754#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 1755#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 1756#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 1757#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 1758#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 1759#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 1760#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 1761#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 1762#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 1763#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 1764#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 1765#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 1766#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 1767#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 1768#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 1769#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 1770#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 1771#define regk_iop_sw_mpu_set 0x00000001 1772#define regk_iop_sw_mpu_spu0 0x00000002 1773#define regk_iop_sw_mpu_spu1 0x00000003 1774#define regk_iop_sw_mpu_wr 0x00000003 1775#define regk_iop_sw_mpu_yes 0x00000001 1776#endif /* __iop_sw_mpu_defs_asm_h */ 1777