1#ifndef __iop_dmc_out_defs_asm_h 2#define __iop_dmc_out_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/iop_dmc_out.r 7 * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp 8 * last modfied: Mon Apr 11 16:08:45 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r 11 * id: $Id: iop_dmc_out_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_cfg, scope iop_dmc_out, type rw */ 57#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 58#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 59#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 60#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 61#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 62#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 63#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 64#define reg_iop_dmc_out_rw_cfg_offset 0 65 66/* Register rw_ctrl, scope iop_dmc_out, type rw */ 67#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 68#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 69#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 70#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 71#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 72#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 73#define reg_iop_dmc_out_rw_ctrl_offset 4 74 75/* Register r_stat, scope iop_dmc_out, type r */ 76#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 77#define reg_iop_dmc_out_r_stat___dif_en___width 1 78#define reg_iop_dmc_out_r_stat___dif_en___bit 0 79#define reg_iop_dmc_out_r_stat_offset 8 80 81/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ 82#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 83#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 84#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 85#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 86#define reg_iop_dmc_out_rw_stream_cmd_offset 12 87 88/* Register rs_stream_data, scope iop_dmc_out, type rs */ 89#define reg_iop_dmc_out_rs_stream_data_offset 16 90 91/* Register r_stream_data, scope iop_dmc_out, type r */ 92#define reg_iop_dmc_out_r_stream_data_offset 20 93 94/* Register r_stream_stat, scope iop_dmc_out, type r */ 95#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 96#define reg_iop_dmc_out_r_stream_stat___dth___width 7 97#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 98#define reg_iop_dmc_out_r_stream_stat___dv___width 1 99#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 100#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 101#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 102#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 103#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 104#define reg_iop_dmc_out_r_stream_stat___last___width 1 105#define reg_iop_dmc_out_r_stream_stat___last___bit 18 106#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 107#define reg_iop_dmc_out_r_stream_stat___size___width 3 108#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 109#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 110#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 111#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 112#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 113#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 114#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 115#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 116#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 117#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 118#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 119#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 120#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 121#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 122#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 123#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 124#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 125#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 126#define reg_iop_dmc_out_r_stream_stat_offset 24 127 128/* Register r_data_descr, scope iop_dmc_out, type r */ 129#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 130#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 131#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 132#define reg_iop_dmc_out_r_data_descr___stat___width 8 133#define reg_iop_dmc_out_r_data_descr___md___lsb 16 134#define reg_iop_dmc_out_r_data_descr___md___width 16 135#define reg_iop_dmc_out_r_data_descr_offset 28 136 137/* Register r_ctxt_descr, scope iop_dmc_out, type r */ 138#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 139#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 140#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 141#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 142#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 143#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 144#define reg_iop_dmc_out_r_ctxt_descr_offset 32 145 146/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ 147#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 148 149/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ 150#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 151 152/* Register r_group_descr, scope iop_dmc_out, type r */ 153#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 154#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 155#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 156#define reg_iop_dmc_out_r_group_descr___stat___width 8 157#define reg_iop_dmc_out_r_group_descr___md___lsb 16 158#define reg_iop_dmc_out_r_group_descr___md___width 16 159#define reg_iop_dmc_out_r_group_descr_offset 52 160 161/* Register rw_data_descr, scope iop_dmc_out, type rw */ 162#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 163#define reg_iop_dmc_out_rw_data_descr___md___width 16 164#define reg_iop_dmc_out_rw_data_descr_offset 56 165 166/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ 167#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 168#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 169#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 170 171/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ 172#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 173 174/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ 175#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 176 177/* Register rw_group_descr, scope iop_dmc_out, type rw */ 178#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 179#define reg_iop_dmc_out_rw_group_descr___md___width 16 180#define reg_iop_dmc_out_rw_group_descr_offset 80 181 182/* Register rw_intr_mask, scope iop_dmc_out, type rw */ 183#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 184#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 185#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 186#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 187#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 188#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 189#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 190#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 191#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 192#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 193#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 194#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 195#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 196#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 197#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 198#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 199#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 200#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 201#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 202#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 203#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 204#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 205#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 206#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 207#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 208#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 209#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 210#define reg_iop_dmc_out_rw_intr_mask_offset 84 211 212/* Register rw_ack_intr, scope iop_dmc_out, type rw */ 213#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 214#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 215#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 216#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 217#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 218#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 219#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 220#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 221#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 222#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 223#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 224#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 225#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 226#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 227#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 228#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 229#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 230#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 231#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 232#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 233#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 234#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 235#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 236#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 237#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 238#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 239#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 240#define reg_iop_dmc_out_rw_ack_intr_offset 88 241 242/* Register r_intr, scope iop_dmc_out, type r */ 243#define reg_iop_dmc_out_r_intr___data_md___lsb 0 244#define reg_iop_dmc_out_r_intr___data_md___width 1 245#define reg_iop_dmc_out_r_intr___data_md___bit 0 246#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 247#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 248#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 249#define reg_iop_dmc_out_r_intr___group_md___lsb 2 250#define reg_iop_dmc_out_r_intr___group_md___width 1 251#define reg_iop_dmc_out_r_intr___group_md___bit 2 252#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 253#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 254#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 255#define reg_iop_dmc_out_r_intr___dth___lsb 4 256#define reg_iop_dmc_out_r_intr___dth___width 1 257#define reg_iop_dmc_out_r_intr___dth___bit 4 258#define reg_iop_dmc_out_r_intr___dv___lsb 5 259#define reg_iop_dmc_out_r_intr___dv___width 1 260#define reg_iop_dmc_out_r_intr___dv___bit 5 261#define reg_iop_dmc_out_r_intr___last_data___lsb 6 262#define reg_iop_dmc_out_r_intr___last_data___width 1 263#define reg_iop_dmc_out_r_intr___last_data___bit 6 264#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 265#define reg_iop_dmc_out_r_intr___trf_lim___width 1 266#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 267#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 268#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 269#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 270#define reg_iop_dmc_out_r_intr_offset 92 271 272/* Register r_masked_intr, scope iop_dmc_out, type r */ 273#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 274#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 275#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 276#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 277#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 278#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 279#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 280#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 281#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 282#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 283#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 284#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 285#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 286#define reg_iop_dmc_out_r_masked_intr___dth___width 1 287#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 288#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 289#define reg_iop_dmc_out_r_masked_intr___dv___width 1 290#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 291#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 292#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 293#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 294#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 295#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 296#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 297#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 298#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 299#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 300#define reg_iop_dmc_out_r_masked_intr_offset 96 301 302 303/* Constants */ 304#define regk_iop_dmc_out_ack_pkt 0x00000100 305#define regk_iop_dmc_out_array 0x00000008 306#define regk_iop_dmc_out_burst 0x00000020 307#define regk_iop_dmc_out_copy_next 0x00000010 308#define regk_iop_dmc_out_copy_up 0x00000020 309#define regk_iop_dmc_out_dis_c 0x00000010 310#define regk_iop_dmc_out_dis_g 0x00000020 311#define regk_iop_dmc_out_lim1 0x00000000 312#define regk_iop_dmc_out_lim16 0x00000004 313#define regk_iop_dmc_out_lim2 0x00000001 314#define regk_iop_dmc_out_lim32 0x00000005 315#define regk_iop_dmc_out_lim4 0x00000002 316#define regk_iop_dmc_out_lim64 0x00000006 317#define regk_iop_dmc_out_lim8 0x00000003 318#define regk_iop_dmc_out_load_c 0x00000200 319#define regk_iop_dmc_out_load_c_n 0x00000280 320#define regk_iop_dmc_out_load_c_next 0x00000240 321#define regk_iop_dmc_out_load_d 0x00000140 322#define regk_iop_dmc_out_load_g 0x00000300 323#define regk_iop_dmc_out_load_g_down 0x000003c0 324#define regk_iop_dmc_out_load_g_next 0x00000340 325#define regk_iop_dmc_out_load_g_up 0x00000380 326#define regk_iop_dmc_out_next_en 0x00000010 327#define regk_iop_dmc_out_next_pkt 0x00000010 328#define regk_iop_dmc_out_no 0x00000000 329#define regk_iop_dmc_out_restore 0x00000020 330#define regk_iop_dmc_out_rw_cfg_default 0x00000000 331#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 332#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 333#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 334#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 335#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 336#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 337#define regk_iop_dmc_out_save_down 0x00000020 338#define regk_iop_dmc_out_save_up 0x00000020 339#define regk_iop_dmc_out_set_reg 0x00000050 340#define regk_iop_dmc_out_set_w_size1 0x00000190 341#define regk_iop_dmc_out_set_w_size2 0x000001a0 342#define regk_iop_dmc_out_set_w_size4 0x000001c0 343#define regk_iop_dmc_out_store_c 0x00000002 344#define regk_iop_dmc_out_store_descr 0x00000000 345#define regk_iop_dmc_out_store_g 0x00000004 346#define regk_iop_dmc_out_store_md 0x00000001 347#define regk_iop_dmc_out_update_down 0x00000020 348#define regk_iop_dmc_out_yes 0x00000001 349#endif /* __iop_dmc_out_defs_asm_h */ 350