1#ifndef __eth_defs_asm_h 2#define __eth_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: ../../inst/eth/rtl/eth_regs.r 7 * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp 8 * last modfied: Mon Apr 11 16:07:03 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r 11 * id: $Id: eth_defs_asm.h,v 1.1.1.1 2007/08/03 18:53:23 Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17#ifndef REG_FIELD 18#define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20#define REG_FIELD_X_( value, shift ) ((value) << shift) 21#endif 22 23#ifndef REG_STATE 24#define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26#define REG_STATE_X_( k, shift ) (k << shift) 27#endif 28 29#ifndef REG_MASK 30#define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33#endif 34 35#ifndef REG_LSB 36#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37#endif 38 39#ifndef REG_BIT 40#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41#endif 42 43#ifndef REG_ADDR 44#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46#endif 47 48#ifndef REG_ADDR_VECT 49#define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54#endif 55 56/* Register rw_ma0_lo, scope eth, type rw */ 57#define reg_eth_rw_ma0_lo___addr___lsb 0 58#define reg_eth_rw_ma0_lo___addr___width 32 59#define reg_eth_rw_ma0_lo_offset 0 60 61/* Register rw_ma0_hi, scope eth, type rw */ 62#define reg_eth_rw_ma0_hi___addr___lsb 0 63#define reg_eth_rw_ma0_hi___addr___width 16 64#define reg_eth_rw_ma0_hi_offset 4 65 66/* Register rw_ma1_lo, scope eth, type rw */ 67#define reg_eth_rw_ma1_lo___addr___lsb 0 68#define reg_eth_rw_ma1_lo___addr___width 32 69#define reg_eth_rw_ma1_lo_offset 8 70 71/* Register rw_ma1_hi, scope eth, type rw */ 72#define reg_eth_rw_ma1_hi___addr___lsb 0 73#define reg_eth_rw_ma1_hi___addr___width 16 74#define reg_eth_rw_ma1_hi_offset 12 75 76/* Register rw_ga_lo, scope eth, type rw */ 77#define reg_eth_rw_ga_lo___table___lsb 0 78#define reg_eth_rw_ga_lo___table___width 32 79#define reg_eth_rw_ga_lo_offset 16 80 81/* Register rw_ga_hi, scope eth, type rw */ 82#define reg_eth_rw_ga_hi___table___lsb 0 83#define reg_eth_rw_ga_hi___table___width 32 84#define reg_eth_rw_ga_hi_offset 20 85 86/* Register rw_gen_ctrl, scope eth, type rw */ 87#define reg_eth_rw_gen_ctrl___en___lsb 0 88#define reg_eth_rw_gen_ctrl___en___width 1 89#define reg_eth_rw_gen_ctrl___en___bit 0 90#define reg_eth_rw_gen_ctrl___phy___lsb 1 91#define reg_eth_rw_gen_ctrl___phy___width 2 92#define reg_eth_rw_gen_ctrl___protocol___lsb 3 93#define reg_eth_rw_gen_ctrl___protocol___width 1 94#define reg_eth_rw_gen_ctrl___protocol___bit 3 95#define reg_eth_rw_gen_ctrl___loopback___lsb 4 96#define reg_eth_rw_gen_ctrl___loopback___width 1 97#define reg_eth_rw_gen_ctrl___loopback___bit 4 98#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 99#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 100#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 101#define reg_eth_rw_gen_ctrl_offset 24 102 103/* Register rw_rec_ctrl, scope eth, type rw */ 104#define reg_eth_rw_rec_ctrl___ma0___lsb 0 105#define reg_eth_rw_rec_ctrl___ma0___width 1 106#define reg_eth_rw_rec_ctrl___ma0___bit 0 107#define reg_eth_rw_rec_ctrl___ma1___lsb 1 108#define reg_eth_rw_rec_ctrl___ma1___width 1 109#define reg_eth_rw_rec_ctrl___ma1___bit 1 110#define reg_eth_rw_rec_ctrl___individual___lsb 2 111#define reg_eth_rw_rec_ctrl___individual___width 1 112#define reg_eth_rw_rec_ctrl___individual___bit 2 113#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 114#define reg_eth_rw_rec_ctrl___broadcast___width 1 115#define reg_eth_rw_rec_ctrl___broadcast___bit 3 116#define reg_eth_rw_rec_ctrl___undersize___lsb 4 117#define reg_eth_rw_rec_ctrl___undersize___width 1 118#define reg_eth_rw_rec_ctrl___undersize___bit 4 119#define reg_eth_rw_rec_ctrl___oversize___lsb 5 120#define reg_eth_rw_rec_ctrl___oversize___width 1 121#define reg_eth_rw_rec_ctrl___oversize___bit 5 122#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 123#define reg_eth_rw_rec_ctrl___bad_crc___width 1 124#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 125#define reg_eth_rw_rec_ctrl___duplex___lsb 7 126#define reg_eth_rw_rec_ctrl___duplex___width 1 127#define reg_eth_rw_rec_ctrl___duplex___bit 7 128#define reg_eth_rw_rec_ctrl___max_size___lsb 8 129#define reg_eth_rw_rec_ctrl___max_size___width 1 130#define reg_eth_rw_rec_ctrl___max_size___bit 8 131#define reg_eth_rw_rec_ctrl_offset 28 132 133/* Register rw_tr_ctrl, scope eth, type rw */ 134#define reg_eth_rw_tr_ctrl___crc___lsb 0 135#define reg_eth_rw_tr_ctrl___crc___width 1 136#define reg_eth_rw_tr_ctrl___crc___bit 0 137#define reg_eth_rw_tr_ctrl___pad___lsb 1 138#define reg_eth_rw_tr_ctrl___pad___width 1 139#define reg_eth_rw_tr_ctrl___pad___bit 1 140#define reg_eth_rw_tr_ctrl___retry___lsb 2 141#define reg_eth_rw_tr_ctrl___retry___width 1 142#define reg_eth_rw_tr_ctrl___retry___bit 2 143#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 144#define reg_eth_rw_tr_ctrl___ignore_col___width 1 145#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 146#define reg_eth_rw_tr_ctrl___cancel___lsb 4 147#define reg_eth_rw_tr_ctrl___cancel___width 1 148#define reg_eth_rw_tr_ctrl___cancel___bit 4 149#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 150#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 151#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 152#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 153#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 154#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 155#define reg_eth_rw_tr_ctrl_offset 32 156 157/* Register rw_clr_err, scope eth, type rw */ 158#define reg_eth_rw_clr_err___clr___lsb 0 159#define reg_eth_rw_clr_err___clr___width 1 160#define reg_eth_rw_clr_err___clr___bit 0 161#define reg_eth_rw_clr_err_offset 36 162 163/* Register rw_mgm_ctrl, scope eth, type rw */ 164#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 165#define reg_eth_rw_mgm_ctrl___mdio___width 1 166#define reg_eth_rw_mgm_ctrl___mdio___bit 0 167#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 168#define reg_eth_rw_mgm_ctrl___mdoe___width 1 169#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 170#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 171#define reg_eth_rw_mgm_ctrl___mdc___width 1 172#define reg_eth_rw_mgm_ctrl___mdc___bit 2 173#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 174#define reg_eth_rw_mgm_ctrl___phyclk___width 1 175#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 176#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 177#define reg_eth_rw_mgm_ctrl___txdata___width 4 178#define reg_eth_rw_mgm_ctrl___txen___lsb 8 179#define reg_eth_rw_mgm_ctrl___txen___width 1 180#define reg_eth_rw_mgm_ctrl___txen___bit 8 181#define reg_eth_rw_mgm_ctrl_offset 40 182 183/* Register r_stat, scope eth, type r */ 184#define reg_eth_r_stat___mdio___lsb 0 185#define reg_eth_r_stat___mdio___width 1 186#define reg_eth_r_stat___mdio___bit 0 187#define reg_eth_r_stat___exc_col___lsb 1 188#define reg_eth_r_stat___exc_col___width 1 189#define reg_eth_r_stat___exc_col___bit 1 190#define reg_eth_r_stat___urun___lsb 2 191#define reg_eth_r_stat___urun___width 1 192#define reg_eth_r_stat___urun___bit 2 193#define reg_eth_r_stat___phyclk___lsb 3 194#define reg_eth_r_stat___phyclk___width 1 195#define reg_eth_r_stat___phyclk___bit 3 196#define reg_eth_r_stat___txdata___lsb 4 197#define reg_eth_r_stat___txdata___width 4 198#define reg_eth_r_stat___txen___lsb 8 199#define reg_eth_r_stat___txen___width 1 200#define reg_eth_r_stat___txen___bit 8 201#define reg_eth_r_stat___col___lsb 9 202#define reg_eth_r_stat___col___width 1 203#define reg_eth_r_stat___col___bit 9 204#define reg_eth_r_stat___crs___lsb 10 205#define reg_eth_r_stat___crs___width 1 206#define reg_eth_r_stat___crs___bit 10 207#define reg_eth_r_stat___txclk___lsb 11 208#define reg_eth_r_stat___txclk___width 1 209#define reg_eth_r_stat___txclk___bit 11 210#define reg_eth_r_stat___rxdata___lsb 12 211#define reg_eth_r_stat___rxdata___width 4 212#define reg_eth_r_stat___rxer___lsb 16 213#define reg_eth_r_stat___rxer___width 1 214#define reg_eth_r_stat___rxer___bit 16 215#define reg_eth_r_stat___rxdv___lsb 17 216#define reg_eth_r_stat___rxdv___width 1 217#define reg_eth_r_stat___rxdv___bit 17 218#define reg_eth_r_stat___rxclk___lsb 18 219#define reg_eth_r_stat___rxclk___width 1 220#define reg_eth_r_stat___rxclk___bit 18 221#define reg_eth_r_stat_offset 44 222 223/* Register rs_rec_cnt, scope eth, type rs */ 224#define reg_eth_rs_rec_cnt___crc_err___lsb 0 225#define reg_eth_rs_rec_cnt___crc_err___width 8 226#define reg_eth_rs_rec_cnt___align_err___lsb 8 227#define reg_eth_rs_rec_cnt___align_err___width 8 228#define reg_eth_rs_rec_cnt___oversize___lsb 16 229#define reg_eth_rs_rec_cnt___oversize___width 8 230#define reg_eth_rs_rec_cnt___congestion___lsb 24 231#define reg_eth_rs_rec_cnt___congestion___width 8 232#define reg_eth_rs_rec_cnt_offset 48 233 234/* Register r_rec_cnt, scope eth, type r */ 235#define reg_eth_r_rec_cnt___crc_err___lsb 0 236#define reg_eth_r_rec_cnt___crc_err___width 8 237#define reg_eth_r_rec_cnt___align_err___lsb 8 238#define reg_eth_r_rec_cnt___align_err___width 8 239#define reg_eth_r_rec_cnt___oversize___lsb 16 240#define reg_eth_r_rec_cnt___oversize___width 8 241#define reg_eth_r_rec_cnt___congestion___lsb 24 242#define reg_eth_r_rec_cnt___congestion___width 8 243#define reg_eth_r_rec_cnt_offset 52 244 245/* Register rs_tr_cnt, scope eth, type rs */ 246#define reg_eth_rs_tr_cnt___single_col___lsb 0 247#define reg_eth_rs_tr_cnt___single_col___width 8 248#define reg_eth_rs_tr_cnt___mult_col___lsb 8 249#define reg_eth_rs_tr_cnt___mult_col___width 8 250#define reg_eth_rs_tr_cnt___late_col___lsb 16 251#define reg_eth_rs_tr_cnt___late_col___width 8 252#define reg_eth_rs_tr_cnt___deferred___lsb 24 253#define reg_eth_rs_tr_cnt___deferred___width 8 254#define reg_eth_rs_tr_cnt_offset 56 255 256/* Register r_tr_cnt, scope eth, type r */ 257#define reg_eth_r_tr_cnt___single_col___lsb 0 258#define reg_eth_r_tr_cnt___single_col___width 8 259#define reg_eth_r_tr_cnt___mult_col___lsb 8 260#define reg_eth_r_tr_cnt___mult_col___width 8 261#define reg_eth_r_tr_cnt___late_col___lsb 16 262#define reg_eth_r_tr_cnt___late_col___width 8 263#define reg_eth_r_tr_cnt___deferred___lsb 24 264#define reg_eth_r_tr_cnt___deferred___width 8 265#define reg_eth_r_tr_cnt_offset 60 266 267/* Register rs_phy_cnt, scope eth, type rs */ 268#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 269#define reg_eth_rs_phy_cnt___carrier_loss___width 8 270#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 271#define reg_eth_rs_phy_cnt___sqe_err___width 8 272#define reg_eth_rs_phy_cnt_offset 64 273 274/* Register r_phy_cnt, scope eth, type r */ 275#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 276#define reg_eth_r_phy_cnt___carrier_loss___width 8 277#define reg_eth_r_phy_cnt___sqe_err___lsb 8 278#define reg_eth_r_phy_cnt___sqe_err___width 8 279#define reg_eth_r_phy_cnt_offset 68 280 281/* Register rw_test_ctrl, scope eth, type rw */ 282#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 283#define reg_eth_rw_test_ctrl___snmp_inc___width 1 284#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 285#define reg_eth_rw_test_ctrl___snmp___lsb 1 286#define reg_eth_rw_test_ctrl___snmp___width 1 287#define reg_eth_rw_test_ctrl___snmp___bit 1 288#define reg_eth_rw_test_ctrl___backoff___lsb 2 289#define reg_eth_rw_test_ctrl___backoff___width 1 290#define reg_eth_rw_test_ctrl___backoff___bit 2 291#define reg_eth_rw_test_ctrl_offset 72 292 293/* Register rw_intr_mask, scope eth, type rw */ 294#define reg_eth_rw_intr_mask___crc___lsb 0 295#define reg_eth_rw_intr_mask___crc___width 1 296#define reg_eth_rw_intr_mask___crc___bit 0 297#define reg_eth_rw_intr_mask___align___lsb 1 298#define reg_eth_rw_intr_mask___align___width 1 299#define reg_eth_rw_intr_mask___align___bit 1 300#define reg_eth_rw_intr_mask___oversize___lsb 2 301#define reg_eth_rw_intr_mask___oversize___width 1 302#define reg_eth_rw_intr_mask___oversize___bit 2 303#define reg_eth_rw_intr_mask___congestion___lsb 3 304#define reg_eth_rw_intr_mask___congestion___width 1 305#define reg_eth_rw_intr_mask___congestion___bit 3 306#define reg_eth_rw_intr_mask___single_col___lsb 4 307#define reg_eth_rw_intr_mask___single_col___width 1 308#define reg_eth_rw_intr_mask___single_col___bit 4 309#define reg_eth_rw_intr_mask___mult_col___lsb 5 310#define reg_eth_rw_intr_mask___mult_col___width 1 311#define reg_eth_rw_intr_mask___mult_col___bit 5 312#define reg_eth_rw_intr_mask___late_col___lsb 6 313#define reg_eth_rw_intr_mask___late_col___width 1 314#define reg_eth_rw_intr_mask___late_col___bit 6 315#define reg_eth_rw_intr_mask___deferred___lsb 7 316#define reg_eth_rw_intr_mask___deferred___width 1 317#define reg_eth_rw_intr_mask___deferred___bit 7 318#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 319#define reg_eth_rw_intr_mask___carrier_loss___width 1 320#define reg_eth_rw_intr_mask___carrier_loss___bit 8 321#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 322#define reg_eth_rw_intr_mask___sqe_test_err___width 1 323#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 324#define reg_eth_rw_intr_mask___orun___lsb 10 325#define reg_eth_rw_intr_mask___orun___width 1 326#define reg_eth_rw_intr_mask___orun___bit 10 327#define reg_eth_rw_intr_mask___urun___lsb 11 328#define reg_eth_rw_intr_mask___urun___width 1 329#define reg_eth_rw_intr_mask___urun___bit 11 330#define reg_eth_rw_intr_mask___excessive_col___lsb 12 331#define reg_eth_rw_intr_mask___excessive_col___width 1 332#define reg_eth_rw_intr_mask___excessive_col___bit 12 333#define reg_eth_rw_intr_mask___mdio___lsb 13 334#define reg_eth_rw_intr_mask___mdio___width 1 335#define reg_eth_rw_intr_mask___mdio___bit 13 336#define reg_eth_rw_intr_mask_offset 76 337 338/* Register rw_ack_intr, scope eth, type rw */ 339#define reg_eth_rw_ack_intr___crc___lsb 0 340#define reg_eth_rw_ack_intr___crc___width 1 341#define reg_eth_rw_ack_intr___crc___bit 0 342#define reg_eth_rw_ack_intr___align___lsb 1 343#define reg_eth_rw_ack_intr___align___width 1 344#define reg_eth_rw_ack_intr___align___bit 1 345#define reg_eth_rw_ack_intr___oversize___lsb 2 346#define reg_eth_rw_ack_intr___oversize___width 1 347#define reg_eth_rw_ack_intr___oversize___bit 2 348#define reg_eth_rw_ack_intr___congestion___lsb 3 349#define reg_eth_rw_ack_intr___congestion___width 1 350#define reg_eth_rw_ack_intr___congestion___bit 3 351#define reg_eth_rw_ack_intr___single_col___lsb 4 352#define reg_eth_rw_ack_intr___single_col___width 1 353#define reg_eth_rw_ack_intr___single_col___bit 4 354#define reg_eth_rw_ack_intr___mult_col___lsb 5 355#define reg_eth_rw_ack_intr___mult_col___width 1 356#define reg_eth_rw_ack_intr___mult_col___bit 5 357#define reg_eth_rw_ack_intr___late_col___lsb 6 358#define reg_eth_rw_ack_intr___late_col___width 1 359#define reg_eth_rw_ack_intr___late_col___bit 6 360#define reg_eth_rw_ack_intr___deferred___lsb 7 361#define reg_eth_rw_ack_intr___deferred___width 1 362#define reg_eth_rw_ack_intr___deferred___bit 7 363#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 364#define reg_eth_rw_ack_intr___carrier_loss___width 1 365#define reg_eth_rw_ack_intr___carrier_loss___bit 8 366#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 367#define reg_eth_rw_ack_intr___sqe_test_err___width 1 368#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 369#define reg_eth_rw_ack_intr___orun___lsb 10 370#define reg_eth_rw_ack_intr___orun___width 1 371#define reg_eth_rw_ack_intr___orun___bit 10 372#define reg_eth_rw_ack_intr___urun___lsb 11 373#define reg_eth_rw_ack_intr___urun___width 1 374#define reg_eth_rw_ack_intr___urun___bit 11 375#define reg_eth_rw_ack_intr___excessive_col___lsb 12 376#define reg_eth_rw_ack_intr___excessive_col___width 1 377#define reg_eth_rw_ack_intr___excessive_col___bit 12 378#define reg_eth_rw_ack_intr___mdio___lsb 13 379#define reg_eth_rw_ack_intr___mdio___width 1 380#define reg_eth_rw_ack_intr___mdio___bit 13 381#define reg_eth_rw_ack_intr_offset 80 382 383/* Register r_intr, scope eth, type r */ 384#define reg_eth_r_intr___crc___lsb 0 385#define reg_eth_r_intr___crc___width 1 386#define reg_eth_r_intr___crc___bit 0 387#define reg_eth_r_intr___align___lsb 1 388#define reg_eth_r_intr___align___width 1 389#define reg_eth_r_intr___align___bit 1 390#define reg_eth_r_intr___oversize___lsb 2 391#define reg_eth_r_intr___oversize___width 1 392#define reg_eth_r_intr___oversize___bit 2 393#define reg_eth_r_intr___congestion___lsb 3 394#define reg_eth_r_intr___congestion___width 1 395#define reg_eth_r_intr___congestion___bit 3 396#define reg_eth_r_intr___single_col___lsb 4 397#define reg_eth_r_intr___single_col___width 1 398#define reg_eth_r_intr___single_col___bit 4 399#define reg_eth_r_intr___mult_col___lsb 5 400#define reg_eth_r_intr___mult_col___width 1 401#define reg_eth_r_intr___mult_col___bit 5 402#define reg_eth_r_intr___late_col___lsb 6 403#define reg_eth_r_intr___late_col___width 1 404#define reg_eth_r_intr___late_col___bit 6 405#define reg_eth_r_intr___deferred___lsb 7 406#define reg_eth_r_intr___deferred___width 1 407#define reg_eth_r_intr___deferred___bit 7 408#define reg_eth_r_intr___carrier_loss___lsb 8 409#define reg_eth_r_intr___carrier_loss___width 1 410#define reg_eth_r_intr___carrier_loss___bit 8 411#define reg_eth_r_intr___sqe_test_err___lsb 9 412#define reg_eth_r_intr___sqe_test_err___width 1 413#define reg_eth_r_intr___sqe_test_err___bit 9 414#define reg_eth_r_intr___orun___lsb 10 415#define reg_eth_r_intr___orun___width 1 416#define reg_eth_r_intr___orun___bit 10 417#define reg_eth_r_intr___urun___lsb 11 418#define reg_eth_r_intr___urun___width 1 419#define reg_eth_r_intr___urun___bit 11 420#define reg_eth_r_intr___excessive_col___lsb 12 421#define reg_eth_r_intr___excessive_col___width 1 422#define reg_eth_r_intr___excessive_col___bit 12 423#define reg_eth_r_intr___mdio___lsb 13 424#define reg_eth_r_intr___mdio___width 1 425#define reg_eth_r_intr___mdio___bit 13 426#define reg_eth_r_intr_offset 84 427 428/* Register r_masked_intr, scope eth, type r */ 429#define reg_eth_r_masked_intr___crc___lsb 0 430#define reg_eth_r_masked_intr___crc___width 1 431#define reg_eth_r_masked_intr___crc___bit 0 432#define reg_eth_r_masked_intr___align___lsb 1 433#define reg_eth_r_masked_intr___align___width 1 434#define reg_eth_r_masked_intr___align___bit 1 435#define reg_eth_r_masked_intr___oversize___lsb 2 436#define reg_eth_r_masked_intr___oversize___width 1 437#define reg_eth_r_masked_intr___oversize___bit 2 438#define reg_eth_r_masked_intr___congestion___lsb 3 439#define reg_eth_r_masked_intr___congestion___width 1 440#define reg_eth_r_masked_intr___congestion___bit 3 441#define reg_eth_r_masked_intr___single_col___lsb 4 442#define reg_eth_r_masked_intr___single_col___width 1 443#define reg_eth_r_masked_intr___single_col___bit 4 444#define reg_eth_r_masked_intr___mult_col___lsb 5 445#define reg_eth_r_masked_intr___mult_col___width 1 446#define reg_eth_r_masked_intr___mult_col___bit 5 447#define reg_eth_r_masked_intr___late_col___lsb 6 448#define reg_eth_r_masked_intr___late_col___width 1 449#define reg_eth_r_masked_intr___late_col___bit 6 450#define reg_eth_r_masked_intr___deferred___lsb 7 451#define reg_eth_r_masked_intr___deferred___width 1 452#define reg_eth_r_masked_intr___deferred___bit 7 453#define reg_eth_r_masked_intr___carrier_loss___lsb 8 454#define reg_eth_r_masked_intr___carrier_loss___width 1 455#define reg_eth_r_masked_intr___carrier_loss___bit 8 456#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 457#define reg_eth_r_masked_intr___sqe_test_err___width 1 458#define reg_eth_r_masked_intr___sqe_test_err___bit 9 459#define reg_eth_r_masked_intr___orun___lsb 10 460#define reg_eth_r_masked_intr___orun___width 1 461#define reg_eth_r_masked_intr___orun___bit 10 462#define reg_eth_r_masked_intr___urun___lsb 11 463#define reg_eth_r_masked_intr___urun___width 1 464#define reg_eth_r_masked_intr___urun___bit 11 465#define reg_eth_r_masked_intr___excessive_col___lsb 12 466#define reg_eth_r_masked_intr___excessive_col___width 1 467#define reg_eth_r_masked_intr___excessive_col___bit 12 468#define reg_eth_r_masked_intr___mdio___lsb 13 469#define reg_eth_r_masked_intr___mdio___width 1 470#define reg_eth_r_masked_intr___mdio___bit 13 471#define reg_eth_r_masked_intr_offset 88 472 473 474/* Constants */ 475#define regk_eth_discard 0x00000000 476#define regk_eth_ether 0x00000000 477#define regk_eth_full 0x00000001 478#define regk_eth_half 0x00000000 479#define regk_eth_hsh 0x00000001 480#define regk_eth_mii 0x00000001 481#define regk_eth_mii_clk 0x00000000 482#define regk_eth_mii_rec 0x00000002 483#define regk_eth_no 0x00000000 484#define regk_eth_rec 0x00000001 485#define regk_eth_rw_ga_hi_default 0x00000000 486#define regk_eth_rw_ga_lo_default 0x00000000 487#define regk_eth_rw_gen_ctrl_default 0x00000000 488#define regk_eth_rw_intr_mask_default 0x00000000 489#define regk_eth_rw_ma0_hi_default 0x00000000 490#define regk_eth_rw_ma0_lo_default 0x00000000 491#define regk_eth_rw_ma1_hi_default 0x00000000 492#define regk_eth_rw_ma1_lo_default 0x00000000 493#define regk_eth_rw_mgm_ctrl_default 0x00000000 494#define regk_eth_rw_test_ctrl_default 0x00000000 495#define regk_eth_size1518 0x00000000 496#define regk_eth_size1522 0x00000001 497#define regk_eth_yes 0x00000001 498#endif /* __eth_defs_asm_h */ 499