1/* 2 * Memory MAP 3 * Common header file for blackfin BF561 of processors. 4 */ 5 6#ifndef _MEM_MAP_561_H_ 7#define _MEM_MAP_561_H_ 8 9#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 10#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 11 12/* Async Memory Banks */ 13#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ 14#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ 15#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ 16#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ 17#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ 18#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ 19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ 20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ 21 22/* Level 1 Memory */ 23 24#ifdef CONFIG_BLKFIN_CACHE 25#define BLKFIN_ICACHESIZE (16*1024) 26#else 27#define BLKFIN_ICACHESIZE (0*1024) 28#endif 29 30/* Memory Map for ADSP-BF561 processors */ 31 32#ifdef CONFIG_BF561 33#define L1_CODE_START 0xFFA00000 34#define L1_DATA_A_START 0xFF800000 35#define L1_DATA_B_START 0xFF900000 36 37#define L1_CODE_LENGTH 0x4000 38 39#ifdef CONFIG_BLKFIN_DCACHE 40 41#ifdef CONFIG_BLKFIN_DCACHE_BANKA 42#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 43#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 44#define L1_DATA_B_LENGTH 0x8000 45#define BLKFIN_DCACHESIZE (16*1024) 46#define BLKFIN_DSUPBANKS 1 47#else 48#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 49#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 50#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 51#define BLKFIN_DCACHESIZE (32*1024) 52#define BLKFIN_DSUPBANKS 2 53#endif 54 55#else 56#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 57#define L1_DATA_A_LENGTH 0x8000 58#define L1_DATA_B_LENGTH 0x8000 59#define BLKFIN_DCACHESIZE (0*1024) 60#define BLKFIN_DSUPBANKS 0 61#endif /*CONFIG_BLKFIN_DCACHE*/ 62#endif 63 64/* Level 2 Memory */ 65#define L2_START 0xFEB00000 66#define L2_LENGTH 0x20000 67 68/* Scratch Pad Memory */ 69 70#if defined(CONFIG_BF561) 71#define L1_SCRATCH_START 0xFFB00000 72#define L1_SCRATCH_LENGTH 0x1000 73#endif 74 75#endif /* _MEM_MAP_533_H_ */ 76