1#ifndef __ASMARM_TLBFLUSH_H
2#define __ASMARM_TLBFLUSH_H
3
4/*
5 * TLB flushing:
6 *
7 *  - flush_tlb_all() flushes all processes TLBs
8 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
9 *  - flush_tlb_page(vma, vmaddr) flushes one page
10 *  - flush_tlb_range(vma, start, end) flushes a range of pages
11 */
12
13#define flush_tlb_all()				memc_update_all()
14#define flush_tlb_mm(mm)			memc_update_mm(mm)
15#define flush_tlb_page(vma, vmaddr)		do { printk("flush_tlb_page\n");} while (0)  // IS THIS RIGHT?
16#define flush_tlb_range(vma,start,end)		\
17		do { memc_update_mm(vma->vm_mm); (void)(start); (void)(end); } while (0)
18#define flush_tlb_pgtables(mm,start,end)        do { printk("flush_tlb_pgtables\n");} while (0)
19#define flush_tlb_kernel_range(s,e)             do { printk("flush_tlb_range\n");} while (0)
20
21/*
22 * The following handle the weird MEMC chip
23 */
24static inline void memc_update_all(void)
25{
26	struct task_struct *p;
27	cpu_memc_update_all(init_mm.pgd);
28	for_each_process(p) {
29		if (!p->mm)
30			continue;
31		cpu_memc_update_all(p->mm->pgd);
32	}
33	processor._set_pgd(current->active_mm->pgd);
34}
35
36static inline void memc_update_mm(struct mm_struct *mm)
37{
38	cpu_memc_update_all(mm->pgd);
39
40	if (mm == current->active_mm)
41		processor._set_pgd(mm->pgd);
42}
43
44static inline void
45memc_clear(struct mm_struct *mm, struct page *page)
46{
47	cpu_memc_update_entry(mm->pgd, (unsigned long) page_address(page), 0);
48
49	if (mm == current->active_mm)
50		processor._set_pgd(mm->pgd);
51}
52
53static inline void
54memc_update_addr(struct mm_struct *mm, pte_t pte, unsigned long vaddr)
55{
56	cpu_memc_update_entry(mm->pgd, pte_val(pte), vaddr);
57
58	if (mm == current->active_mm)
59		processor._set_pgd(mm->pgd);
60}
61
62static inline void
63update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
64{
65	struct mm_struct *mm = vma->vm_mm;
66printk("update_mmu_cache\n");
67	memc_update_addr(mm, pte, addr);
68}
69
70#endif
71