1/* linux/include/asm-arm/arch-s3c2410/regs-timer.h 2 * 3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * S3C2410 Timer configuration 11*/ 12 13 14#ifndef __ASM_ARCH_REGS_TIMER_H 15#define __ASM_ARCH_REGS_TIMER_H "$Id: regs-timer.h,v 1.1.1.1 2007/08/03 18:53:17 Exp $" 16 17#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x)) 18#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c)) 19 20#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00) 21#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04) 22#define S3C2410_TCON S3C2410_TIMERREG(0x08) 23 24#define S3C2410_TCFG_PRESCALER0_MASK (255<<0) 25#define S3C2410_TCFG_PRESCALER1_MASK (255<<8) 26#define S3C2410_TCFG_PRESCALER1_SHIFT (8) 27#define S3C2410_TCFG_DEADZONE_MASK (255<<16) 28#define S3C2410_TCFG_DEADZONE_SHIFT (16) 29 30#define S3C2410_TCFG1_MUX4_DIV2 (0<<16) 31#define S3C2410_TCFG1_MUX4_DIV4 (1<<16) 32#define S3C2410_TCFG1_MUX4_DIV8 (2<<16) 33#define S3C2410_TCFG1_MUX4_DIV16 (3<<16) 34#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16) 35#define S3C2410_TCFG1_MUX4_MASK (15<<16) 36#define S3C2410_TCFG1_MUX4_SHIFT (16) 37 38#define S3C2410_TCFG1_MUX3_DIV2 (0<<12) 39#define S3C2410_TCFG1_MUX3_DIV4 (1<<12) 40#define S3C2410_TCFG1_MUX3_DIV8 (2<<12) 41#define S3C2410_TCFG1_MUX3_DIV16 (3<<12) 42#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12) 43#define S3C2410_TCFG1_MUX3_MASK (15<<12) 44 45 46#define S3C2410_TCFG1_MUX2_DIV2 (0<<8) 47#define S3C2410_TCFG1_MUX2_DIV4 (1<<8) 48#define S3C2410_TCFG1_MUX2_DIV8 (2<<8) 49#define S3C2410_TCFG1_MUX2_DIV16 (3<<8) 50#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8) 51#define S3C2410_TCFG1_MUX2_MASK (15<<8) 52 53 54#define S3C2410_TCFG1_MUX1_DIV2 (0<<4) 55#define S3C2410_TCFG1_MUX1_DIV4 (1<<4) 56#define S3C2410_TCFG1_MUX1_DIV8 (2<<4) 57#define S3C2410_TCFG1_MUX1_DIV16 (3<<4) 58#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4) 59#define S3C2410_TCFG1_MUX1_MASK (15<<4) 60 61#define S3C2410_TCFG1_MUX0_DIV2 (0<<0) 62#define S3C2410_TCFG1_MUX0_DIV4 (1<<0) 63#define S3C2410_TCFG1_MUX0_DIV8 (2<<0) 64#define S3C2410_TCFG1_MUX0_DIV16 (3<<0) 65#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) 66#define S3C2410_TCFG1_MUX0_MASK (15<<0) 67 68/* for each timer, we have an count buffer, an compare buffer and 69 * an observation buffer 70*/ 71 72/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ 73 74#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00) 75#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04) 76#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) 77 78#define S3C2410_TCON_T4RELOAD (1<<22) 79#define S3C2410_TCON_T4MANUALUPD (1<<21) 80#define S3C2410_TCON_T4START (1<<20) 81 82#define S3C2410_TCON_T3RELOAD (1<<19) 83#define S3C2410_TCON_T3INVERT (1<<18) 84#define S3C2410_TCON_T3MANUALUPD (1<<17) 85#define S3C2410_TCON_T3START (1<<16) 86 87#define S3C2410_TCON_T2RELOAD (1<<15) 88#define S3C2410_TCON_T2INVERT (1<<14) 89#define S3C2410_TCON_T2MANUALUPD (1<<13) 90#define S3C2410_TCON_T2START (1<<12) 91 92#define S3C2410_TCON_T1RELOAD (1<<11) 93#define S3C2410_TCON_T1INVERT (1<<10) 94#define S3C2410_TCON_T1MANUALUPD (1<<9) 95#define S3C2410_TCON_T1START (1<<8) 96 97#define S3C2410_TCON_T0DEADZONE (1<<4) 98#define S3C2410_TCON_T0RELOAD (1<<3) 99#define S3C2410_TCON_T0INVERT (1<<2) 100#define S3C2410_TCON_T0MANUALUPD (1<<1) 101#define S3C2410_TCON_T0START (1<<0) 102 103#endif /* __ASM_ARCH_REGS_TIMER_H */ 104