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  • only in /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-arm/arch-realview/
1/*
2 * linux/include/asm-arm/arch-realview/platform.h
3 *
4 * Copyright (c) ARM Limited 2003.  All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 */
20
21#ifndef __address_h
22#define __address_h                     1
23
24/*
25 * Memory definitions
26 */
27#define REALVIEW_BOOT_ROM_LO          0x30000000		/* DoC Base (64Mb)...*/
28#define REALVIEW_BOOT_ROM_HI          0x30000000
29#define REALVIEW_BOOT_ROM_BASE        REALVIEW_BOOT_ROM_HI	 /*  Normal position */
30#define REALVIEW_BOOT_ROM_SIZE        SZ_64M
31
32#define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
33#define REALVIEW_SSRAM_SIZE           SZ_2M
34
35#define REALVIEW_FLASH_BASE           0x40000000
36#define REALVIEW_FLASH_SIZE           SZ_64M
37
38/*
39 *  SDRAM
40 */
41#define REALVIEW_SDRAM_BASE           0x00000000
42
43/*
44 *  Logic expansion modules
45 *
46 */
47
48
49/* ------------------------------------------------------------------------
50 *  RealView Registers
51 * ------------------------------------------------------------------------
52 *
53 */
54#define REALVIEW_SYS_ID_OFFSET               0x00
55#define REALVIEW_SYS_SW_OFFSET               0x04
56#define REALVIEW_SYS_LED_OFFSET              0x08
57#define REALVIEW_SYS_OSC0_OFFSET             0x0C
58
59#define REALVIEW_SYS_OSC1_OFFSET             0x10
60#define REALVIEW_SYS_OSC2_OFFSET             0x14
61#define REALVIEW_SYS_OSC3_OFFSET             0x18
62#define REALVIEW_SYS_OSC4_OFFSET             0x1C	/* OSC1 for RealView/AB */
63
64#define REALVIEW_SYS_LOCK_OFFSET             0x20
65#define REALVIEW_SYS_100HZ_OFFSET            0x24
66#define REALVIEW_SYS_CFGDATA1_OFFSET         0x28
67#define REALVIEW_SYS_CFGDATA2_OFFSET         0x2C
68#define REALVIEW_SYS_FLAGS_OFFSET            0x30
69#define REALVIEW_SYS_FLAGSSET_OFFSET         0x30
70#define REALVIEW_SYS_FLAGSCLR_OFFSET         0x34
71#define REALVIEW_SYS_NVFLAGS_OFFSET          0x38
72#define REALVIEW_SYS_NVFLAGSSET_OFFSET       0x38
73#define REALVIEW_SYS_NVFLAGSCLR_OFFSET       0x3C
74#define REALVIEW_SYS_RESETCTL_OFFSET         0x40
75#define REALVIEW_SYS_PCICTL_OFFSET           0x44
76#define REALVIEW_SYS_MCI_OFFSET              0x48
77#define REALVIEW_SYS_FLASH_OFFSET            0x4C
78#define REALVIEW_SYS_CLCD_OFFSET             0x50
79#define REALVIEW_SYS_CLCDSER_OFFSET          0x54
80#define REALVIEW_SYS_BOOTCS_OFFSET           0x58
81#define REALVIEW_SYS_24MHz_OFFSET            0x5C
82#define REALVIEW_SYS_MISC_OFFSET             0x60
83#define REALVIEW_SYS_IOSEL_OFFSET            0x70
84#define REALVIEW_SYS_TEST_OSC0_OFFSET        0x80
85#define REALVIEW_SYS_TEST_OSC1_OFFSET        0x84
86#define REALVIEW_SYS_TEST_OSC2_OFFSET        0x88
87#define REALVIEW_SYS_TEST_OSC3_OFFSET        0x8C
88#define REALVIEW_SYS_TEST_OSC4_OFFSET        0x90
89
90#define REALVIEW_SYS_BASE                    0x10000000
91#define REALVIEW_SYS_ID                      (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
92#define REALVIEW_SYS_SW                      (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
93#define REALVIEW_SYS_LED                     (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
94#define REALVIEW_SYS_OSC0                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
95#define REALVIEW_SYS_OSC1                    (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
96
97#define REALVIEW_SYS_LOCK                    (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
98#define REALVIEW_SYS_100HZ                   (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
99#define REALVIEW_SYS_CFGDATA1                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
100#define REALVIEW_SYS_CFGDATA2                (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
101#define REALVIEW_SYS_FLAGS                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
102#define REALVIEW_SYS_FLAGSSET                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
103#define REALVIEW_SYS_FLAGSCLR                (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
104#define REALVIEW_SYS_NVFLAGS                 (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
105#define REALVIEW_SYS_NVFLAGSSET              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
106#define REALVIEW_SYS_NVFLAGSCLR              (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
107#define REALVIEW_SYS_RESETCTL                (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
108#define REALVIEW_SYS_PCICTL                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
109#define REALVIEW_SYS_MCI                     (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
110#define REALVIEW_SYS_FLASH                   (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
111#define REALVIEW_SYS_CLCD                    (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
112#define REALVIEW_SYS_CLCDSER                 (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
113#define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
114#define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
115#define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
116#define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
117#define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
118#define REALVIEW_SYS_TEST_OSC1               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
119#define REALVIEW_SYS_TEST_OSC2               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
120#define REALVIEW_SYS_TEST_OSC3               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
121#define REALVIEW_SYS_TEST_OSC4               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
122
123/*
124 * Values for REALVIEW_SYS_RESET_CTRL
125 */
126#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR    0x01
127#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT   0x02
128#define REALVIEW_SYS_CTRL_RESET_DLLRESET     0x03
129#define REALVIEW_SYS_CTRL_RESET_PLLRESET     0x04
130#define REALVIEW_SYS_CTRL_RESET_POR          0x05
131#define REALVIEW_SYS_CTRL_RESET_DoC          0x06
132
133#define REALVIEW_SYS_CTRL_LED         (1 << 0)
134
135
136/* ------------------------------------------------------------------------
137 *  RealView control registers
138 * ------------------------------------------------------------------------
139 */
140
141/*
142 * REALVIEW_IDFIELD
143 *
144 * 31:24 = manufacturer (0x41 = ARM)
145 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
146 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
147 * 11:4  = build value
148 * 3:0   = revision number (0x1 = rev B (AHB))
149 */
150
151/*
152 * REALVIEW_SYS_LOCK
153 *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
154 *     SYS_CLD, SYS_BOOTCS
155 */
156#define REALVIEW_SYS_LOCK_LOCKED    (1 << 16)
157#define REALVIEW_SYS_LOCKVAL_MASK	0xFFFF		/* write 0xA05F to enable write access */
158
159/*
160 * REALVIEW_SYS_FLASH
161 */
162#define REALVIEW_FLASHPROG_FLVPPEN	(1 << 0)	/* Enable writing to flash */
163
164/*
165 * REALVIEW_INTREG
166 *     - used to acknowledge and control MMCI and UART interrupts
167 */
168#define REALVIEW_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
169#define REALVIEW_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
170#define REALVIEW_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
171                                                /* write 1 to acknowledge and clear               */
172#define REALVIEW_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
173#define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
174
175/*
176 * REALVIEW peripheral addresses
177 */
178#define REALVIEW_SCTL_BASE            0x10001000	/* System controller */
179#define REALVIEW_I2C_BASE             0x10002000	/* I2C control */
180	/* Reserved 0x10003000 */
181#define REALVIEW_AACI_BASE            0x10004000	/* Audio */
182#define REALVIEW_MMCI0_BASE           0x10005000	/* MMC interface */
183#define REALVIEW_KMI0_BASE            0x10006000	/* KMI interface */
184#define REALVIEW_KMI1_BASE            0x10007000	/* KMI 2nd interface */
185#define REALVIEW_CHAR_LCD_BASE        0x10008000	/* Character LCD */
186#define REALVIEW_UART0_BASE           0x10009000	/* UART 0 */
187#define REALVIEW_UART1_BASE           0x1000A000	/* UART 1 */
188#define REALVIEW_UART2_BASE           0x1000B000	/* UART 2 */
189#define REALVIEW_UART3_BASE           0x1000C000	/* UART 3 */
190#define REALVIEW_SSP_BASE             0x1000D000	/* Synchronous Serial Port */
191#define REALVIEW_SCI_BASE             0x1000E000	/* Smart card controller */
192	/* Reserved 0x1000F000 */
193#define REALVIEW_WATCHDOG_BASE        0x10010000	/* watchdog interface */
194#define REALVIEW_TIMER0_1_BASE        0x10011000	/* Timer 0 and 1 */
195#define REALVIEW_TIMER2_3_BASE        0x10012000	/* Timer 2 and 3 */
196#define REALVIEW_GPIO0_BASE           0x10013000	/* GPIO port 0 */
197#define REALVIEW_GPIO1_BASE           0x10014000	/* GPIO port 1 */
198#define REALVIEW_GPIO2_BASE           0x10015000	/* GPIO port 2 */
199	/* Reserved 0x10016000 */
200#define REALVIEW_RTC_BASE             0x10017000	/* Real Time Clock */
201#define REALVIEW_DMC_BASE             0x10018000	/* DMC configuration */
202#define REALVIEW_PCI_CORE_BASE        0x10019000	/* PCI configuration */
203	/* Reserved 0x1001A000 - 0x1001FFFF */
204#define REALVIEW_CLCD_BASE            0x10020000	/* CLCD */
205#define REALVIEW_DMAC_BASE            0x10030000	/* DMA controller */
206#ifndef CONFIG_REALVIEW_MPCORE
207#define REALVIEW_GIC_CPU_BASE         0x10040000	/* Generic interrupt controller CPU interface */
208#define REALVIEW_GIC_DIST_BASE        0x10041000	/* Generic interrupt controller distributor */
209#else
210#ifdef CONFIG_REALVIEW_MPCORE_REVB
211#define REALVIEW_MPCORE_SCU_BASE	0x10100000	/*  SCU registers */
212#define REALVIEW_GIC_CPU_BASE		0x10100100	/* Generic interrupt controller CPU interface */
213#define REALVIEW_TWD_BASE		0x10100700
214#define REALVIEW_TWD_SIZE		0x00000100
215#define REALVIEW_GIC_DIST_BASE		0x10101000	/* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE	0x10102000	/* L220 registers */
217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8		/*  Register offset for MPCore sysctl */
218#else
219#define REALVIEW_MPCORE_SCU_BASE      0x1F000000	/*  SCU registers */
220#define REALVIEW_GIC_CPU_BASE         0x1F000100	/* Generic interrupt controller CPU interface */
221#define REALVIEW_TWD_BASE             0x1F000700
222#define REALVIEW_TWD_SIZE             0x00000100
223#define REALVIEW_GIC_DIST_BASE        0x1F001000	/* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE     0x1F002000	/* L220 registers */
225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74		/*  Register offset for MPCore sysctl */
226#endif
227#define REALVIEW_GIC1_CPU_BASE        0x10040000	/* Generic interrupt controller CPU interface */
228#define REALVIEW_GIC1_DIST_BASE       0x10041000	/* Generic interrupt controller distributor */
229#endif
230#define REALVIEW_SMC_BASE             0x10080000	/* SMC */
231	/* Reserved 0x10090000 - 0x100EFFFF */
232
233#define REALVIEW_ETH_BASE             0x4E000000	/* Ethernet */
234
235/* PCI space */
236#define REALVIEW_PCI_BASE             0x41000000	/* PCI Interface */
237#define REALVIEW_PCI_CFG_BASE	      0x42000000
238#define REALVIEW_PCI_MEM_BASE0        0x44000000
239#define REALVIEW_PCI_MEM_BASE1        0x50000000
240#define REALVIEW_PCI_MEM_BASE2        0x60000000
241/* Sizes of above maps */
242#define REALVIEW_PCI_BASE_SIZE	       0x01000000
243#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
244#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000	/* 32Mb */
245#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000	/* 256Mb */
246#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000	/* 256Mb */
247
248#define REALVIEW_SDRAM67_BASE         0x70000000	/* SDRAM banks 6 and 7 */
249#define REALVIEW_LT_BASE              0x80000000	/* Logic Tile expansion */
250
251/*
252 * Disk on Chip
253 */
254#define REALVIEW_DOC_BASE             0x2C000000
255#define REALVIEW_DOC_SIZE             (16 << 20)
256#define REALVIEW_DOC_PAGE_SIZE        512
257#define REALVIEW_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
258
259#define ERASE_UNIT_PAGES    32
260#define START_PAGE          0x80
261
262/*
263 *  LED settings, bits [7:0]
264 */
265#define REALVIEW_SYS_LED0             (1 << 0)
266#define REALVIEW_SYS_LED1             (1 << 1)
267#define REALVIEW_SYS_LED2             (1 << 2)
268#define REALVIEW_SYS_LED3             (1 << 3)
269#define REALVIEW_SYS_LED4             (1 << 4)
270#define REALVIEW_SYS_LED5             (1 << 5)
271#define REALVIEW_SYS_LED6             (1 << 6)
272#define REALVIEW_SYS_LED7             (1 << 7)
273
274#define ALL_LEDS                  0xFF
275
276#define LED_BANK                  REALVIEW_SYS_LED
277
278/*
279 * Control registers
280 */
281#define REALVIEW_IDFIELD_OFFSET	0x0	/* RealView build information */
282#define REALVIEW_FLASHPROG_OFFSET	0x4	/* Flash devices */
283#define REALVIEW_INTREG_OFFSET		0x8	/* Interrupt control */
284#define REALVIEW_DECODE_OFFSET		0xC	/* Fitted logic modules */
285
286/* ------------------------------------------------------------------------
287 *  Interrupts - bit assignment (primary)
288 * ------------------------------------------------------------------------
289 */
290#ifndef CONFIG_REALVIEW_MPCORE
291#define INT_WDOGINT			0	/* Watchdog timer */
292#define INT_SOFTINT			1	/* Software interrupt */
293#define INT_COMMRx			2	/* Debug Comm Rx interrupt */
294#define INT_COMMTx			3	/* Debug Comm Tx interrupt */
295#define INT_TIMERINT0_1			4	/* Timer 0 and 1 */
296#define INT_TIMERINT2_3			5	/* Timer 2 and 3 */
297#define INT_GPIOINT0			6	/* GPIO 0 */
298#define INT_GPIOINT1			7	/* GPIO 1 */
299#define INT_GPIOINT2			8	/* GPIO 2 */
300/* 9 reserved */
301#define INT_RTCINT			10	/* Real Time Clock */
302#define INT_SSPINT			11	/* Synchronous Serial Port */
303#define INT_UARTINT0			12	/* UART 0 on development chip */
304#define INT_UARTINT1			13	/* UART 1 on development chip */
305#define INT_UARTINT2			14	/* UART 2 on development chip */
306#define INT_UARTINT3			15	/* UART 3 on development chip */
307#define INT_SCIINT			16	/* Smart Card Interface */
308#define INT_MMCI0A			17	/* Multimedia Card 0A */
309#define INT_MMCI0B			18	/* Multimedia Card 0B */
310#define INT_AACI			19	/* Audio Codec */
311#define INT_KMI0			20	/* Keyboard/Mouse port 0 */
312#define INT_KMI1			21	/* Keyboard/Mouse port 1 */
313#define INT_CHARLCD			22	/* Character LCD */
314#define INT_CLCDINT			23	/* CLCD controller */
315#define INT_DMAINT			24	/* DMA controller */
316#define INT_PWRFAILINT			25	/* Power failure */
317#define INT_PISMO			26
318#define INT_DoC				27	/* Disk on Chip memory controller */
319#define INT_ETH				28	/* Ethernet controller */
320#define INT_USB				29	/* USB controller */
321#define INT_TSPENINT			30	/* Touchscreen pen */
322#define INT_TSKPADINT			31	/* Touchscreen keypad */
323
324#else
325
326#define MAX_GIC_NR			2
327
328#define INT_AACI			0
329#define INT_TIMERINT0_1			1
330#define INT_TIMERINT2_3			2
331#define INT_USB				3
332#define INT_UARTINT0			4
333#define INT_UARTINT1			5
334#define INT_RTCINT			6
335#define INT_KMI0			7
336#define INT_KMI1			8
337#define INT_ETH				9
338#define INT_EB_IRQ1			10	/* main GIC */
339#define INT_EB_IRQ2			11	/* tile GIC */
340#define INT_EB_FIQ1			12	/* main GIC */
341#define INT_EB_FIQ2			13	/* tile GIC */
342#define INT_MMCI0A			14
343#define INT_MMCI0B			15
344
345#define INT_PMU_CPU0			17
346#define INT_PMU_CPU1			18
347#define INT_PMU_CPU2			19
348#define INT_PMU_CPU3			20
349#define INT_PMU_SCU0			21
350#define INT_PMU_SCU1			22
351#define INT_PMU_SCU2			23
352#define INT_PMU_SCU3			24
353#define INT_PMU_SCU4			25
354#define INT_PMU_SCU5			26
355#define INT_PMU_SCU6			27
356#define INT_PMU_SCU7			28
357
358#define INT_L220_EVENT			29
359#define INT_L220_SLAVE			30
360#define INT_L220_DECODE			31
361
362#define INT_UARTINT2			-1
363#define INT_UARTINT3			-1
364#define INT_CLCDINT			-1
365#define INT_DMAINT			-1
366#define INT_WDOGINT			-1
367#define INT_GPIOINT0			-1
368#define INT_GPIOINT1			-1
369#define INT_GPIOINT2			-1
370#define INT_SCIINT			-1
371#define INT_SSPINT			-1
372#endif
373
374/*
375 *  Interrupt bit positions
376 *
377 */
378#define INTMASK_WDOGINT			(1 << INT_WDOGINT)
379#define INTMASK_SOFTINT			(1 << INT_SOFTINT)
380#define INTMASK_COMMRx			(1 << INT_COMMRx)
381#define INTMASK_COMMTx			(1 << INT_COMMTx)
382#define INTMASK_TIMERINT0_1		(1 << INT_TIMERINT0_1)
383#define INTMASK_TIMERINT2_3		(1 << INT_TIMERINT2_3)
384#define INTMASK_GPIOINT0		(1 << INT_GPIOINT0)
385#define INTMASK_GPIOINT1		(1 << INT_GPIOINT1)
386#define INTMASK_GPIOINT2		(1 << INT_GPIOINT2)
387#define INTMASK_RTCINT			(1 << INT_RTCINT)
388#define INTMASK_SSPINT			(1 << INT_SSPINT)
389#define INTMASK_UARTINT0		(1 << INT_UARTINT0)
390#define INTMASK_UARTINT1		(1 << INT_UARTINT1)
391#define INTMASK_UARTINT2		(1 << INT_UARTINT2)
392#define INTMASK_UARTINT3		(1 << INT_UARTINT3)
393#define INTMASK_SCIINT			(1 << INT_SCIINT)
394#define INTMASK_MMCI0A			(1 << INT_MMCI0A)
395#define INTMASK_MMCI0B			(1 << INT_MMCI0B)
396#define INTMASK_AACI			(1 << INT_AACI)
397#define INTMASK_KMI0			(1 << INT_KMI0)
398#define INTMASK_KMI1			(1 << INT_KMI1)
399#define INTMASK_CHARLCD			(1 << INT_CHARLCD)
400#define INTMASK_CLCDINT			(1 << INT_CLCDINT)
401#define INTMASK_DMAINT			(1 << INT_DMAINT)
402#define INTMASK_PWRFAILINT		(1 << INT_PWRFAILINT)
403#define INTMASK_PISMO			(1 << INT_PISMO)
404#define INTMASK_DoC			(1 << INT_DoC)
405#define INTMASK_ETH			(1 << INT_ETH)
406#define INTMASK_USB			(1 << INT_USB)
407#define INTMASK_TSPENINT		(1 << INT_TSPENINT)
408#define INTMASK_TSKPADINT		(1 << INT_TSKPADINT)
409
410#define MAXIRQNUM                       31
411#define MAXFIQNUM                       31
412#define MAXSWINUM                       31
413
414/*
415 *  Application Flash
416 *
417 */
418#define FLASH_BASE                      REALVIEW_FLASH_BASE
419#define FLASH_SIZE                      REALVIEW_FLASH_SIZE
420#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
421#define FLASH_BLOCK_SIZE                SZ_128K
422
423/*
424 *  Boot Flash
425 *
426 */
427#define EPROM_BASE                      REALVIEW_BOOT_ROM_HI
428#define EPROM_SIZE                      REALVIEW_BOOT_ROM_SIZE
429#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
430
431/*
432 *  Clean base - dummy
433 *
434 */
435#define CLEAN_BASE                      EPROM_BASE
436
437/*
438 * System controller bit assignment
439 */
440#define REALVIEW_REFCLK	0
441#define REALVIEW_TIMCLK	1
442
443#define REALVIEW_TIMER1_EnSel	15
444#define REALVIEW_TIMER2_EnSel	17
445#define REALVIEW_TIMER3_EnSel	19
446#define REALVIEW_TIMER4_EnSel	21
447
448
449#define MAX_TIMER                       2
450#define MAX_PERIOD                      699050
451#define TICKS_PER_uSEC                  1
452
453/*
454 *  These are useconds NOT ticks.
455 *
456 */
457#define mSEC_1                          1000
458#define mSEC_5                          (mSEC_1 * 5)
459#define mSEC_10                         (mSEC_1 * 10)
460#define mSEC_25                         (mSEC_1 * 25)
461#define SEC_1                           (mSEC_1 * 1000)
462
463#define REALVIEW_CSR_BASE             0x10000000
464#define REALVIEW_CSR_SIZE             0x10000000
465
466#endif
467
468/* 	END */
469