1/* 2 * w1_io.c 3 * 4 * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru> 5 * 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22#include <asm/io.h> 23 24#include <linux/delay.h> 25#include <linux/moduleparam.h> 26#include <linux/module.h> 27 28#include "w1.h" 29#include "w1_log.h" 30 31static int w1_delay_parm = 1; 32module_param_named(delay_coef, w1_delay_parm, int, 0); 33 34static u8 w1_crc8_table[] = { 35 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65, 36 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220, 37 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98, 38 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255, 39 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7, 40 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154, 41 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36, 42 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185, 43 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205, 44 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80, 45 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238, 46 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115, 47 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139, 48 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22, 49 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168, 50 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53 51}; 52 53static void w1_delay(unsigned long tm) 54{ 55 udelay(tm * w1_delay_parm); 56} 57 58static void w1_write_bit(struct w1_master *dev, int bit); 59static u8 w1_read_bit(struct w1_master *dev); 60 61/** 62 * Generates a write-0 or write-1 cycle and samples the level. 63 */ 64static u8 w1_touch_bit(struct w1_master *dev, int bit) 65{ 66 if (dev->bus_master->touch_bit) 67 return dev->bus_master->touch_bit(dev->bus_master->data, bit); 68 else if (bit) 69 return w1_read_bit(dev); 70 else { 71 w1_write_bit(dev, 0); 72 return(0); 73 } 74} 75 76/** 77 * Generates a write-0 or write-1 cycle. 78 * Only call if dev->bus_master->touch_bit is NULL 79 */ 80static void w1_write_bit(struct w1_master *dev, int bit) 81{ 82 if (bit) { 83 dev->bus_master->write_bit(dev->bus_master->data, 0); 84 w1_delay(6); 85 dev->bus_master->write_bit(dev->bus_master->data, 1); 86 w1_delay(64); 87 } else { 88 dev->bus_master->write_bit(dev->bus_master->data, 0); 89 w1_delay(60); 90 dev->bus_master->write_bit(dev->bus_master->data, 1); 91 w1_delay(10); 92 } 93} 94 95/** 96 * Writes 8 bits. 97 * 98 * @param dev the master device 99 * @param byte the byte to write 100 */ 101void w1_write_8(struct w1_master *dev, u8 byte) 102{ 103 int i; 104 105 if (dev->bus_master->write_byte) 106 dev->bus_master->write_byte(dev->bus_master->data, byte); 107 else 108 for (i = 0; i < 8; ++i) 109 w1_touch_bit(dev, (byte >> i) & 0x1); 110} 111EXPORT_SYMBOL_GPL(w1_write_8); 112 113 114/** 115 * Generates a write-1 cycle and samples the level. 116 * Only call if dev->bus_master->touch_bit is NULL 117 */ 118static u8 w1_read_bit(struct w1_master *dev) 119{ 120 int result; 121 122 dev->bus_master->write_bit(dev->bus_master->data, 0); 123 w1_delay(6); 124 dev->bus_master->write_bit(dev->bus_master->data, 1); 125 w1_delay(9); 126 127 result = dev->bus_master->read_bit(dev->bus_master->data); 128 w1_delay(55); 129 130 return result & 0x1; 131} 132 133/** 134 * Does a triplet - used for searching ROM addresses. 135 * Return bits: 136 * bit 0 = id_bit 137 * bit 1 = comp_bit 138 * bit 2 = dir_taken 139 * If both bits 0 & 1 are set, the search should be restarted. 140 * 141 * @param dev the master device 142 * @param bdir the bit to write if both id_bit and comp_bit are 0 143 * @return bit fields - see above 144 */ 145u8 w1_triplet(struct w1_master *dev, int bdir) 146{ 147 if ( dev->bus_master->triplet ) 148 return(dev->bus_master->triplet(dev->bus_master->data, bdir)); 149 else { 150 u8 id_bit = w1_touch_bit(dev, 1); 151 u8 comp_bit = w1_touch_bit(dev, 1); 152 u8 retval; 153 154 if ( id_bit && comp_bit ) 155 return(0x03); /* error */ 156 157 if ( !id_bit && !comp_bit ) { 158 /* Both bits are valid, take the direction given */ 159 retval = bdir ? 0x04 : 0; 160 } else { 161 /* Only one bit is valid, take that direction */ 162 bdir = id_bit; 163 retval = id_bit ? 0x05 : 0x02; 164 } 165 166 if ( dev->bus_master->touch_bit ) 167 w1_touch_bit(dev, bdir); 168 else 169 w1_write_bit(dev, bdir); 170 return(retval); 171 } 172} 173 174/** 175 * Reads 8 bits. 176 * 177 * @param dev the master device 178 * @return the byte read 179 */ 180static u8 w1_read_8(struct w1_master * dev) 181{ 182 int i; 183 u8 res = 0; 184 185 if (dev->bus_master->read_byte) 186 res = dev->bus_master->read_byte(dev->bus_master->data); 187 else 188 for (i = 0; i < 8; ++i) 189 res |= (w1_touch_bit(dev,1) << i); 190 191 return res; 192} 193 194/** 195 * Writes a series of bytes. 196 * 197 * @param dev the master device 198 * @param buf pointer to the data to write 199 * @param len the number of bytes to write 200 * @return the byte read 201 */ 202void w1_write_block(struct w1_master *dev, const u8 *buf, int len) 203{ 204 int i; 205 206 if (dev->bus_master->write_block) 207 dev->bus_master->write_block(dev->bus_master->data, buf, len); 208 else 209 for (i = 0; i < len; ++i) 210 w1_write_8(dev, buf[i]); 211} 212EXPORT_SYMBOL_GPL(w1_write_block); 213 214/** 215 * Reads a series of bytes. 216 * 217 * @param dev the master device 218 * @param buf pointer to the buffer to fill 219 * @param len the number of bytes to read 220 * @return the number of bytes read 221 */ 222u8 w1_read_block(struct w1_master *dev, u8 *buf, int len) 223{ 224 int i; 225 u8 ret; 226 227 if (dev->bus_master->read_block) 228 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len); 229 else { 230 for (i = 0; i < len; ++i) 231 buf[i] = w1_read_8(dev); 232 ret = len; 233 } 234 235 return ret; 236} 237EXPORT_SYMBOL_GPL(w1_read_block); 238 239/** 240 * Issues a reset bus sequence. 241 * 242 * @param dev The bus master pointer 243 * @return 0=Device present, 1=No device present or error 244 */ 245int w1_reset_bus(struct w1_master *dev) 246{ 247 int result; 248 249 if (dev->bus_master->reset_bus) 250 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1; 251 else { 252 dev->bus_master->write_bit(dev->bus_master->data, 0); 253 w1_delay(480); 254 dev->bus_master->write_bit(dev->bus_master->data, 1); 255 w1_delay(70); 256 257 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1; 258 w1_delay(410); 259 } 260 261 return result; 262} 263EXPORT_SYMBOL_GPL(w1_reset_bus); 264 265u8 w1_calc_crc8(u8 * data, int len) 266{ 267 u8 crc = 0; 268 269 while (len--) 270 crc = w1_crc8_table[crc ^ *data++]; 271 272 return crc; 273} 274EXPORT_SYMBOL_GPL(w1_calc_crc8); 275 276void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb) 277{ 278 dev->attempts++; 279 if (dev->bus_master->search) 280 dev->bus_master->search(dev->bus_master->data, search_type, cb); 281 else 282 w1_search(dev, search_type, cb); 283} 284 285/** 286 * Resets the bus and then selects the slave by sending either a skip rom 287 * or a rom match. 288 * The w1 master lock must be held. 289 * 290 * @param sl the slave to select 291 * @return 0=success, anything else=error 292 */ 293int w1_reset_select_slave(struct w1_slave *sl) 294{ 295 if (w1_reset_bus(sl->master)) 296 return -1; 297 298 if (sl->master->slave_count == 1) 299 w1_write_8(sl->master, W1_SKIP_ROM); 300 else { 301 u8 match[9] = {W1_MATCH_ROM, }; 302 memcpy(&match[1], (u8 *)&sl->reg_num, 8); 303 w1_write_block(sl->master, match, 9); 304 } 305 return 0; 306} 307EXPORT_SYMBOL_GPL(w1_reset_select_slave); 308