1/* 2 * linux/drivers/video/acornfb.h 3 * 4 * Copyright (C) 1998,1999 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Frame buffer code for Acorn platforms 11 */ 12#if defined(HAS_VIDC20) 13#include <asm/hardware/iomd.h> 14#define VIDC_PALETTE_SIZE 256 15#define VIDC_NAME "VIDC20" 16#elif defined(HAS_VIDC) 17#include <asm/hardware/memc.h> 18#define VIDC_PALETTE_SIZE 16 19#define VIDC_NAME "VIDC" 20#endif 21 22#define EXTEND8(x) ((x)|(x)<<8) 23#define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12) 24 25struct vidc20_palette { 26 u_int red:8; 27 u_int green:8; 28 u_int blue:8; 29 u_int ext:4; 30 u_int unused:4; 31}; 32 33struct vidc_palette { 34 u_int red:4; 35 u_int green:4; 36 u_int blue:4; 37 u_int trans:1; 38 u_int sbz1:13; 39 u_int reg:4; 40 u_int sbz2:2; 41}; 42 43union palette { 44 struct vidc20_palette vidc20; 45 struct vidc_palette vidc; 46 u_int p; 47}; 48 49struct acornfb_par { 50 struct device *dev; 51 unsigned long screen_end; 52 unsigned int dram_size; 53 unsigned int vram_half_sam; 54 unsigned int palette_size; 55 signed int montype; 56 unsigned int using_vram : 1; 57 unsigned int dpms : 1; 58 59 union palette palette[VIDC_PALETTE_SIZE]; 60 61 u32 pseudo_palette[16]; 62}; 63 64struct vidc_timing { 65 u_int h_cycle; 66 u_int h_sync_width; 67 u_int h_border_start; 68 u_int h_display_start; 69 u_int h_display_end; 70 u_int h_border_end; 71 u_int h_interlace; 72 73 u_int v_cycle; 74 u_int v_sync_width; 75 u_int v_border_start; 76 u_int v_display_start; 77 u_int v_display_end; 78 u_int v_border_end; 79 80 u_int control; 81 82 /* VIDC20 only */ 83 u_int pll_ctl; 84}; 85 86struct modey_params { 87 u_int y_res; 88 u_int u_margin; 89 u_int b_margin; 90 u_int vsync_len; 91 u_int vf; 92}; 93 94struct modex_params { 95 u_int x_res; 96 u_int l_margin; 97 u_int r_margin; 98 u_int hsync_len; 99 u_int clock; 100 u_int hf; 101 const struct modey_params *modey; 102}; 103 104#ifdef HAS_VIDC 105 106#define VID_CTL_VS_NVSYNC (1 << 3) 107#define VID_CTL_HS_NHSYNC (1 << 2) 108#define VID_CTL_24MHz (0) 109#define VID_CTL_25MHz (1) 110#define VID_CTL_36MHz (2) 111 112#define VIDC_CTRL_CSYNC (1 << 7) 113#define VIDC_CTRL_INTERLACE (1 << 6) 114#define VIDC_CTRL_FIFO_0_4 (0 << 4) 115#define VIDC_CTRL_FIFO_1_5 (1 << 4) 116#define VIDC_CTRL_FIFO_2_6 (2 << 4) 117#define VIDC_CTRL_FIFO_3_7 (3 << 4) 118#define VIDC_CTRL_1BPP (0 << 2) 119#define VIDC_CTRL_2BPP (1 << 2) 120#define VIDC_CTRL_4BPP (2 << 2) 121#define VIDC_CTRL_8BPP (3 << 2) 122#define VIDC_CTRL_DIV3 (0 << 0) 123#define VIDC_CTRL_DIV2 (1 << 0) 124#define VIDC_CTRL_DIV1_5 (2 << 0) 125#define VIDC_CTRL_DIV1 (3 << 0) 126 127#endif 128 129#ifdef HAS_VIDC20 130/* 131 * VIDC20 registers 132 */ 133#define VIDC20_CTRL 0xe0000000 134#define VIDC20_CTRL_PIX_VCLK (0 << 0) 135#define VIDC20_CTRL_PIX_HCLK (1 << 0) 136#define VIDC20_CTRL_PIX_RCLK (2 << 0) 137#define VIDC20_CTRL_PIX_CK (0 << 2) 138#define VIDC20_CTRL_PIX_CK2 (1 << 2) 139#define VIDC20_CTRL_PIX_CK3 (2 << 2) 140#define VIDC20_CTRL_PIX_CK4 (3 << 2) 141#define VIDC20_CTRL_PIX_CK5 (4 << 2) 142#define VIDC20_CTRL_PIX_CK6 (5 << 2) 143#define VIDC20_CTRL_PIX_CK7 (6 << 2) 144#define VIDC20_CTRL_PIX_CK8 (7 << 2) 145#define VIDC20_CTRL_1BPP (0 << 5) 146#define VIDC20_CTRL_2BPP (1 << 5) 147#define VIDC20_CTRL_4BPP (2 << 5) 148#define VIDC20_CTRL_8BPP (3 << 5) 149#define VIDC20_CTRL_16BPP (4 << 5) 150#define VIDC20_CTRL_32BPP (6 << 5) 151#define VIDC20_CTRL_FIFO_NS (0 << 8) 152#define VIDC20_CTRL_FIFO_4 (1 << 8) 153#define VIDC20_CTRL_FIFO_8 (2 << 8) 154#define VIDC20_CTRL_FIFO_12 (3 << 8) 155#define VIDC20_CTRL_FIFO_16 (4 << 8) 156#define VIDC20_CTRL_FIFO_20 (5 << 8) 157#define VIDC20_CTRL_FIFO_24 (6 << 8) 158#define VIDC20_CTRL_FIFO_28 (7 << 8) 159#define VIDC20_CTRL_INT (1 << 12) 160#define VIDC20_CTRL_DUP (1 << 13) 161#define VIDC20_CTRL_PDOWN (1 << 14) 162 163#define VIDC20_ECTL 0xc0000000 164#define VIDC20_ECTL_REG(x) ((x) & 0xf3) 165#define VIDC20_ECTL_ECK (1 << 2) 166#define VIDC20_ECTL_REDPED (1 << 8) 167#define VIDC20_ECTL_GREENPED (1 << 9) 168#define VIDC20_ECTL_BLUEPED (1 << 10) 169#define VIDC20_ECTL_DAC (1 << 12) 170#define VIDC20_ECTL_LCDGS (1 << 13) 171#define VIDC20_ECTL_HRM (1 << 14) 172 173#define VIDC20_ECTL_HS_MASK (3 << 16) 174#define VIDC20_ECTL_HS_HSYNC (0 << 16) 175#define VIDC20_ECTL_HS_NHSYNC (1 << 16) 176#define VIDC20_ECTL_HS_CSYNC (2 << 16) 177#define VIDC20_ECTL_HS_NCSYNC (3 << 16) 178 179#define VIDC20_ECTL_VS_MASK (3 << 18) 180#define VIDC20_ECTL_VS_VSYNC (0 << 18) 181#define VIDC20_ECTL_VS_NVSYNC (1 << 18) 182#define VIDC20_ECTL_VS_CSYNC (2 << 18) 183#define VIDC20_ECTL_VS_NCSYNC (3 << 18) 184 185#define VIDC20_DCTL 0xf0000000 186/* 0-9 = number of words in scanline */ 187#define VIDC20_DCTL_SNA (1 << 12) 188#define VIDC20_DCTL_HDIS (1 << 13) 189#define VIDC20_DCTL_BUS_NS (0 << 16) 190#define VIDC20_DCTL_BUS_D31_0 (1 << 16) 191#define VIDC20_DCTL_BUS_D63_32 (2 << 16) 192#define VIDC20_DCTL_BUS_D63_0 (3 << 16) 193#define VIDC20_DCTL_VRAM_DIS (0 << 18) 194#define VIDC20_DCTL_VRAM_PXCLK (1 << 18) 195#define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18) 196#define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18) 197 198#endif 199