1/* 2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG. 3 * 4 * Copyright (C) 2004 Texas Instruments, Inc. 5 * Copyright (C) 2004-2005 David Brownell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22#undef DEBUG 23#undef VERBOSE 24 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/ioport.h> 28#include <linux/types.h> 29#include <linux/errno.h> 30#include <linux/delay.h> 31#include <linux/slab.h> 32#include <linux/init.h> 33#include <linux/timer.h> 34#include <linux/list.h> 35#include <linux/interrupt.h> 36#include <linux/proc_fs.h> 37#include <linux/mm.h> 38#include <linux/moduleparam.h> 39#include <linux/platform_device.h> 40#include <linux/usb/ch9.h> 41#include <linux/usb_gadget.h> 42#include <linux/usb/otg.h> 43#include <linux/dma-mapping.h> 44#include <linux/clk.h> 45 46#include <asm/byteorder.h> 47#include <asm/io.h> 48#include <asm/irq.h> 49#include <asm/system.h> 50#include <asm/unaligned.h> 51#include <asm/mach-types.h> 52 53#include <asm/arch/dma.h> 54#include <asm/arch/usb.h> 55 56#include "omap_udc.h" 57 58#undef USB_TRACE 59 60/* bulk DMA seems to be behaving for both IN and OUT */ 61#define USE_DMA 62 63#ifdef CONFIG_ARCH_OMAP2 64#undef USE_DMA 65#endif 66 67/* ISO too */ 68#define USE_ISO 69 70#define DRIVER_DESC "OMAP UDC driver" 71#define DRIVER_VERSION "4 October 2004" 72 73#define DMA_ADDR_INVALID (~(dma_addr_t)0) 74 75 76/* 77 * The OMAP UDC needs _very_ early endpoint setup: before enabling the 78 * D+ pullup to allow enumeration. That's too early for the gadget 79 * framework to use from usb_endpoint_enable(), which happens after 80 * enumeration as part of activating an interface. (But if we add an 81 * optional new "UDC not yet running" state to the gadget driver model, 82 * even just during driver binding, the endpoint autoconfig logic is the 83 * natural spot to manufacture new endpoints.) 84 * 85 * So instead of using endpoint enable calls to control the hardware setup, 86 * this driver defines a "fifo mode" parameter. It's used during driver 87 * initialization to choose among a set of pre-defined endpoint configs. 88 * See omap_udc_setup() for available modes, or to add others. That code 89 * lives in an init section, so use this driver as a module if you need 90 * to change the fifo mode after the kernel boots. 91 * 92 * Gadget drivers normally ignore endpoints they don't care about, and 93 * won't include them in configuration descriptors. That means only 94 * misbehaving hosts would even notice they exist. 95 */ 96#ifdef USE_ISO 97static unsigned fifo_mode = 3; 98#else 99static unsigned fifo_mode = 0; 100#endif 101 102/* "modprobe omap_udc fifo_mode=42", or else as a kernel 103 * boot parameter "omap_udc:fifo_mode=42" 104 */ 105module_param (fifo_mode, uint, 0); 106MODULE_PARM_DESC (fifo_mode, "endpoint configuration"); 107 108#ifdef USE_DMA 109static unsigned use_dma = 1; 110 111/* "modprobe omap_udc use_dma=y", or else as a kernel 112 * boot parameter "omap_udc:use_dma=y" 113 */ 114module_param (use_dma, bool, 0); 115MODULE_PARM_DESC (use_dma, "enable/disable DMA"); 116#else /* !USE_DMA */ 117 118/* save a bit of code */ 119#define use_dma 0 120#endif /* !USE_DMA */ 121 122 123static const char driver_name [] = "omap_udc"; 124static const char driver_desc [] = DRIVER_DESC; 125 126/*-------------------------------------------------------------------------*/ 127 128/* there's a notion of "current endpoint" for modifying endpoint 129 * state, and PIO access to its FIFO. 130 */ 131 132static void use_ep(struct omap_ep *ep, u16 select) 133{ 134 u16 num = ep->bEndpointAddress & 0x0f; 135 136 if (ep->bEndpointAddress & USB_DIR_IN) 137 num |= UDC_EP_DIR; 138 UDC_EP_NUM_REG = num | select; 139 /* when select, MUST deselect later !! */ 140} 141 142static inline void deselect_ep(void) 143{ 144 UDC_EP_NUM_REG &= ~UDC_EP_SEL; 145 /* 6 wait states before TX will happen */ 146} 147 148static void dma_channel_claim(struct omap_ep *ep, unsigned preferred); 149 150/*-------------------------------------------------------------------------*/ 151 152static int omap_ep_enable(struct usb_ep *_ep, 153 const struct usb_endpoint_descriptor *desc) 154{ 155 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 156 struct omap_udc *udc; 157 unsigned long flags; 158 u16 maxp; 159 160 /* catch various bogus parameters */ 161 if (!_ep || !desc || ep->desc 162 || desc->bDescriptorType != USB_DT_ENDPOINT 163 || ep->bEndpointAddress != desc->bEndpointAddress 164 || ep->maxpacket < le16_to_cpu 165 (desc->wMaxPacketSize)) { 166 DBG("%s, bad ep or descriptor\n", __FUNCTION__); 167 return -EINVAL; 168 } 169 maxp = le16_to_cpu (desc->wMaxPacketSize); 170 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK 171 && maxp != ep->maxpacket) 172 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket 173 || !desc->wMaxPacketSize) { 174 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name); 175 return -ERANGE; 176 } 177 178#ifdef USE_ISO 179 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC 180 && desc->bInterval != 1)) { 181 /* hardware wants period = 1; USB allows 2^(Interval-1) */ 182 DBG("%s, unsupported ISO period %dms\n", _ep->name, 183 1 << (desc->bInterval - 1)); 184 return -EDOM; 185 } 186#else 187 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 188 DBG("%s, ISO nyet\n", _ep->name); 189 return -EDOM; 190 } 191#endif 192 193 /* xfer types must match, except that interrupt ~= bulk */ 194 if (ep->bmAttributes != desc->bmAttributes 195 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK 196 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { 197 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); 198 return -EINVAL; 199 } 200 201 udc = ep->udc; 202 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 203 DBG("%s, bogus device state\n", __FUNCTION__); 204 return -ESHUTDOWN; 205 } 206 207 spin_lock_irqsave(&udc->lock, flags); 208 209 ep->desc = desc; 210 ep->irqs = 0; 211 ep->stopped = 0; 212 ep->ep.maxpacket = maxp; 213 214 /* set endpoint to initial state */ 215 ep->dma_channel = 0; 216 ep->has_dma = 0; 217 ep->lch = -1; 218 use_ep(ep, UDC_EP_SEL); 219 UDC_CTRL_REG = udc->clr_halt; 220 ep->ackwait = 0; 221 deselect_ep(); 222 223 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 224 list_add(&ep->iso, &udc->iso); 225 226 /* maybe assign a DMA channel to this endpoint */ 227 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK) 228 dma_channel_claim(ep, 0); 229 230 /* PIO OUT may RX packets */ 231 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC 232 && !ep->has_dma 233 && !(ep->bEndpointAddress & USB_DIR_IN)) { 234 UDC_CTRL_REG = UDC_SET_FIFO_EN; 235 ep->ackwait = 1 + ep->double_buf; 236 } 237 238 spin_unlock_irqrestore(&udc->lock, flags); 239 VDBG("%s enabled\n", _ep->name); 240 return 0; 241} 242 243static void nuke(struct omap_ep *, int status); 244 245static int omap_ep_disable(struct usb_ep *_ep) 246{ 247 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 248 unsigned long flags; 249 250 if (!_ep || !ep->desc) { 251 DBG("%s, %s not enabled\n", __FUNCTION__, 252 _ep ? ep->ep.name : NULL); 253 return -EINVAL; 254 } 255 256 spin_lock_irqsave(&ep->udc->lock, flags); 257 ep->desc = NULL; 258 nuke (ep, -ESHUTDOWN); 259 ep->ep.maxpacket = ep->maxpacket; 260 ep->has_dma = 0; 261 UDC_CTRL_REG = UDC_SET_HALT; 262 list_del_init(&ep->iso); 263 del_timer(&ep->timer); 264 265 spin_unlock_irqrestore(&ep->udc->lock, flags); 266 267 VDBG("%s disabled\n", _ep->name); 268 return 0; 269} 270 271/*-------------------------------------------------------------------------*/ 272 273static struct usb_request * 274omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 275{ 276 struct omap_req *req; 277 278 req = kzalloc(sizeof(*req), gfp_flags); 279 if (req) { 280 req->req.dma = DMA_ADDR_INVALID; 281 INIT_LIST_HEAD (&req->queue); 282 } 283 return &req->req; 284} 285 286static void 287omap_free_request(struct usb_ep *ep, struct usb_request *_req) 288{ 289 struct omap_req *req = container_of(_req, struct omap_req, req); 290 291 if (_req) 292 kfree (req); 293} 294 295/*-------------------------------------------------------------------------*/ 296 297 298static void * 299omap_alloc_buffer( 300 struct usb_ep *_ep, 301 unsigned bytes, 302 dma_addr_t *dma, 303 gfp_t gfp_flags 304) 305{ 306 void *retval; 307 struct omap_ep *ep; 308 309 if (!_ep) 310 return NULL; 311 312 ep = container_of(_ep, struct omap_ep, ep); 313 if (use_dma && ep->has_dma) { 314 static int warned; 315 if (!warned && bytes < PAGE_SIZE) { 316 dev_warn(ep->udc->gadget.dev.parent, 317 "using dma_alloc_coherent for " 318 "small allocations wastes memory\n"); 319 warned++; 320 } 321 return dma_alloc_coherent(ep->udc->gadget.dev.parent, 322 bytes, dma, gfp_flags); 323 } 324 325 retval = kmalloc(bytes, gfp_flags); 326 if (retval) 327 *dma = virt_to_phys(retval); 328 return retval; 329} 330 331static DEFINE_SPINLOCK(buflock); 332static LIST_HEAD(buffers); 333 334struct free_record { 335 struct list_head list; 336 struct device *dev; 337 unsigned bytes; 338 dma_addr_t dma; 339}; 340 341static void do_free(unsigned long ignored) 342{ 343 spin_lock_irq(&buflock); 344 while (!list_empty(&buffers)) { 345 struct free_record *buf; 346 347 buf = list_entry(buffers.next, struct free_record, list); 348 list_del(&buf->list); 349 spin_unlock_irq(&buflock); 350 351 dma_free_coherent(buf->dev, buf->bytes, buf, buf->dma); 352 353 spin_lock_irq(&buflock); 354 } 355 spin_unlock_irq(&buflock); 356} 357 358static DECLARE_TASKLET(deferred_free, do_free, 0); 359 360static void omap_free_buffer( 361 struct usb_ep *_ep, 362 void *buf, 363 dma_addr_t dma, 364 unsigned bytes 365) 366{ 367 if (!_ep) { 368 WARN_ON(1); 369 return; 370 } 371 372 /* free memory into the right allocator */ 373 if (dma != DMA_ADDR_INVALID) { 374 struct omap_ep *ep; 375 struct free_record *rec = buf; 376 unsigned long flags; 377 378 ep = container_of(_ep, struct omap_ep, ep); 379 380 rec->dev = ep->udc->gadget.dev.parent; 381 rec->bytes = bytes; 382 rec->dma = dma; 383 384 spin_lock_irqsave(&buflock, flags); 385 list_add_tail(&rec->list, &buffers); 386 tasklet_schedule(&deferred_free); 387 spin_unlock_irqrestore(&buflock, flags); 388 } else 389 kfree(buf); 390} 391 392/*-------------------------------------------------------------------------*/ 393 394static void 395done(struct omap_ep *ep, struct omap_req *req, int status) 396{ 397 unsigned stopped = ep->stopped; 398 399 list_del_init(&req->queue); 400 401 if (req->req.status == -EINPROGRESS) 402 req->req.status = status; 403 else 404 status = req->req.status; 405 406 if (use_dma && ep->has_dma) { 407 if (req->mapped) { 408 dma_unmap_single(ep->udc->gadget.dev.parent, 409 req->req.dma, req->req.length, 410 (ep->bEndpointAddress & USB_DIR_IN) 411 ? DMA_TO_DEVICE 412 : DMA_FROM_DEVICE); 413 req->req.dma = DMA_ADDR_INVALID; 414 req->mapped = 0; 415 } else 416 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, 417 req->req.dma, req->req.length, 418 (ep->bEndpointAddress & USB_DIR_IN) 419 ? DMA_TO_DEVICE 420 : DMA_FROM_DEVICE); 421 } 422 423#ifndef USB_TRACE 424 if (status && status != -ESHUTDOWN) 425#endif 426 VDBG("complete %s req %p stat %d len %u/%u\n", 427 ep->ep.name, &req->req, status, 428 req->req.actual, req->req.length); 429 430 /* don't modify queue heads during completion callback */ 431 ep->stopped = 1; 432 spin_unlock(&ep->udc->lock); 433 req->req.complete(&ep->ep, &req->req); 434 spin_lock(&ep->udc->lock); 435 ep->stopped = stopped; 436} 437 438/*-------------------------------------------------------------------------*/ 439 440#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL) 441#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL) 442 443#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY) 444#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY) 445 446static inline int 447write_packet(u8 *buf, struct omap_req *req, unsigned max) 448{ 449 unsigned len; 450 u16 *wp; 451 452 len = min(req->req.length - req->req.actual, max); 453 req->req.actual += len; 454 455 max = len; 456 if (likely((((int)buf) & 1) == 0)) { 457 wp = (u16 *)buf; 458 while (max >= 2) { 459 UDC_DATA_REG = *wp++; 460 max -= 2; 461 } 462 buf = (u8 *)wp; 463 } 464 while (max--) 465 *(volatile u8 *)&UDC_DATA_REG = *buf++; 466 return len; 467} 468 469 470 471// return: 0 = still running, 1 = completed, negative = errno 472static int write_fifo(struct omap_ep *ep, struct omap_req *req) 473{ 474 u8 *buf; 475 unsigned count; 476 int is_last; 477 u16 ep_stat; 478 479 buf = req->req.buf + req->req.actual; 480 prefetch(buf); 481 482 /* PIO-IN isn't double buffered except for iso */ 483 ep_stat = UDC_STAT_FLG_REG; 484 if (ep_stat & UDC_FIFO_UNWRITABLE) 485 return 0; 486 487 count = ep->ep.maxpacket; 488 count = write_packet(buf, req, count); 489 UDC_CTRL_REG = UDC_SET_FIFO_EN; 490 ep->ackwait = 1; 491 492 /* last packet is often short (sometimes a zlp) */ 493 if (count != ep->ep.maxpacket) 494 is_last = 1; 495 else if (req->req.length == req->req.actual 496 && !req->req.zero) 497 is_last = 1; 498 else 499 is_last = 0; 500 501 /* NOTE: requests complete when all IN data is in a 502 * FIFO (or sometimes later, if a zlp was needed). 503 * Use usb_ep_fifo_status() where needed. 504 */ 505 if (is_last) 506 done(ep, req, 0); 507 return is_last; 508} 509 510static inline int 511read_packet(u8 *buf, struct omap_req *req, unsigned avail) 512{ 513 unsigned len; 514 u16 *wp; 515 516 len = min(req->req.length - req->req.actual, avail); 517 req->req.actual += len; 518 avail = len; 519 520 if (likely((((int)buf) & 1) == 0)) { 521 wp = (u16 *)buf; 522 while (avail >= 2) { 523 *wp++ = UDC_DATA_REG; 524 avail -= 2; 525 } 526 buf = (u8 *)wp; 527 } 528 while (avail--) 529 *buf++ = *(volatile u8 *)&UDC_DATA_REG; 530 return len; 531} 532 533// return: 0 = still running, 1 = queue empty, negative = errno 534static int read_fifo(struct omap_ep *ep, struct omap_req *req) 535{ 536 u8 *buf; 537 unsigned count, avail; 538 int is_last; 539 540 buf = req->req.buf + req->req.actual; 541 prefetchw(buf); 542 543 for (;;) { 544 u16 ep_stat = UDC_STAT_FLG_REG; 545 546 is_last = 0; 547 if (ep_stat & FIFO_EMPTY) { 548 if (!ep->double_buf) 549 break; 550 ep->fnf = 1; 551 } 552 if (ep_stat & UDC_EP_HALTED) 553 break; 554 555 if (ep_stat & UDC_FIFO_FULL) 556 avail = ep->ep.maxpacket; 557 else { 558 avail = UDC_RXFSTAT_REG; 559 ep->fnf = ep->double_buf; 560 } 561 count = read_packet(buf, req, avail); 562 563 /* partial packet reads may not be errors */ 564 if (count < ep->ep.maxpacket) { 565 is_last = 1; 566 /* overflowed this request? flush extra data */ 567 if (count != avail) { 568 req->req.status = -EOVERFLOW; 569 avail -= count; 570 while (avail--) 571 (void) *(volatile u8 *)&UDC_DATA_REG; 572 } 573 } else if (req->req.length == req->req.actual) 574 is_last = 1; 575 else 576 is_last = 0; 577 578 if (!ep->bEndpointAddress) 579 break; 580 if (is_last) 581 done(ep, req, 0); 582 break; 583 } 584 return is_last; 585} 586 587/*-------------------------------------------------------------------------*/ 588 589static inline dma_addr_t dma_csac(unsigned lch) 590{ 591 dma_addr_t csac; 592 593 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is 594 * read before the DMA controller finished disabling the channel. 595 */ 596 csac = OMAP_DMA_CSAC_REG(lch); 597 if (csac == 0) 598 csac = OMAP_DMA_CSAC_REG(lch); 599 return csac; 600} 601 602static inline dma_addr_t dma_cdac(unsigned lch) 603{ 604 dma_addr_t cdac; 605 606 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is 607 * read before the DMA controller finished disabling the channel. 608 */ 609 cdac = OMAP_DMA_CDAC_REG(lch); 610 if (cdac == 0) 611 cdac = OMAP_DMA_CDAC_REG(lch); 612 return cdac; 613} 614 615static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) 616{ 617 dma_addr_t end; 618 619 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports 620 * the last transfer's bytecount by more than a FIFO's worth. 621 */ 622 if (cpu_is_omap15xx()) 623 return 0; 624 625 end = dma_csac(ep->lch); 626 if (end == ep->dma_counter) 627 return 0; 628 629 end |= start & (0xffff << 16); 630 if (end < start) 631 end += 0x10000; 632 return end - start; 633} 634 635#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \ 636 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \ 637 : dma_cdac(x)) 638 639static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) 640{ 641 dma_addr_t end; 642 643 end = DMA_DEST_LAST(ep->lch); 644 if (end == ep->dma_counter) 645 return 0; 646 647 end |= start & (0xffff << 16); 648 if (cpu_is_omap15xx()) 649 end++; 650 if (end < start) 651 end += 0x10000; 652 return end - start; 653} 654 655 656/* Each USB transfer request using DMA maps to one or more DMA transfers. 657 * When DMA completion isn't request completion, the UDC continues with 658 * the next DMA transfer for that USB transfer. 659 */ 660 661static void next_in_dma(struct omap_ep *ep, struct omap_req *req) 662{ 663 u16 txdma_ctrl; 664 unsigned length = req->req.length - req->req.actual; 665 const int sync_mode = cpu_is_omap15xx() 666 ? OMAP_DMA_SYNC_FRAME 667 : OMAP_DMA_SYNC_ELEMENT; 668 669 /* measure length in either bytes or packets */ 670 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC) 671 || (cpu_is_omap15xx() && length < ep->maxpacket)) { 672 txdma_ctrl = UDC_TXN_EOT | length; 673 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, 674 length, 1, sync_mode, 0, 0); 675 } else { 676 length = min(length / ep->maxpacket, 677 (unsigned) UDC_TXN_TSC + 1); 678 txdma_ctrl = length; 679 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, 680 ep->ep.maxpacket >> 1, length, sync_mode, 681 0, 0); 682 length *= ep->maxpacket; 683 } 684 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF, 685 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 686 0, 0); 687 688 omap_start_dma(ep->lch); 689 ep->dma_counter = dma_csac(ep->lch); 690 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel); 691 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl; 692 req->dma_bytes = length; 693} 694 695static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) 696{ 697 if (status == 0) { 698 req->req.actual += req->dma_bytes; 699 700 /* return if this request needs to send data or zlp */ 701 if (req->req.actual < req->req.length) 702 return; 703 if (req->req.zero 704 && req->dma_bytes != 0 705 && (req->req.actual % ep->maxpacket) == 0) 706 return; 707 } else 708 req->req.actual += dma_src_len(ep, req->req.dma 709 + req->req.actual); 710 711 /* tx completion */ 712 omap_stop_dma(ep->lch); 713 UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel); 714 done(ep, req, status); 715} 716 717static void next_out_dma(struct omap_ep *ep, struct omap_req *req) 718{ 719 unsigned packets; 720 721 /* NOTE: we filtered out "short reads" before, so we know 722 * the buffer has only whole numbers of packets. 723 */ 724 725 /* set up this DMA transfer, enable the fifo, start */ 726 packets = (req->req.length - req->req.actual) / ep->ep.maxpacket; 727 packets = min(packets, (unsigned)UDC_RXN_TC + 1); 728 req->dma_bytes = packets * ep->ep.maxpacket; 729 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, 730 ep->ep.maxpacket >> 1, packets, 731 OMAP_DMA_SYNC_ELEMENT, 732 0, 0); 733 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, 734 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, 735 0, 0); 736 ep->dma_counter = DMA_DEST_LAST(ep->lch); 737 738 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1); 739 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel); 740 UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf); 741 UDC_CTRL_REG = UDC_SET_FIFO_EN; 742 743 omap_start_dma(ep->lch); 744} 745 746static void 747finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) 748{ 749 u16 count; 750 751 if (status == 0) 752 ep->dma_counter = (u16) (req->req.dma + req->req.actual); 753 count = dma_dest_len(ep, req->req.dma + req->req.actual); 754 count += req->req.actual; 755 if (one) 756 count--; 757 if (count <= req->req.length) 758 req->req.actual = count; 759 760 if (count != req->dma_bytes || status) 761 omap_stop_dma(ep->lch); 762 763 /* if this wasn't short, request may need another transfer */ 764 else if (req->req.actual < req->req.length) 765 return; 766 767 /* rx completion */ 768 UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel); 769 done(ep, req, status); 770} 771 772static void dma_irq(struct omap_udc *udc, u16 irq_src) 773{ 774 u16 dman_stat = UDC_DMAN_STAT_REG; 775 struct omap_ep *ep; 776 struct omap_req *req; 777 778 /* IN dma: tx to host */ 779 if (irq_src & UDC_TXN_DONE) { 780 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)]; 781 ep->irqs++; 782 /* can see TXN_DONE after dma abort */ 783 if (!list_empty(&ep->queue)) { 784 req = container_of(ep->queue.next, 785 struct omap_req, queue); 786 finish_in_dma(ep, req, 0); 787 } 788 UDC_IRQ_SRC_REG = UDC_TXN_DONE; 789 790 if (!list_empty (&ep->queue)) { 791 req = container_of(ep->queue.next, 792 struct omap_req, queue); 793 next_in_dma(ep, req); 794 } 795 } 796 797 /* OUT dma: rx from host */ 798 if (irq_src & UDC_RXN_EOT) { 799 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; 800 ep->irqs++; 801 /* can see RXN_EOT after dma abort */ 802 if (!list_empty(&ep->queue)) { 803 req = container_of(ep->queue.next, 804 struct omap_req, queue); 805 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); 806 } 807 UDC_IRQ_SRC_REG = UDC_RXN_EOT; 808 809 if (!list_empty (&ep->queue)) { 810 req = container_of(ep->queue.next, 811 struct omap_req, queue); 812 next_out_dma(ep, req); 813 } 814 } 815 816 if (irq_src & UDC_RXN_CNT) { 817 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; 818 ep->irqs++; 819 /* omap15xx does this unasked... */ 820 VDBG("%s, RX_CNT irq?\n", ep->ep.name); 821 UDC_IRQ_SRC_REG = UDC_RXN_CNT; 822 } 823} 824 825static void dma_error(int lch, u16 ch_status, void *data) 826{ 827 struct omap_ep *ep = data; 828 829 /* if ch_status & OMAP_DMA_DROP_IRQ ... */ 830 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */ 831 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status); 832 833 /* complete current transfer ... */ 834} 835 836static void dma_channel_claim(struct omap_ep *ep, unsigned channel) 837{ 838 u16 reg; 839 int status, restart, is_in; 840 841 is_in = ep->bEndpointAddress & USB_DIR_IN; 842 if (is_in) 843 reg = UDC_TXDMA_CFG_REG; 844 else 845 reg = UDC_RXDMA_CFG_REG; 846 reg |= UDC_DMA_REQ; /* "pulse" activated */ 847 848 ep->dma_channel = 0; 849 ep->lch = -1; 850 if (channel == 0 || channel > 3) { 851 if ((reg & 0x0f00) == 0) 852 channel = 3; 853 else if ((reg & 0x00f0) == 0) 854 channel = 2; 855 else if ((reg & 0x000f) == 0) /* preferred for ISO */ 856 channel = 1; 857 else { 858 status = -EMLINK; 859 goto just_restart; 860 } 861 } 862 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1)); 863 ep->dma_channel = channel; 864 865 if (is_in) { 866 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel, 867 ep->ep.name, dma_error, ep, &ep->lch); 868 if (status == 0) { 869 UDC_TXDMA_CFG_REG = reg; 870 /* EMIFF */ 871 omap_set_dma_src_burst_mode(ep->lch, 872 OMAP_DMA_DATA_BURST_4); 873 omap_set_dma_src_data_pack(ep->lch, 1); 874 /* TIPB */ 875 omap_set_dma_dest_params(ep->lch, 876 OMAP_DMA_PORT_TIPB, 877 OMAP_DMA_AMODE_CONSTANT, 878 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), 879 0, 0); 880 } 881 } else { 882 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel, 883 ep->ep.name, dma_error, ep, &ep->lch); 884 if (status == 0) { 885 UDC_RXDMA_CFG_REG = reg; 886 /* TIPB */ 887 omap_set_dma_src_params(ep->lch, 888 OMAP_DMA_PORT_TIPB, 889 OMAP_DMA_AMODE_CONSTANT, 890 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), 891 0, 0); 892 /* EMIFF */ 893 omap_set_dma_dest_burst_mode(ep->lch, 894 OMAP_DMA_DATA_BURST_4); 895 omap_set_dma_dest_data_pack(ep->lch, 1); 896 } 897 } 898 if (status) 899 ep->dma_channel = 0; 900 else { 901 ep->has_dma = 1; 902 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ); 903 904 /* channel type P: hw synch (fifo) */ 905 if (!cpu_is_omap15xx()) 906 OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2; 907 } 908 909just_restart: 910 /* restart any queue, even if the claim failed */ 911 restart = !ep->stopped && !list_empty(&ep->queue); 912 913 if (status) 914 DBG("%s no dma channel: %d%s\n", ep->ep.name, status, 915 restart ? " (restart)" : ""); 916 else 917 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name, 918 is_in ? 't' : 'r', 919 ep->dma_channel - 1, ep->lch, 920 restart ? " (restart)" : ""); 921 922 if (restart) { 923 struct omap_req *req; 924 req = container_of(ep->queue.next, struct omap_req, queue); 925 if (ep->has_dma) 926 (is_in ? next_in_dma : next_out_dma)(ep, req); 927 else { 928 use_ep(ep, UDC_EP_SEL); 929 (is_in ? write_fifo : read_fifo)(ep, req); 930 deselect_ep(); 931 if (!is_in) { 932 UDC_CTRL_REG = UDC_SET_FIFO_EN; 933 ep->ackwait = 1 + ep->double_buf; 934 } 935 /* IN: 6 wait states before it'll tx */ 936 } 937 } 938} 939 940static void dma_channel_release(struct omap_ep *ep) 941{ 942 int shift = 4 * (ep->dma_channel - 1); 943 u16 mask = 0x0f << shift; 944 struct omap_req *req; 945 int active; 946 947 /* abort any active usb transfer request */ 948 if (!list_empty(&ep->queue)) 949 req = container_of(ep->queue.next, struct omap_req, queue); 950 else 951 req = NULL; 952 953 active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0; 954 955 DBG("%s release %s %cxdma%d %p\n", ep->ep.name, 956 active ? "active" : "idle", 957 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', 958 ep->dma_channel - 1, req); 959 960 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before 961 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them. 962 */ 963 964 /* wait till current packet DMA finishes, and fifo empties */ 965 if (ep->bEndpointAddress & USB_DIR_IN) { 966 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; 967 968 if (req) { 969 finish_in_dma(ep, req, -ECONNRESET); 970 971 /* clear FIFO; hosts probably won't empty it */ 972 use_ep(ep, UDC_EP_SEL); 973 UDC_CTRL_REG = UDC_CLR_EP; 974 deselect_ep(); 975 } 976 while (UDC_TXDMA_CFG_REG & mask) 977 udelay(10); 978 } else { 979 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; 980 981 /* dma empties the fifo */ 982 while (UDC_RXDMA_CFG_REG & mask) 983 udelay(10); 984 if (req) 985 finish_out_dma(ep, req, -ECONNRESET, 0); 986 } 987 omap_free_dma(ep->lch); 988 ep->dma_channel = 0; 989 ep->lch = -1; 990 /* has_dma still set, till endpoint is fully quiesced */ 991} 992 993 994/*-------------------------------------------------------------------------*/ 995 996static int 997omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 998{ 999 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 1000 struct omap_req *req = container_of(_req, struct omap_req, req); 1001 struct omap_udc *udc; 1002 unsigned long flags; 1003 int is_iso = 0; 1004 1005 /* catch various bogus parameters */ 1006 if (!_req || !req->req.complete || !req->req.buf 1007 || !list_empty(&req->queue)) { 1008 DBG("%s, bad params\n", __FUNCTION__); 1009 return -EINVAL; 1010 } 1011 if (!_ep || (!ep->desc && ep->bEndpointAddress)) { 1012 DBG("%s, bad ep\n", __FUNCTION__); 1013 return -EINVAL; 1014 } 1015 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { 1016 if (req->req.length > ep->ep.maxpacket) 1017 return -EMSGSIZE; 1018 is_iso = 1; 1019 } 1020 1021 /* this isn't bogus, but OMAP DMA isn't the only hardware to 1022 * have a hard time with partial packet reads... reject it. 1023 */ 1024 if (use_dma 1025 && ep->has_dma 1026 && ep->bEndpointAddress != 0 1027 && (ep->bEndpointAddress & USB_DIR_IN) == 0 1028 && (req->req.length % ep->ep.maxpacket) != 0) { 1029 DBG("%s, no partial packet OUT reads\n", __FUNCTION__); 1030 return -EMSGSIZE; 1031 } 1032 1033 udc = ep->udc; 1034 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 1035 return -ESHUTDOWN; 1036 1037 if (use_dma && ep->has_dma) { 1038 if (req->req.dma == DMA_ADDR_INVALID) { 1039 req->req.dma = dma_map_single( 1040 ep->udc->gadget.dev.parent, 1041 req->req.buf, 1042 req->req.length, 1043 (ep->bEndpointAddress & USB_DIR_IN) 1044 ? DMA_TO_DEVICE 1045 : DMA_FROM_DEVICE); 1046 req->mapped = 1; 1047 } else { 1048 dma_sync_single_for_device( 1049 ep->udc->gadget.dev.parent, 1050 req->req.dma, req->req.length, 1051 (ep->bEndpointAddress & USB_DIR_IN) 1052 ? DMA_TO_DEVICE 1053 : DMA_FROM_DEVICE); 1054 req->mapped = 0; 1055 } 1056 } 1057 1058 VDBG("%s queue req %p, len %d buf %p\n", 1059 ep->ep.name, _req, _req->length, _req->buf); 1060 1061 spin_lock_irqsave(&udc->lock, flags); 1062 1063 req->req.status = -EINPROGRESS; 1064 req->req.actual = 0; 1065 1066 /* maybe kickstart non-iso i/o queues */ 1067 if (is_iso) 1068 UDC_IRQ_EN_REG |= UDC_SOF_IE; 1069 else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { 1070 int is_in; 1071 1072 if (ep->bEndpointAddress == 0) { 1073 if (!udc->ep0_pending || !list_empty (&ep->queue)) { 1074 spin_unlock_irqrestore(&udc->lock, flags); 1075 return -EL2HLT; 1076 } 1077 1078 /* empty DATA stage? */ 1079 is_in = udc->ep0_in; 1080 if (!req->req.length) { 1081 1082 /* chip became CONFIGURED or ADDRESSED 1083 * earlier; drivers may already have queued 1084 * requests to non-control endpoints 1085 */ 1086 if (udc->ep0_set_config) { 1087 u16 irq_en = UDC_IRQ_EN_REG; 1088 1089 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; 1090 if (!udc->ep0_reset_config) 1091 irq_en |= UDC_EPN_RX_IE 1092 | UDC_EPN_TX_IE; 1093 UDC_IRQ_EN_REG = irq_en; 1094 } 1095 1096 /* STATUS for zero length DATA stages is 1097 * always an IN ... even for IN transfers, 1098 * a wierd case which seem to stall OMAP. 1099 */ 1100 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR); 1101 UDC_CTRL_REG = UDC_CLR_EP; 1102 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1103 UDC_EP_NUM_REG = UDC_EP_DIR; 1104 1105 /* cleanup */ 1106 udc->ep0_pending = 0; 1107 done(ep, req, 0); 1108 req = NULL; 1109 1110 /* non-empty DATA stage */ 1111 } else if (is_in) { 1112 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1113 } else { 1114 if (udc->ep0_setup) 1115 goto irq_wait; 1116 UDC_EP_NUM_REG = UDC_EP_SEL; 1117 } 1118 } else { 1119 is_in = ep->bEndpointAddress & USB_DIR_IN; 1120 if (!ep->has_dma) 1121 use_ep(ep, UDC_EP_SEL); 1122 /* if ISO: SOF IRQs must be enabled/disabled! */ 1123 } 1124 1125 if (ep->has_dma) 1126 (is_in ? next_in_dma : next_out_dma)(ep, req); 1127 else if (req) { 1128 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1) 1129 req = NULL; 1130 deselect_ep(); 1131 if (!is_in) { 1132 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1133 ep->ackwait = 1 + ep->double_buf; 1134 } 1135 /* IN: 6 wait states before it'll tx */ 1136 } 1137 } 1138 1139irq_wait: 1140 /* irq handler advances the queue */ 1141 if (req != NULL) 1142 list_add_tail(&req->queue, &ep->queue); 1143 spin_unlock_irqrestore(&udc->lock, flags); 1144 1145 return 0; 1146} 1147 1148static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1149{ 1150 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 1151 struct omap_req *req; 1152 unsigned long flags; 1153 1154 if (!_ep || !_req) 1155 return -EINVAL; 1156 1157 spin_lock_irqsave(&ep->udc->lock, flags); 1158 1159 /* make sure it's actually queued on this endpoint */ 1160 list_for_each_entry (req, &ep->queue, queue) { 1161 if (&req->req == _req) 1162 break; 1163 } 1164 if (&req->req != _req) { 1165 spin_unlock_irqrestore(&ep->udc->lock, flags); 1166 return -EINVAL; 1167 } 1168 1169 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) { 1170 int channel = ep->dma_channel; 1171 1172 /* releasing the channel cancels the request, 1173 * reclaiming the channel restarts the queue 1174 */ 1175 dma_channel_release(ep); 1176 dma_channel_claim(ep, channel); 1177 } else 1178 done(ep, req, -ECONNRESET); 1179 spin_unlock_irqrestore(&ep->udc->lock, flags); 1180 return 0; 1181} 1182 1183/*-------------------------------------------------------------------------*/ 1184 1185static int omap_ep_set_halt(struct usb_ep *_ep, int value) 1186{ 1187 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); 1188 unsigned long flags; 1189 int status = -EOPNOTSUPP; 1190 1191 spin_lock_irqsave(&ep->udc->lock, flags); 1192 1193 /* just use protocol stalls for ep0; real halts are annoying */ 1194 if (ep->bEndpointAddress == 0) { 1195 if (!ep->udc->ep0_pending) 1196 status = -EINVAL; 1197 else if (value) { 1198 if (ep->udc->ep0_set_config) { 1199 WARN("error changing config?\n"); 1200 UDC_SYSCON2_REG = UDC_CLR_CFG; 1201 } 1202 UDC_SYSCON2_REG = UDC_STALL_CMD; 1203 ep->udc->ep0_pending = 0; 1204 status = 0; 1205 } else /* NOP */ 1206 status = 0; 1207 1208 /* otherwise, all active non-ISO endpoints can halt */ 1209 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) { 1210 1211 /* IN endpoints must already be idle */ 1212 if ((ep->bEndpointAddress & USB_DIR_IN) 1213 && !list_empty(&ep->queue)) { 1214 status = -EAGAIN; 1215 goto done; 1216 } 1217 1218 if (value) { 1219 int channel; 1220 1221 if (use_dma && ep->dma_channel 1222 && !list_empty(&ep->queue)) { 1223 channel = ep->dma_channel; 1224 dma_channel_release(ep); 1225 } else 1226 channel = 0; 1227 1228 use_ep(ep, UDC_EP_SEL); 1229 if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) { 1230 UDC_CTRL_REG = UDC_SET_HALT; 1231 status = 0; 1232 } else 1233 status = -EAGAIN; 1234 deselect_ep(); 1235 1236 if (channel) 1237 dma_channel_claim(ep, channel); 1238 } else { 1239 use_ep(ep, 0); 1240 UDC_CTRL_REG = ep->udc->clr_halt; 1241 ep->ackwait = 0; 1242 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1243 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1244 ep->ackwait = 1 + ep->double_buf; 1245 } 1246 } 1247 } 1248done: 1249 VDBG("%s %s halt stat %d\n", ep->ep.name, 1250 value ? "set" : "clear", status); 1251 1252 spin_unlock_irqrestore(&ep->udc->lock, flags); 1253 return status; 1254} 1255 1256static struct usb_ep_ops omap_ep_ops = { 1257 .enable = omap_ep_enable, 1258 .disable = omap_ep_disable, 1259 1260 .alloc_request = omap_alloc_request, 1261 .free_request = omap_free_request, 1262 1263 .alloc_buffer = omap_alloc_buffer, 1264 .free_buffer = omap_free_buffer, 1265 1266 .queue = omap_ep_queue, 1267 .dequeue = omap_ep_dequeue, 1268 1269 .set_halt = omap_ep_set_halt, 1270 // fifo_status ... report bytes in fifo 1271 // fifo_flush ... flush fifo 1272}; 1273 1274/*-------------------------------------------------------------------------*/ 1275 1276static int omap_get_frame(struct usb_gadget *gadget) 1277{ 1278 u16 sof = UDC_SOF_REG; 1279 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; 1280} 1281 1282static int omap_wakeup(struct usb_gadget *gadget) 1283{ 1284 struct omap_udc *udc; 1285 unsigned long flags; 1286 int retval = -EHOSTUNREACH; 1287 1288 udc = container_of(gadget, struct omap_udc, gadget); 1289 1290 spin_lock_irqsave(&udc->lock, flags); 1291 if (udc->devstat & UDC_SUS) { 1292 /* NOTE: OTG spec erratum says that OTG devices may 1293 * issue wakeups without host enable. 1294 */ 1295 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { 1296 DBG("remote wakeup...\n"); 1297 UDC_SYSCON2_REG = UDC_RMT_WKP; 1298 retval = 0; 1299 } 1300 1301 /* NOTE: non-OTG systems may use SRP TOO... */ 1302 } else if (!(udc->devstat & UDC_ATT)) { 1303 if (udc->transceiver) 1304 retval = otg_start_srp(udc->transceiver); 1305 } 1306 spin_unlock_irqrestore(&udc->lock, flags); 1307 1308 return retval; 1309} 1310 1311static int 1312omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) 1313{ 1314 struct omap_udc *udc; 1315 unsigned long flags; 1316 u16 syscon1; 1317 1318 udc = container_of(gadget, struct omap_udc, gadget); 1319 spin_lock_irqsave(&udc->lock, flags); 1320 syscon1 = UDC_SYSCON1_REG; 1321 if (is_selfpowered) 1322 syscon1 |= UDC_SELF_PWR; 1323 else 1324 syscon1 &= ~UDC_SELF_PWR; 1325 UDC_SYSCON1_REG = syscon1; 1326 spin_unlock_irqrestore(&udc->lock, flags); 1327 1328 return 0; 1329} 1330 1331static int can_pullup(struct omap_udc *udc) 1332{ 1333 return udc->driver && udc->softconnect && udc->vbus_active; 1334} 1335 1336static void pullup_enable(struct omap_udc *udc) 1337{ 1338 udc->gadget.dev.parent->power.power_state = PMSG_ON; 1339 udc->gadget.dev.power.power_state = PMSG_ON; 1340 UDC_SYSCON1_REG |= UDC_PULLUP_EN; 1341#ifndef CONFIG_USB_OTG 1342 if (!cpu_is_omap15xx()) 1343 OTG_CTRL_REG |= OTG_BSESSVLD; 1344#endif 1345 UDC_IRQ_EN_REG = UDC_DS_CHG_IE; 1346} 1347 1348static void pullup_disable(struct omap_udc *udc) 1349{ 1350#ifndef CONFIG_USB_OTG 1351 if (!cpu_is_omap15xx()) 1352 OTG_CTRL_REG &= ~OTG_BSESSVLD; 1353#endif 1354 UDC_IRQ_EN_REG = UDC_DS_CHG_IE; 1355 UDC_SYSCON1_REG &= ~UDC_PULLUP_EN; 1356} 1357 1358static struct omap_udc *udc; 1359 1360static void omap_udc_enable_clock(int enable) 1361{ 1362 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL) 1363 return; 1364 1365 if (enable) { 1366 clk_enable(udc->dc_clk); 1367 clk_enable(udc->hhc_clk); 1368 udelay(100); 1369 } else { 1370 clk_disable(udc->hhc_clk); 1371 clk_disable(udc->dc_clk); 1372 } 1373} 1374 1375/* 1376 * Called by whatever detects VBUS sessions: external transceiver 1377 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock. 1378 */ 1379static int omap_vbus_session(struct usb_gadget *gadget, int is_active) 1380{ 1381 struct omap_udc *udc; 1382 unsigned long flags; 1383 1384 udc = container_of(gadget, struct omap_udc, gadget); 1385 spin_lock_irqsave(&udc->lock, flags); 1386 VDBG("VBUS %s\n", is_active ? "on" : "off"); 1387 udc->vbus_active = (is_active != 0); 1388 if (cpu_is_omap15xx()) { 1389 /* "software" detect, ignored if !VBUS_MODE_1510 */ 1390 if (is_active) 1391 FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510; 1392 else 1393 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; 1394 } 1395 if (udc->dc_clk != NULL && is_active) { 1396 if (!udc->clk_requested) { 1397 omap_udc_enable_clock(1); 1398 udc->clk_requested = 1; 1399 } 1400 } 1401 if (can_pullup(udc)) 1402 pullup_enable(udc); 1403 else 1404 pullup_disable(udc); 1405 if (udc->dc_clk != NULL && !is_active) { 1406 if (udc->clk_requested) { 1407 omap_udc_enable_clock(0); 1408 udc->clk_requested = 0; 1409 } 1410 } 1411 spin_unlock_irqrestore(&udc->lock, flags); 1412 return 0; 1413} 1414 1415static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1416{ 1417 struct omap_udc *udc; 1418 1419 udc = container_of(gadget, struct omap_udc, gadget); 1420 if (udc->transceiver) 1421 return otg_set_power(udc->transceiver, mA); 1422 return -EOPNOTSUPP; 1423} 1424 1425static int omap_pullup(struct usb_gadget *gadget, int is_on) 1426{ 1427 struct omap_udc *udc; 1428 unsigned long flags; 1429 1430 udc = container_of(gadget, struct omap_udc, gadget); 1431 spin_lock_irqsave(&udc->lock, flags); 1432 udc->softconnect = (is_on != 0); 1433 if (can_pullup(udc)) 1434 pullup_enable(udc); 1435 else 1436 pullup_disable(udc); 1437 spin_unlock_irqrestore(&udc->lock, flags); 1438 return 0; 1439} 1440 1441static struct usb_gadget_ops omap_gadget_ops = { 1442 .get_frame = omap_get_frame, 1443 .wakeup = omap_wakeup, 1444 .set_selfpowered = omap_set_selfpowered, 1445 .vbus_session = omap_vbus_session, 1446 .vbus_draw = omap_vbus_draw, 1447 .pullup = omap_pullup, 1448}; 1449 1450/*-------------------------------------------------------------------------*/ 1451 1452/* dequeue ALL requests; caller holds udc->lock */ 1453static void nuke(struct omap_ep *ep, int status) 1454{ 1455 struct omap_req *req; 1456 1457 ep->stopped = 1; 1458 1459 if (use_dma && ep->dma_channel) 1460 dma_channel_release(ep); 1461 1462 use_ep(ep, 0); 1463 UDC_CTRL_REG = UDC_CLR_EP; 1464 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) 1465 UDC_CTRL_REG = UDC_SET_HALT; 1466 1467 while (!list_empty(&ep->queue)) { 1468 req = list_entry(ep->queue.next, struct omap_req, queue); 1469 done(ep, req, status); 1470 } 1471} 1472 1473/* caller holds udc->lock */ 1474static void udc_quiesce(struct omap_udc *udc) 1475{ 1476 struct omap_ep *ep; 1477 1478 udc->gadget.speed = USB_SPEED_UNKNOWN; 1479 nuke(&udc->ep[0], -ESHUTDOWN); 1480 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) 1481 nuke(ep, -ESHUTDOWN); 1482} 1483 1484/*-------------------------------------------------------------------------*/ 1485 1486static void update_otg(struct omap_udc *udc) 1487{ 1488 u16 devstat; 1489 1490 if (!udc->gadget.is_otg) 1491 return; 1492 1493 if (OTG_CTRL_REG & OTG_ID) 1494 devstat = UDC_DEVSTAT_REG; 1495 else 1496 devstat = 0; 1497 1498 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE); 1499 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT); 1500 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT); 1501 1502 /* Enable HNP early, avoiding races on suspend irq path. 1503 * ASSUMES OTG state machine B_BUS_REQ input is true. 1504 */ 1505 if (udc->gadget.b_hnp_enable) 1506 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ) 1507 & ~OTG_PULLUP; 1508} 1509 1510static void ep0_irq(struct omap_udc *udc, u16 irq_src) 1511{ 1512 struct omap_ep *ep0 = &udc->ep[0]; 1513 struct omap_req *req = NULL; 1514 1515 ep0->irqs++; 1516 1517 /* Clear any pending requests and then scrub any rx/tx state 1518 * before starting to handle the SETUP request. 1519 */ 1520 if (irq_src & UDC_SETUP) { 1521 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX); 1522 1523 nuke(ep0, 0); 1524 if (ack) { 1525 UDC_IRQ_SRC_REG = ack; 1526 irq_src = UDC_SETUP; 1527 } 1528 } 1529 1530 /* IN/OUT packets mean we're in the DATA or STATUS stage. 1531 * This driver uses only uses protocol stalls (ep0 never halts), 1532 * and if we got this far the gadget driver already had a 1533 * chance to stall. Tries to be forgiving of host oddities. 1534 * 1535 * NOTE: the last chance gadget drivers have to stall control 1536 * requests is during their request completion callback. 1537 */ 1538 if (!list_empty(&ep0->queue)) 1539 req = container_of(ep0->queue.next, struct omap_req, queue); 1540 1541 /* IN == TX to host */ 1542 if (irq_src & UDC_EP0_TX) { 1543 int stat; 1544 1545 UDC_IRQ_SRC_REG = UDC_EP0_TX; 1546 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1547 stat = UDC_STAT_FLG_REG; 1548 if (stat & UDC_ACK) { 1549 if (udc->ep0_in) { 1550 /* write next IN packet from response, 1551 * or set up the status stage. 1552 */ 1553 if (req) 1554 stat = write_fifo(ep0, req); 1555 UDC_EP_NUM_REG = UDC_EP_DIR; 1556 if (!req && udc->ep0_pending) { 1557 UDC_EP_NUM_REG = UDC_EP_SEL; 1558 UDC_CTRL_REG = UDC_CLR_EP; 1559 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1560 UDC_EP_NUM_REG = 0; 1561 udc->ep0_pending = 0; 1562 } /* else: 6 wait states before it'll tx */ 1563 } else { 1564 /* ack status stage of OUT transfer */ 1565 UDC_EP_NUM_REG = UDC_EP_DIR; 1566 if (req) 1567 done(ep0, req, 0); 1568 } 1569 req = NULL; 1570 } else if (stat & UDC_STALL) { 1571 UDC_CTRL_REG = UDC_CLR_HALT; 1572 UDC_EP_NUM_REG = UDC_EP_DIR; 1573 } else { 1574 UDC_EP_NUM_REG = UDC_EP_DIR; 1575 } 1576 } 1577 1578 /* OUT == RX from host */ 1579 if (irq_src & UDC_EP0_RX) { 1580 int stat; 1581 1582 UDC_IRQ_SRC_REG = UDC_EP0_RX; 1583 UDC_EP_NUM_REG = UDC_EP_SEL; 1584 stat = UDC_STAT_FLG_REG; 1585 if (stat & UDC_ACK) { 1586 if (!udc->ep0_in) { 1587 stat = 0; 1588 /* read next OUT packet of request, maybe 1589 * reactiviting the fifo; stall on errors. 1590 */ 1591 if (!req || (stat = read_fifo(ep0, req)) < 0) { 1592 UDC_SYSCON2_REG = UDC_STALL_CMD; 1593 udc->ep0_pending = 0; 1594 stat = 0; 1595 } else if (stat == 0) 1596 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1597 UDC_EP_NUM_REG = 0; 1598 1599 /* activate status stage */ 1600 if (stat == 1) { 1601 done(ep0, req, 0); 1602 /* that may have STALLed ep0... */ 1603 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1604 UDC_CTRL_REG = UDC_CLR_EP; 1605 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1606 UDC_EP_NUM_REG = UDC_EP_DIR; 1607 udc->ep0_pending = 0; 1608 } 1609 } else { 1610 /* ack status stage of IN transfer */ 1611 UDC_EP_NUM_REG = 0; 1612 if (req) 1613 done(ep0, req, 0); 1614 } 1615 } else if (stat & UDC_STALL) { 1616 UDC_CTRL_REG = UDC_CLR_HALT; 1617 UDC_EP_NUM_REG = 0; 1618 } else { 1619 UDC_EP_NUM_REG = 0; 1620 } 1621 } 1622 1623 /* SETUP starts all control transfers */ 1624 if (irq_src & UDC_SETUP) { 1625 union u { 1626 u16 word[4]; 1627 struct usb_ctrlrequest r; 1628 } u; 1629 int status = -EINVAL; 1630 struct omap_ep *ep; 1631 1632 /* read the (latest) SETUP message */ 1633 do { 1634 UDC_EP_NUM_REG = UDC_SETUP_SEL; 1635 /* two bytes at a time */ 1636 u.word[0] = UDC_DATA_REG; 1637 u.word[1] = UDC_DATA_REG; 1638 u.word[2] = UDC_DATA_REG; 1639 u.word[3] = UDC_DATA_REG; 1640 UDC_EP_NUM_REG = 0; 1641 } while (UDC_IRQ_SRC_REG & UDC_SETUP); 1642 1643#define w_value le16_to_cpu(u.r.wValue) 1644#define w_index le16_to_cpu(u.r.wIndex) 1645#define w_length le16_to_cpu(u.r.wLength) 1646 1647 /* Delegate almost all control requests to the gadget driver, 1648 * except for a handful of ch9 status/feature requests that 1649 * hardware doesn't autodecode _and_ the gadget API hides. 1650 */ 1651 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0; 1652 udc->ep0_set_config = 0; 1653 udc->ep0_pending = 1; 1654 ep0->stopped = 0; 1655 ep0->ackwait = 0; 1656 switch (u.r.bRequest) { 1657 case USB_REQ_SET_CONFIGURATION: 1658 /* udc needs to know when ep != 0 is valid */ 1659 if (u.r.bRequestType != USB_RECIP_DEVICE) 1660 goto delegate; 1661 if (w_length != 0) 1662 goto do_stall; 1663 udc->ep0_set_config = 1; 1664 udc->ep0_reset_config = (w_value == 0); 1665 VDBG("set config %d\n", w_value); 1666 1667 /* update udc NOW since gadget driver may start 1668 * queueing requests immediately; clear config 1669 * later if it fails the request. 1670 */ 1671 if (udc->ep0_reset_config) 1672 UDC_SYSCON2_REG = UDC_CLR_CFG; 1673 else 1674 UDC_SYSCON2_REG = UDC_DEV_CFG; 1675 update_otg(udc); 1676 goto delegate; 1677 case USB_REQ_CLEAR_FEATURE: 1678 /* clear endpoint halt */ 1679 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1680 goto delegate; 1681 if (w_value != USB_ENDPOINT_HALT 1682 || w_length != 0) 1683 goto do_stall; 1684 ep = &udc->ep[w_index & 0xf]; 1685 if (ep != ep0) { 1686 if (w_index & USB_DIR_IN) 1687 ep += 16; 1688 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1689 || !ep->desc) 1690 goto do_stall; 1691 use_ep(ep, 0); 1692 UDC_CTRL_REG = udc->clr_halt; 1693 ep->ackwait = 0; 1694 if (!(ep->bEndpointAddress & USB_DIR_IN)) { 1695 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1696 ep->ackwait = 1 + ep->double_buf; 1697 } 1698 /* NOTE: assumes the host behaves sanely, 1699 * only clearing real halts. Else we may 1700 * need to kill pending transfers and then 1701 * restart the queue... very messy for DMA! 1702 */ 1703 } 1704 VDBG("%s halt cleared by host\n", ep->name); 1705 goto ep0out_status_stage; 1706 case USB_REQ_SET_FEATURE: 1707 /* set endpoint halt */ 1708 if (u.r.bRequestType != USB_RECIP_ENDPOINT) 1709 goto delegate; 1710 if (w_value != USB_ENDPOINT_HALT 1711 || w_length != 0) 1712 goto do_stall; 1713 ep = &udc->ep[w_index & 0xf]; 1714 if (w_index & USB_DIR_IN) 1715 ep += 16; 1716 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC 1717 || ep == ep0 || !ep->desc) 1718 goto do_stall; 1719 if (use_dma && ep->has_dma) { 1720 /* this has rude side-effects (aborts) and 1721 * can't really work if DMA-IN is active 1722 */ 1723 DBG("%s host set_halt, NYET \n", ep->name); 1724 goto do_stall; 1725 } 1726 use_ep(ep, 0); 1727 /* can't halt if fifo isn't empty... */ 1728 UDC_CTRL_REG = UDC_CLR_EP; 1729 UDC_CTRL_REG = UDC_SET_HALT; 1730 VDBG("%s halted by host\n", ep->name); 1731ep0out_status_stage: 1732 status = 0; 1733 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1734 UDC_CTRL_REG = UDC_CLR_EP; 1735 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1736 UDC_EP_NUM_REG = UDC_EP_DIR; 1737 udc->ep0_pending = 0; 1738 break; 1739 case USB_REQ_GET_STATUS: 1740 /* USB_ENDPOINT_HALT status? */ 1741 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT)) 1742 goto intf_status; 1743 1744 /* ep0 never stalls */ 1745 if (!(w_index & 0xf)) 1746 goto zero_status; 1747 1748 /* only active endpoints count */ 1749 ep = &udc->ep[w_index & 0xf]; 1750 if (w_index & USB_DIR_IN) 1751 ep += 16; 1752 if (!ep->desc) 1753 goto do_stall; 1754 1755 /* iso never stalls */ 1756 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 1757 goto zero_status; 1758 1759 ERR("%s status, can't report\n", ep->ep.name); 1760 goto do_stall; 1761 1762intf_status: 1763 /* return interface status. if we were pedantic, 1764 * we'd detect non-existent interfaces, and stall. 1765 */ 1766 if (u.r.bRequestType 1767 != (USB_DIR_IN|USB_RECIP_INTERFACE)) 1768 goto delegate; 1769 1770zero_status: 1771 /* return two zero bytes */ 1772 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; 1773 UDC_DATA_REG = 0; 1774 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1775 UDC_EP_NUM_REG = UDC_EP_DIR; 1776 status = 0; 1777 VDBG("GET_STATUS, interface %d\n", w_index); 1778 /* next, status stage */ 1779 break; 1780 default: 1781delegate: 1782 /* activate the ep0out fifo right away */ 1783 if (!udc->ep0_in && w_length) { 1784 UDC_EP_NUM_REG = 0; 1785 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1786 } 1787 1788 /* gadget drivers see class/vendor specific requests, 1789 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, 1790 * and more 1791 */ 1792 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", 1793 u.r.bRequestType, u.r.bRequest, 1794 w_value, w_index, w_length); 1795 1796#undef w_value 1797#undef w_index 1798#undef w_length 1799 1800 /* The gadget driver may return an error here, 1801 * causing an immediate protocol stall. 1802 * 1803 * Else it must issue a response, either queueing a 1804 * response buffer for the DATA stage, or halting ep0 1805 * (causing a protocol stall, not a real halt). A 1806 * zero length buffer means no DATA stage. 1807 * 1808 * It's fine to issue that response after the setup() 1809 * call returns, and this IRQ was handled. 1810 */ 1811 udc->ep0_setup = 1; 1812 spin_unlock(&udc->lock); 1813 status = udc->driver->setup (&udc->gadget, &u.r); 1814 spin_lock(&udc->lock); 1815 udc->ep0_setup = 0; 1816 } 1817 1818 if (status < 0) { 1819do_stall: 1820 VDBG("req %02x.%02x protocol STALL; stat %d\n", 1821 u.r.bRequestType, u.r.bRequest, status); 1822 if (udc->ep0_set_config) { 1823 if (udc->ep0_reset_config) 1824 WARN("error resetting config?\n"); 1825 else 1826 UDC_SYSCON2_REG = UDC_CLR_CFG; 1827 } 1828 UDC_SYSCON2_REG = UDC_STALL_CMD; 1829 udc->ep0_pending = 0; 1830 } 1831 } 1832} 1833 1834/*-------------------------------------------------------------------------*/ 1835 1836#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT) 1837 1838static void devstate_irq(struct omap_udc *udc, u16 irq_src) 1839{ 1840 u16 devstat, change; 1841 1842 devstat = UDC_DEVSTAT_REG; 1843 change = devstat ^ udc->devstat; 1844 udc->devstat = devstat; 1845 1846 if (change & (UDC_USB_RESET|UDC_ATT)) { 1847 udc_quiesce(udc); 1848 1849 if (change & UDC_ATT) { 1850 /* driver for any external transceiver will 1851 * have called omap_vbus_session() already 1852 */ 1853 if (devstat & UDC_ATT) { 1854 udc->gadget.speed = USB_SPEED_FULL; 1855 VDBG("connect\n"); 1856 if (!udc->transceiver) 1857 pullup_enable(udc); 1858 // if (driver->connect) call it 1859 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) { 1860 udc->gadget.speed = USB_SPEED_UNKNOWN; 1861 if (!udc->transceiver) 1862 pullup_disable(udc); 1863 DBG("disconnect, gadget %s\n", 1864 udc->driver->driver.name); 1865 if (udc->driver->disconnect) { 1866 spin_unlock(&udc->lock); 1867 udc->driver->disconnect(&udc->gadget); 1868 spin_lock(&udc->lock); 1869 } 1870 } 1871 change &= ~UDC_ATT; 1872 } 1873 1874 if (change & UDC_USB_RESET) { 1875 if (devstat & UDC_USB_RESET) { 1876 VDBG("RESET=1\n"); 1877 } else { 1878 udc->gadget.speed = USB_SPEED_FULL; 1879 INFO("USB reset done, gadget %s\n", 1880 udc->driver->driver.name); 1881 /* ep0 traffic is legal from now on */ 1882 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE; 1883 } 1884 change &= ~UDC_USB_RESET; 1885 } 1886 } 1887 if (change & UDC_SUS) { 1888 if (udc->gadget.speed != USB_SPEED_UNKNOWN) { 1889 if (devstat & UDC_SUS) { 1890 VDBG("suspend\n"); 1891 update_otg(udc); 1892 /* HNP could be under way already */ 1893 if (udc->gadget.speed == USB_SPEED_FULL 1894 && udc->driver->suspend) { 1895 spin_unlock(&udc->lock); 1896 udc->driver->suspend(&udc->gadget); 1897 spin_lock(&udc->lock); 1898 } 1899 if (udc->transceiver) 1900 otg_set_suspend(udc->transceiver, 1); 1901 } else { 1902 VDBG("resume\n"); 1903 if (udc->transceiver) 1904 otg_set_suspend(udc->transceiver, 0); 1905 if (udc->gadget.speed == USB_SPEED_FULL 1906 && udc->driver->resume) { 1907 spin_unlock(&udc->lock); 1908 udc->driver->resume(&udc->gadget); 1909 spin_lock(&udc->lock); 1910 } 1911 } 1912 } 1913 change &= ~UDC_SUS; 1914 } 1915 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) { 1916 update_otg(udc); 1917 change &= ~OTG_FLAGS; 1918 } 1919 1920 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD); 1921 if (change) 1922 VDBG("devstat %03x, ignore change %03x\n", 1923 devstat, change); 1924 1925 UDC_IRQ_SRC_REG = UDC_DS_CHG; 1926} 1927 1928static irqreturn_t omap_udc_irq(int irq, void *_udc) 1929{ 1930 struct omap_udc *udc = _udc; 1931 u16 irq_src; 1932 irqreturn_t status = IRQ_NONE; 1933 unsigned long flags; 1934 1935 spin_lock_irqsave(&udc->lock, flags); 1936 irq_src = UDC_IRQ_SRC_REG; 1937 1938 /* Device state change (usb ch9 stuff) */ 1939 if (irq_src & UDC_DS_CHG) { 1940 devstate_irq(_udc, irq_src); 1941 status = IRQ_HANDLED; 1942 irq_src &= ~UDC_DS_CHG; 1943 } 1944 1945 /* EP0 control transfers */ 1946 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) { 1947 ep0_irq(_udc, irq_src); 1948 status = IRQ_HANDLED; 1949 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX); 1950 } 1951 1952 /* DMA transfer completion */ 1953 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) { 1954 dma_irq(_udc, irq_src); 1955 status = IRQ_HANDLED; 1956 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); 1957 } 1958 1959 irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX); 1960 if (irq_src) 1961 DBG("udc_irq, unhandled %03x\n", irq_src); 1962 spin_unlock_irqrestore(&udc->lock, flags); 1963 1964 return status; 1965} 1966 1967#define PIO_OUT_TIMEOUT (jiffies + HZ/3) 1968#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY))) 1969 1970static void pio_out_timer(unsigned long _ep) 1971{ 1972 struct omap_ep *ep = (void *) _ep; 1973 unsigned long flags; 1974 u16 stat_flg; 1975 1976 spin_lock_irqsave(&ep->udc->lock, flags); 1977 if (!list_empty(&ep->queue) && ep->ackwait) { 1978 use_ep(ep, UDC_EP_SEL); 1979 stat_flg = UDC_STAT_FLG_REG; 1980 1981 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) 1982 || (ep->double_buf && HALF_FULL(stat_flg)))) { 1983 struct omap_req *req; 1984 1985 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg); 1986 req = container_of(ep->queue.next, 1987 struct omap_req, queue); 1988 (void) read_fifo(ep, req); 1989 UDC_EP_NUM_REG = ep->bEndpointAddress; 1990 UDC_CTRL_REG = UDC_SET_FIFO_EN; 1991 ep->ackwait = 1 + ep->double_buf; 1992 } else 1993 deselect_ep(); 1994 } 1995 mod_timer(&ep->timer, PIO_OUT_TIMEOUT); 1996 spin_unlock_irqrestore(&ep->udc->lock, flags); 1997} 1998 1999static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) 2000{ 2001 u16 epn_stat, irq_src; 2002 irqreturn_t status = IRQ_NONE; 2003 struct omap_ep *ep; 2004 int epnum; 2005 struct omap_udc *udc = _dev; 2006 struct omap_req *req; 2007 unsigned long flags; 2008 2009 spin_lock_irqsave(&udc->lock, flags); 2010 epn_stat = UDC_EPN_STAT_REG; 2011 irq_src = UDC_IRQ_SRC_REG; 2012 2013 /* handle OUT first, to avoid some wasteful NAKs */ 2014 if (irq_src & UDC_EPN_RX) { 2015 epnum = (epn_stat >> 8) & 0x0f; 2016 UDC_IRQ_SRC_REG = UDC_EPN_RX; 2017 status = IRQ_HANDLED; 2018 ep = &udc->ep[epnum]; 2019 ep->irqs++; 2020 2021 UDC_EP_NUM_REG = epnum | UDC_EP_SEL; 2022 ep->fnf = 0; 2023 if ((UDC_STAT_FLG_REG & UDC_ACK)) { 2024 ep->ackwait--; 2025 if (!list_empty(&ep->queue)) { 2026 int stat; 2027 req = container_of(ep->queue.next, 2028 struct omap_req, queue); 2029 stat = read_fifo(ep, req); 2030 if (!ep->double_buf) 2031 ep->fnf = 1; 2032 } 2033 } 2034 /* min 6 clock delay before clearing EP_SEL ... */ 2035 epn_stat = UDC_EPN_STAT_REG; 2036 epn_stat = UDC_EPN_STAT_REG; 2037 UDC_EP_NUM_REG = epnum; 2038 2039 /* enabling fifo _after_ clearing ACK, contrary to docs, 2040 * reduces lossage; timer still needed though (sigh). 2041 */ 2042 if (ep->fnf) { 2043 UDC_CTRL_REG = UDC_SET_FIFO_EN; 2044 ep->ackwait = 1 + ep->double_buf; 2045 } 2046 mod_timer(&ep->timer, PIO_OUT_TIMEOUT); 2047 } 2048 2049 /* then IN transfers */ 2050 else if (irq_src & UDC_EPN_TX) { 2051 epnum = epn_stat & 0x0f; 2052 UDC_IRQ_SRC_REG = UDC_EPN_TX; 2053 status = IRQ_HANDLED; 2054 ep = &udc->ep[16 + epnum]; 2055 ep->irqs++; 2056 2057 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL; 2058 if ((UDC_STAT_FLG_REG & UDC_ACK)) { 2059 ep->ackwait = 0; 2060 if (!list_empty(&ep->queue)) { 2061 req = container_of(ep->queue.next, 2062 struct omap_req, queue); 2063 (void) write_fifo(ep, req); 2064 } 2065 } 2066 /* min 6 clock delay before clearing EP_SEL ... */ 2067 epn_stat = UDC_EPN_STAT_REG; 2068 epn_stat = UDC_EPN_STAT_REG; 2069 UDC_EP_NUM_REG = epnum | UDC_EP_DIR; 2070 /* then 6 clocks before it'd tx */ 2071 } 2072 2073 spin_unlock_irqrestore(&udc->lock, flags); 2074 return status; 2075} 2076 2077#ifdef USE_ISO 2078static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) 2079{ 2080 struct omap_udc *udc = _dev; 2081 struct omap_ep *ep; 2082 int pending = 0; 2083 unsigned long flags; 2084 2085 spin_lock_irqsave(&udc->lock, flags); 2086 2087 /* handle all non-DMA ISO transfers */ 2088 list_for_each_entry (ep, &udc->iso, iso) { 2089 u16 stat; 2090 struct omap_req *req; 2091 2092 if (ep->has_dma || list_empty(&ep->queue)) 2093 continue; 2094 req = list_entry(ep->queue.next, struct omap_req, queue); 2095 2096 use_ep(ep, UDC_EP_SEL); 2097 stat = UDC_STAT_FLG_REG; 2098 2099 /* NOTE: like the other controller drivers, this isn't 2100 * currently reporting lost or damaged frames. 2101 */ 2102 if (ep->bEndpointAddress & USB_DIR_IN) { 2103 if (stat & UDC_MISS_IN) 2104 /* done(ep, req, -EPROTO) */; 2105 else 2106 write_fifo(ep, req); 2107 } else { 2108 int status = 0; 2109 2110 if (stat & UDC_NO_RXPACKET) 2111 status = -EREMOTEIO; 2112 else if (stat & UDC_ISO_ERR) 2113 status = -EILSEQ; 2114 else if (stat & UDC_DATA_FLUSH) 2115 status = -ENOSR; 2116 2117 if (status) 2118 /* done(ep, req, status) */; 2119 else 2120 read_fifo(ep, req); 2121 } 2122 deselect_ep(); 2123 /* 6 wait states before next EP */ 2124 2125 ep->irqs++; 2126 if (!list_empty(&ep->queue)) 2127 pending = 1; 2128 } 2129 if (!pending) 2130 UDC_IRQ_EN_REG &= ~UDC_SOF_IE; 2131 UDC_IRQ_SRC_REG = UDC_SOF; 2132 2133 spin_unlock_irqrestore(&udc->lock, flags); 2134 return IRQ_HANDLED; 2135} 2136#endif 2137 2138/*-------------------------------------------------------------------------*/ 2139 2140static inline int machine_without_vbus_sense(void) 2141{ 2142 return (machine_is_omap_innovator() 2143 || machine_is_omap_osk() 2144 || machine_is_omap_apollon() 2145#ifndef CONFIG_MACH_OMAP_H4_OTG 2146 || machine_is_omap_h4() 2147#endif 2148 || machine_is_sx1() 2149 ); 2150} 2151 2152int usb_gadget_register_driver (struct usb_gadget_driver *driver) 2153{ 2154 int status = -ENODEV; 2155 struct omap_ep *ep; 2156 unsigned long flags; 2157 2158 /* basic sanity tests */ 2159 if (!udc) 2160 return -ENODEV; 2161 if (!driver 2162 || driver->speed < USB_SPEED_FULL 2163 || !driver->bind 2164 || !driver->setup) 2165 return -EINVAL; 2166 2167 spin_lock_irqsave(&udc->lock, flags); 2168 if (udc->driver) { 2169 spin_unlock_irqrestore(&udc->lock, flags); 2170 return -EBUSY; 2171 } 2172 2173 /* reset state */ 2174 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) { 2175 ep->irqs = 0; 2176 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) 2177 continue; 2178 use_ep(ep, 0); 2179 UDC_CTRL_REG = UDC_SET_HALT; 2180 } 2181 udc->ep0_pending = 0; 2182 udc->ep[0].irqs = 0; 2183 udc->softconnect = 1; 2184 2185 /* hook up the driver */ 2186 driver->driver.bus = NULL; 2187 udc->driver = driver; 2188 udc->gadget.dev.driver = &driver->driver; 2189 spin_unlock_irqrestore(&udc->lock, flags); 2190 2191 if (udc->dc_clk != NULL) 2192 omap_udc_enable_clock(1); 2193 2194 status = driver->bind (&udc->gadget); 2195 if (status) { 2196 DBG("bind to %s --> %d\n", driver->driver.name, status); 2197 udc->gadget.dev.driver = NULL; 2198 udc->driver = NULL; 2199 goto done; 2200 } 2201 DBG("bound to driver %s\n", driver->driver.name); 2202 2203 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; 2204 2205 /* connect to bus through transceiver */ 2206 if (udc->transceiver) { 2207 status = otg_set_peripheral(udc->transceiver, &udc->gadget); 2208 if (status < 0) { 2209 ERR("can't bind to transceiver\n"); 2210 if (driver->unbind) { 2211 driver->unbind (&udc->gadget); 2212 udc->gadget.dev.driver = NULL; 2213 udc->driver = NULL; 2214 } 2215 goto done; 2216 } 2217 } else { 2218 if (can_pullup(udc)) 2219 pullup_enable (udc); 2220 else 2221 pullup_disable (udc); 2222 } 2223 2224 /* boards that don't have VBUS sensing can't autogate 48MHz; 2225 * can't enter deep sleep while a gadget driver is active. 2226 */ 2227 if (machine_without_vbus_sense()) 2228 omap_vbus_session(&udc->gadget, 1); 2229 2230done: 2231 if (udc->dc_clk != NULL) 2232 omap_udc_enable_clock(0); 2233 return status; 2234} 2235EXPORT_SYMBOL(usb_gadget_register_driver); 2236 2237int usb_gadget_unregister_driver (struct usb_gadget_driver *driver) 2238{ 2239 unsigned long flags; 2240 int status = -ENODEV; 2241 2242 if (!udc) 2243 return -ENODEV; 2244 if (!driver || driver != udc->driver || !driver->unbind) 2245 return -EINVAL; 2246 2247 if (udc->dc_clk != NULL) 2248 omap_udc_enable_clock(1); 2249 2250 if (machine_without_vbus_sense()) 2251 omap_vbus_session(&udc->gadget, 0); 2252 2253 if (udc->transceiver) 2254 (void) otg_set_peripheral(udc->transceiver, NULL); 2255 else 2256 pullup_disable(udc); 2257 2258 spin_lock_irqsave(&udc->lock, flags); 2259 udc_quiesce(udc); 2260 spin_unlock_irqrestore(&udc->lock, flags); 2261 2262 driver->unbind(&udc->gadget); 2263 udc->gadget.dev.driver = NULL; 2264 udc->driver = NULL; 2265 2266 if (udc->dc_clk != NULL) 2267 omap_udc_enable_clock(0); 2268 DBG("unregistered driver '%s'\n", driver->driver.name); 2269 return status; 2270} 2271EXPORT_SYMBOL(usb_gadget_unregister_driver); 2272 2273 2274/*-------------------------------------------------------------------------*/ 2275 2276#ifdef CONFIG_USB_GADGET_DEBUG_FILES 2277 2278#include <linux/seq_file.h> 2279 2280static const char proc_filename[] = "driver/udc"; 2281 2282#define FOURBITS "%s%s%s%s" 2283#define EIGHTBITS FOURBITS FOURBITS 2284 2285static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) 2286{ 2287 u16 stat_flg; 2288 struct omap_req *req; 2289 char buf[20]; 2290 2291 use_ep(ep, 0); 2292 2293 if (use_dma && ep->has_dma) 2294 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ", 2295 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', 2296 ep->dma_channel - 1, ep->lch); 2297 else 2298 buf[0] = 0; 2299 2300 stat_flg = UDC_STAT_FLG_REG; 2301 seq_printf(s, 2302 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", 2303 ep->name, buf, 2304 ep->double_buf ? "dbuf " : "", 2305 ({char *s; switch(ep->ackwait){ 2306 case 0: s = ""; break; 2307 case 1: s = "(ackw) "; break; 2308 case 2: s = "(ackw2) "; break; 2309 default: s = "(?) "; break; 2310 } s;}), 2311 ep->irqs, stat_flg, 2312 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "", 2313 (stat_flg & UDC_MISS_IN) ? "miss_in " : "", 2314 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "", 2315 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "", 2316 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "", 2317 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "", 2318 (stat_flg & UDC_EP_HALTED) ? "HALT " : "", 2319 (stat_flg & UDC_STALL) ? "STALL " : "", 2320 (stat_flg & UDC_NAK) ? "NAK " : "", 2321 (stat_flg & UDC_ACK) ? "ACK " : "", 2322 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "", 2323 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "", 2324 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : ""); 2325 2326 if (list_empty (&ep->queue)) 2327 seq_printf(s, "\t(queue empty)\n"); 2328 else 2329 list_for_each_entry (req, &ep->queue, queue) { 2330 unsigned length = req->req.actual; 2331 2332 if (use_dma && buf[0]) { 2333 length += ((ep->bEndpointAddress & USB_DIR_IN) 2334 ? dma_src_len : dma_dest_len) 2335 (ep, req->req.dma + length); 2336 buf[0] = 0; 2337 } 2338 seq_printf(s, "\treq %p len %d/%d buf %p\n", 2339 &req->req, length, 2340 req->req.length, req->req.buf); 2341 } 2342} 2343 2344static char *trx_mode(unsigned m, int enabled) 2345{ 2346 switch (m) { 2347 case 0: return enabled ? "*6wire" : "unused"; 2348 case 1: return "4wire"; 2349 case 2: return "3wire"; 2350 case 3: return "6wire"; 2351 default: return "unknown"; 2352 } 2353} 2354 2355static int proc_otg_show(struct seq_file *s) 2356{ 2357 u32 tmp; 2358 u32 trans; 2359 char *ctrl_name; 2360 2361 tmp = OTG_REV_REG; 2362 if (cpu_is_omap24xx()) { 2363 ctrl_name = "control_devconf"; 2364 trans = CONTROL_DEVCONF_REG; 2365 } else { 2366 ctrl_name = "tranceiver_ctrl"; 2367 trans = USB_TRANSCEIVER_CTRL_REG; 2368 } 2369 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", 2370 tmp >> 4, tmp & 0xf, ctrl_name, trans); 2371 tmp = OTG_SYSCON_1_REG; 2372 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," 2373 FOURBITS "\n", tmp, 2374 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), 2375 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R), 2376 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710()) 2377 ? "internal" 2378 : trx_mode(USB0_TRX_MODE(tmp), 1), 2379 (tmp & OTG_IDLE_EN) ? " !otg" : "", 2380 (tmp & HST_IDLE_EN) ? " !host" : "", 2381 (tmp & DEV_IDLE_EN) ? " !dev" : "", 2382 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); 2383 tmp = OTG_SYSCON_2_REG; 2384 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS 2385 " b_ase_brst=%d hmc=%d\n", tmp, 2386 (tmp & OTG_EN) ? " otg_en" : "", 2387 (tmp & USBX_SYNCHRO) ? " synchro" : "", 2388 // much more SRP stuff 2389 (tmp & SRP_DATA) ? " srp_data" : "", 2390 (tmp & SRP_VBUS) ? " srp_vbus" : "", 2391 (tmp & OTG_PADEN) ? " otg_paden" : "", 2392 (tmp & HMC_PADEN) ? " hmc_paden" : "", 2393 (tmp & UHOST_EN) ? " uhost_en" : "", 2394 (tmp & HMC_TLLSPEED) ? " tllspeed" : "", 2395 (tmp & HMC_TLLATTACH) ? " tllattach" : "", 2396 B_ASE_BRST(tmp), 2397 OTG_HMC(tmp)); 2398 tmp = OTG_CTRL_REG; 2399 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, 2400 (tmp & OTG_ASESSVLD) ? " asess" : "", 2401 (tmp & OTG_BSESSEND) ? " bsess_end" : "", 2402 (tmp & OTG_BSESSVLD) ? " bsess" : "", 2403 (tmp & OTG_VBUSVLD) ? " vbus" : "", 2404 (tmp & OTG_ID) ? " id" : "", 2405 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST", 2406 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "", 2407 (tmp & OTG_A_BUSREQ) ? " a_bus" : "", 2408 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "", 2409 (tmp & OTG_B_BUSREQ) ? " b_bus" : "", 2410 (tmp & OTG_BUSDROP) ? " busdrop" : "", 2411 (tmp & OTG_PULLDOWN) ? " down" : "", 2412 (tmp & OTG_PULLUP) ? " up" : "", 2413 (tmp & OTG_DRV_VBUS) ? " drv" : "", 2414 (tmp & OTG_PD_VBUS) ? " pd_vb" : "", 2415 (tmp & OTG_PU_VBUS) ? " pu_vb" : "", 2416 (tmp & OTG_PU_ID) ? " pu_id" : "" 2417 ); 2418 tmp = OTG_IRQ_EN_REG; 2419 seq_printf(s, "otg_irq_en %04x" "\n", tmp); 2420 tmp = OTG_IRQ_SRC_REG; 2421 seq_printf(s, "otg_irq_src %04x" "\n", tmp); 2422 tmp = OTG_OUTCTRL_REG; 2423 seq_printf(s, "otg_outctrl %04x" "\n", tmp); 2424 tmp = OTG_TEST_REG; 2425 seq_printf(s, "otg_test %04x" "\n", tmp); 2426 return 0; 2427} 2428 2429static int proc_udc_show(struct seq_file *s, void *_) 2430{ 2431 u32 tmp; 2432 struct omap_ep *ep; 2433 unsigned long flags; 2434 2435 spin_lock_irqsave(&udc->lock, flags); 2436 2437 seq_printf(s, "%s, version: " DRIVER_VERSION 2438#ifdef USE_ISO 2439 " (iso)" 2440#endif 2441 "%s\n", 2442 driver_desc, 2443 use_dma ? " (dma)" : ""); 2444 2445 tmp = UDC_REV_REG & 0xff; 2446 seq_printf(s, 2447 "UDC rev %d.%d, fifo mode %d, gadget %s\n" 2448 "hmc %d, transceiver %s\n", 2449 tmp >> 4, tmp & 0xf, 2450 fifo_mode, 2451 udc->driver ? udc->driver->driver.name : "(none)", 2452 HMC, 2453 udc->transceiver 2454 ? udc->transceiver->label 2455 : ((cpu_is_omap1710() || cpu_is_omap24xx()) 2456 ? "external" : "(none)")); 2457 if (cpu_class_is_omap1()) { 2458 seq_printf(s, "ULPD control %04x req %04x status %04x\n", 2459 __REG16(ULPD_CLOCK_CTRL), 2460 __REG16(ULPD_SOFT_REQ), 2461 __REG16(ULPD_STATUS_REQ)); 2462 } 2463 2464 /* OTG controller registers */ 2465 if (!cpu_is_omap15xx()) 2466 proc_otg_show(s); 2467 2468 tmp = UDC_SYSCON1_REG; 2469 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, 2470 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", 2471 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", 2472 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "", 2473 (tmp & UDC_NAK_EN) ? " nak" : "", 2474 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "", 2475 (tmp & UDC_SELF_PWR) ? " self_pwr" : "", 2476 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "", 2477 (tmp & UDC_PULLUP_EN) ? " PULLUP" : ""); 2478 // syscon2 is write-only 2479 2480 /* UDC controller registers */ 2481 if (!(tmp & UDC_PULLUP_EN)) { 2482 seq_printf(s, "(suspended)\n"); 2483 spin_unlock_irqrestore(&udc->lock, flags); 2484 return 0; 2485 } 2486 2487 tmp = UDC_DEVSTAT_REG; 2488 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, 2489 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", 2490 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", 2491 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "", 2492 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "", 2493 (tmp & UDC_USB_RESET) ? " usb_reset" : "", 2494 (tmp & UDC_SUS) ? " SUS" : "", 2495 (tmp & UDC_CFG) ? " CFG" : "", 2496 (tmp & UDC_ADD) ? " ADD" : "", 2497 (tmp & UDC_DEF) ? " DEF" : "", 2498 (tmp & UDC_ATT) ? " ATT" : ""); 2499 seq_printf(s, "sof %04x\n", UDC_SOF_REG); 2500 tmp = UDC_IRQ_EN_REG; 2501 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, 2502 (tmp & UDC_SOF_IE) ? " sof" : "", 2503 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", 2504 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", 2505 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", 2506 (tmp & UDC_EP0_IE) ? " ep0" : ""); 2507 tmp = UDC_IRQ_SRC_REG; 2508 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, 2509 (tmp & UDC_TXN_DONE) ? " txn_done" : "", 2510 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", 2511 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", 2512 (tmp & UDC_SOF) ? " sof" : "", 2513 (tmp & UDC_EPN_RX) ? " epn_rx" : "", 2514 (tmp & UDC_EPN_TX) ? " epn_tx" : "", 2515 (tmp & UDC_DS_CHG) ? " ds_chg" : "", 2516 (tmp & UDC_SETUP) ? " setup" : "", 2517 (tmp & UDC_EP0_RX) ? " ep0out" : "", 2518 (tmp & UDC_EP0_TX) ? " ep0in" : ""); 2519 if (use_dma) { 2520 unsigned i; 2521 2522 tmp = UDC_DMA_IRQ_EN_REG; 2523 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, 2524 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", 2525 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", 2526 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "", 2527 2528 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "", 2529 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "", 2530 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "", 2531 2532 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "", 2533 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", 2534 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); 2535 2536 tmp = UDC_RXDMA_CFG_REG; 2537 seq_printf(s, "rxdma_cfg %04x\n", tmp); 2538 if (tmp) { 2539 for (i = 0; i < 3; i++) { 2540 if ((tmp & (0x0f << (i * 4))) == 0) 2541 continue; 2542 seq_printf(s, "rxdma[%d] %04x\n", i, 2543 UDC_RXDMA_REG(i + 1)); 2544 } 2545 } 2546 tmp = UDC_TXDMA_CFG_REG; 2547 seq_printf(s, "txdma_cfg %04x\n", tmp); 2548 if (tmp) { 2549 for (i = 0; i < 3; i++) { 2550 if (!(tmp & (0x0f << (i * 4)))) 2551 continue; 2552 seq_printf(s, "txdma[%d] %04x\n", i, 2553 UDC_TXDMA_REG(i + 1)); 2554 } 2555 } 2556 } 2557 2558 tmp = UDC_DEVSTAT_REG; 2559 if (tmp & UDC_ATT) { 2560 proc_ep_show(s, &udc->ep[0]); 2561 if (tmp & UDC_ADD) { 2562 list_for_each_entry (ep, &udc->gadget.ep_list, 2563 ep.ep_list) { 2564 if (ep->desc) 2565 proc_ep_show(s, ep); 2566 } 2567 } 2568 } 2569 spin_unlock_irqrestore(&udc->lock, flags); 2570 return 0; 2571} 2572 2573static int proc_udc_open(struct inode *inode, struct file *file) 2574{ 2575 return single_open(file, proc_udc_show, NULL); 2576} 2577 2578static const struct file_operations proc_ops = { 2579 .open = proc_udc_open, 2580 .read = seq_read, 2581 .llseek = seq_lseek, 2582 .release = single_release, 2583}; 2584 2585static void create_proc_file(void) 2586{ 2587 struct proc_dir_entry *pde; 2588 2589 pde = create_proc_entry (proc_filename, 0, NULL); 2590 if (pde) 2591 pde->proc_fops = &proc_ops; 2592} 2593 2594static void remove_proc_file(void) 2595{ 2596 remove_proc_entry(proc_filename, NULL); 2597} 2598 2599#else 2600 2601static inline void create_proc_file(void) {} 2602static inline void remove_proc_file(void) {} 2603 2604#endif 2605 2606/*-------------------------------------------------------------------------*/ 2607 2608/* Before this controller can enumerate, we need to pick an endpoint 2609 * configuration, or "fifo_mode" That involves allocating 2KB of packet 2610 * buffer space among the endpoints we'll be operating. 2611 * 2612 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when 2613 * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that 2614 * capability yet though. 2615 */ 2616static unsigned __init 2617omap_ep_setup(char *name, u8 addr, u8 type, 2618 unsigned buf, unsigned maxp, int dbuf) 2619{ 2620 struct omap_ep *ep; 2621 u16 epn_rxtx = 0; 2622 2623 /* OUT endpoints first, then IN */ 2624 ep = &udc->ep[addr & 0xf]; 2625 if (addr & USB_DIR_IN) 2626 ep += 16; 2627 2628 /* in case of ep init table bugs */ 2629 BUG_ON(ep->name[0]); 2630 2631 /* chip setup ... bit values are same for IN, OUT */ 2632 if (type == USB_ENDPOINT_XFER_ISOC) { 2633 switch (maxp) { 2634 case 8: epn_rxtx = 0 << 12; break; 2635 case 16: epn_rxtx = 1 << 12; break; 2636 case 32: epn_rxtx = 2 << 12; break; 2637 case 64: epn_rxtx = 3 << 12; break; 2638 case 128: epn_rxtx = 4 << 12; break; 2639 case 256: epn_rxtx = 5 << 12; break; 2640 case 512: epn_rxtx = 6 << 12; break; 2641 default: BUG(); 2642 } 2643 epn_rxtx |= UDC_EPN_RX_ISO; 2644 dbuf = 1; 2645 } else { 2646 /* double-buffering "not supported" on 15xx, 2647 * and ignored for PIO-IN on newer chips 2648 * (for more reliable behavior) 2649 */ 2650 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx()) 2651 dbuf = 0; 2652 2653 switch (maxp) { 2654 case 8: epn_rxtx = 0 << 12; break; 2655 case 16: epn_rxtx = 1 << 12; break; 2656 case 32: epn_rxtx = 2 << 12; break; 2657 case 64: epn_rxtx = 3 << 12; break; 2658 default: BUG(); 2659 } 2660 if (dbuf && addr) 2661 epn_rxtx |= UDC_EPN_RX_DB; 2662 init_timer(&ep->timer); 2663 ep->timer.function = pio_out_timer; 2664 ep->timer.data = (unsigned long) ep; 2665 } 2666 if (addr) 2667 epn_rxtx |= UDC_EPN_RX_VALID; 2668 BUG_ON(buf & 0x07); 2669 epn_rxtx |= buf >> 3; 2670 2671 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n", 2672 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); 2673 2674 if (addr & USB_DIR_IN) 2675 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx; 2676 else 2677 UDC_EP_RX_REG(addr) = epn_rxtx; 2678 2679 /* next endpoint's buffer starts after this one's */ 2680 buf += maxp; 2681 if (dbuf) 2682 buf += maxp; 2683 BUG_ON(buf > 2048); 2684 2685 /* set up driver data structures */ 2686 BUG_ON(strlen(name) >= sizeof ep->name); 2687 strlcpy(ep->name, name, sizeof ep->name); 2688 INIT_LIST_HEAD(&ep->queue); 2689 INIT_LIST_HEAD(&ep->iso); 2690 ep->bEndpointAddress = addr; 2691 ep->bmAttributes = type; 2692 ep->double_buf = dbuf; 2693 ep->udc = udc; 2694 2695 ep->ep.name = ep->name; 2696 ep->ep.ops = &omap_ep_ops; 2697 ep->ep.maxpacket = ep->maxpacket = maxp; 2698 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list); 2699 2700 return buf; 2701} 2702 2703static void omap_udc_release(struct device *dev) 2704{ 2705 complete(udc->done); 2706 kfree (udc); 2707 udc = NULL; 2708} 2709 2710static int __init 2711omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) 2712{ 2713 unsigned tmp, buf; 2714 2715 /* abolish any previous hardware state */ 2716 UDC_SYSCON1_REG = 0; 2717 UDC_IRQ_EN_REG = 0; 2718 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; 2719 UDC_DMA_IRQ_EN_REG = 0; 2720 UDC_RXDMA_CFG_REG = 0; 2721 UDC_TXDMA_CFG_REG = 0; 2722 2723 /* UDC_PULLUP_EN gates the chip clock */ 2724 // OTG_SYSCON_1_REG |= DEV_IDLE_EN; 2725 2726 udc = kzalloc(sizeof(*udc), GFP_KERNEL); 2727 if (!udc) 2728 return -ENOMEM; 2729 2730 spin_lock_init (&udc->lock); 2731 2732 udc->gadget.ops = &omap_gadget_ops; 2733 udc->gadget.ep0 = &udc->ep[0].ep; 2734 INIT_LIST_HEAD(&udc->gadget.ep_list); 2735 INIT_LIST_HEAD(&udc->iso); 2736 udc->gadget.speed = USB_SPEED_UNKNOWN; 2737 udc->gadget.name = driver_name; 2738 2739 device_initialize(&udc->gadget.dev); 2740 strcpy (udc->gadget.dev.bus_id, "gadget"); 2741 udc->gadget.dev.release = omap_udc_release; 2742 udc->gadget.dev.parent = &odev->dev; 2743 if (use_dma) 2744 udc->gadget.dev.dma_mask = odev->dev.dma_mask; 2745 2746 udc->transceiver = xceiv; 2747 2748 /* ep0 is special; put it right after the SETUP buffer */ 2749 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL, 2750 8 /* after SETUP */, 64 /* maxpacket */, 0); 2751 list_del_init(&udc->ep[0].ep.ep_list); 2752 2753 /* initially disable all non-ep0 endpoints */ 2754 for (tmp = 1; tmp < 15; tmp++) { 2755 UDC_EP_RX_REG(tmp) = 0; 2756 UDC_EP_TX_REG(tmp) = 0; 2757 } 2758 2759#define OMAP_BULK_EP(name,addr) \ 2760 buf = omap_ep_setup(name "-bulk", addr, \ 2761 USB_ENDPOINT_XFER_BULK, buf, 64, 1); 2762#define OMAP_INT_EP(name,addr, maxp) \ 2763 buf = omap_ep_setup(name "-int", addr, \ 2764 USB_ENDPOINT_XFER_INT, buf, maxp, 0); 2765#define OMAP_ISO_EP(name,addr, maxp) \ 2766 buf = omap_ep_setup(name "-iso", addr, \ 2767 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1); 2768 2769 switch (fifo_mode) { 2770 case 0: 2771 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2772 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2773 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); 2774 break; 2775 case 1: 2776 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2777 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2778 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); 2779 2780 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3); 2781 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4); 2782 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16); 2783 2784 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5); 2785 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); 2786 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16); 2787 2788 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); 2789 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6); 2790 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16); 2791 2792 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7); 2793 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); 2794 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16); 2795 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16); 2796 2797 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8); 2798 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8); 2799 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16); 2800 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16); 2801 2802 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15); 2803 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15); 2804 2805 break; 2806 2807#ifdef USE_ISO 2808 case 2: /* mixed iso/bulk */ 2809 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256); 2810 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256); 2811 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128); 2812 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128); 2813 2814 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16); 2815 2816 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); 2817 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); 2818 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16); 2819 break; 2820 case 3: /* mixed bulk/iso */ 2821 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); 2822 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); 2823 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); 2824 2825 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4); 2826 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); 2827 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16); 2828 2829 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256); 2830 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256); 2831 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); 2832 break; 2833#endif 2834 2835 /* add more modes as needed */ 2836 2837 default: 2838 ERR("unsupported fifo_mode #%d\n", fifo_mode); 2839 return -ENODEV; 2840 } 2841 UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR; 2842 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); 2843 return 0; 2844} 2845 2846static int __init omap_udc_probe(struct platform_device *pdev) 2847{ 2848 int status = -ENODEV; 2849 int hmc; 2850 struct otg_transceiver *xceiv = NULL; 2851 const char *type = NULL; 2852 struct omap_usb_config *config = pdev->dev.platform_data; 2853 struct clk *dc_clk; 2854 struct clk *hhc_clk; 2855 2856 /* NOTE: "knows" the order of the resources! */ 2857 if (!request_mem_region(pdev->resource[0].start, 2858 pdev->resource[0].end - pdev->resource[0].start + 1, 2859 driver_name)) { 2860 DBG("request_mem_region failed\n"); 2861 return -EBUSY; 2862 } 2863 2864 if (cpu_is_omap16xx()) { 2865 dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); 2866 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck"); 2867 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); 2868 /* can't use omap_udc_enable_clock yet */ 2869 clk_enable(dc_clk); 2870 clk_enable(hhc_clk); 2871 udelay(100); 2872 } 2873 2874 if (cpu_is_omap24xx()) { 2875 dc_clk = clk_get(&pdev->dev, "usb_fck"); 2876 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick"); 2877 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); 2878 /* can't use omap_udc_enable_clock yet */ 2879 clk_enable(dc_clk); 2880 clk_enable(hhc_clk); 2881 udelay(100); 2882 } 2883 2884 INFO("OMAP UDC rev %d.%d%s\n", 2885 UDC_REV_REG >> 4, UDC_REV_REG & 0xf, 2886 config->otg ? ", Mini-AB" : ""); 2887 2888 /* use the mode given to us by board init code */ 2889 if (cpu_is_omap15xx()) { 2890 hmc = HMC_1510; 2891 type = "(unknown)"; 2892 2893 if (machine_without_vbus_sense()) { 2894 u32 tmp = FUNC_MUX_CTRL_0_REG; 2895 2896 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; 2897 tmp |= VBUS_MODE_1510; 2898 tmp &= ~VBUS_CTRL_1510; 2899 FUNC_MUX_CTRL_0_REG = tmp; 2900 } 2901 } else { 2902 /* The transceiver may package some GPIO logic or handle 2903 * loopback and/or transceiverless setup; if we find one, 2904 * use it. Except for OTG, we don't _need_ to talk to one; 2905 * but not having one probably means no VBUS detection. 2906 */ 2907 xceiv = otg_get_transceiver(); 2908 if (xceiv) 2909 type = xceiv->label; 2910 else if (config->otg) { 2911 DBG("OTG requires external transceiver!\n"); 2912 goto cleanup0; 2913 } 2914 2915 hmc = HMC_1610; 2916 2917 if (cpu_is_omap24xx()) { 2918 /* this could be transceiverless in one of the 2919 * "we don't need to know" modes. 2920 */ 2921 type = "external"; 2922 goto known; 2923 } 2924 2925 switch (hmc) { 2926 case 0: /* POWERUP DEFAULT == 0 */ 2927 case 4: 2928 case 12: 2929 case 20: 2930 if (!cpu_is_omap1710()) { 2931 type = "integrated"; 2932 break; 2933 } 2934 /* FALL THROUGH */ 2935 case 3: 2936 case 11: 2937 case 16: 2938 case 19: 2939 case 25: 2940 if (!xceiv) { 2941 DBG("external transceiver not registered!\n"); 2942 type = "unknown"; 2943 } 2944 break; 2945 case 21: /* internal loopback */ 2946 type = "loopback"; 2947 break; 2948 case 14: /* transceiverless */ 2949 if (cpu_is_omap1710()) 2950 goto bad_on_1710; 2951 /* FALL THROUGH */ 2952 case 13: 2953 case 15: 2954 type = "no"; 2955 break; 2956 2957 default: 2958bad_on_1710: 2959 ERR("unrecognized UDC HMC mode %d\n", hmc); 2960 goto cleanup0; 2961 } 2962 } 2963known: 2964 INFO("hmc mode %d, %s transceiver\n", hmc, type); 2965 2966 /* a "gadget" abstracts/virtualizes the controller */ 2967 status = omap_udc_setup(pdev, xceiv); 2968 if (status) { 2969 goto cleanup0; 2970 } 2971 xceiv = NULL; 2972 // "udc" is now valid 2973 pullup_disable(udc); 2974#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 2975 udc->gadget.is_otg = (config->otg != 0); 2976#endif 2977 2978 /* starting with omap1710 es2.0, clear toggle is a separate bit */ 2979 if (UDC_REV_REG >= 0x61) 2980 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; 2981 else 2982 udc->clr_halt = UDC_RESET_EP; 2983 2984 /* USB general purpose IRQ: ep0, state changes, dma, etc */ 2985 status = request_irq(pdev->resource[1].start, omap_udc_irq, 2986 IRQF_SAMPLE_RANDOM, driver_name, udc); 2987 if (status != 0) { 2988 ERR("can't get irq %d, err %d\n", 2989 (int) pdev->resource[1].start, status); 2990 goto cleanup1; 2991 } 2992 2993 /* USB "non-iso" IRQ (PIO for all but ep0) */ 2994 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq, 2995 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc); 2996 if (status != 0) { 2997 ERR("can't get irq %d, err %d\n", 2998 (int) pdev->resource[2].start, status); 2999 goto cleanup2; 3000 } 3001#ifdef USE_ISO 3002 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq, 3003 IRQF_DISABLED, "omap_udc iso", udc); 3004 if (status != 0) { 3005 ERR("can't get irq %d, err %d\n", 3006 (int) pdev->resource[3].start, status); 3007 goto cleanup3; 3008 } 3009#endif 3010 if (cpu_is_omap16xx()) { 3011 udc->dc_clk = dc_clk; 3012 udc->hhc_clk = hhc_clk; 3013 clk_disable(hhc_clk); 3014 clk_disable(dc_clk); 3015 } 3016 3017 if (cpu_is_omap24xx()) { 3018 udc->dc_clk = dc_clk; 3019 udc->hhc_clk = hhc_clk; 3020 } 3021 3022 create_proc_file(); 3023 status = device_add(&udc->gadget.dev); 3024 if (!status) 3025 return status; 3026 /* If fail, fall through */ 3027#ifdef USE_ISO 3028cleanup3: 3029 free_irq(pdev->resource[2].start, udc); 3030#endif 3031 3032cleanup2: 3033 free_irq(pdev->resource[1].start, udc); 3034 3035cleanup1: 3036 kfree (udc); 3037 udc = NULL; 3038 3039cleanup0: 3040 if (xceiv) 3041 put_device(xceiv->dev); 3042 3043 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 3044 clk_disable(hhc_clk); 3045 clk_disable(dc_clk); 3046 clk_put(hhc_clk); 3047 clk_put(dc_clk); 3048 } 3049 3050 release_mem_region(pdev->resource[0].start, 3051 pdev->resource[0].end - pdev->resource[0].start + 1); 3052 3053 return status; 3054} 3055 3056static int __exit omap_udc_remove(struct platform_device *pdev) 3057{ 3058 DECLARE_COMPLETION_ONSTACK(done); 3059 3060 if (!udc) 3061 return -ENODEV; 3062 if (udc->driver) 3063 return -EBUSY; 3064 3065 udc->done = &done; 3066 3067 pullup_disable(udc); 3068 if (udc->transceiver) { 3069 put_device(udc->transceiver->dev); 3070 udc->transceiver = NULL; 3071 } 3072 UDC_SYSCON1_REG = 0; 3073 3074 remove_proc_file(); 3075 3076#ifdef USE_ISO 3077 free_irq(pdev->resource[3].start, udc); 3078#endif 3079 free_irq(pdev->resource[2].start, udc); 3080 free_irq(pdev->resource[1].start, udc); 3081 3082 if (udc->dc_clk) { 3083 if (udc->clk_requested) 3084 omap_udc_enable_clock(0); 3085 clk_put(udc->hhc_clk); 3086 clk_put(udc->dc_clk); 3087 } 3088 3089 release_mem_region(pdev->resource[0].start, 3090 pdev->resource[0].end - pdev->resource[0].start + 1); 3091 3092 device_unregister(&udc->gadget.dev); 3093 wait_for_completion(&done); 3094 3095 return 0; 3096} 3097 3098/* suspend/resume/wakeup from sysfs (echo > power/state) or when the 3099 * system is forced into deep sleep 3100 * 3101 * REVISIT we should probably reject suspend requests when there's a host 3102 * session active, rather than disconnecting, at least on boards that can 3103 * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to 3104 * make host resumes and VBUS detection trigger OMAP wakeup events; that 3105 * may involve talking to an external transceiver (e.g. isp1301). 3106 */ 3107 3108static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) 3109{ 3110 u32 devstat; 3111 3112 devstat = UDC_DEVSTAT_REG; 3113 3114 /* we're requesting 48 MHz clock if the pullup is enabled 3115 * (== we're attached to the host) and we're not suspended, 3116 * which would prevent entry to deep sleep... 3117 */ 3118 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) { 3119 WARN("session active; suspend requires disconnect\n"); 3120 omap_pullup(&udc->gadget, 0); 3121 } 3122 3123 udc->gadget.dev.power.power_state = PMSG_SUSPEND; 3124 udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND; 3125 return 0; 3126} 3127 3128static int omap_udc_resume(struct platform_device *dev) 3129{ 3130 DBG("resume + wakeup/SRP\n"); 3131 omap_pullup(&udc->gadget, 1); 3132 3133 /* maybe the host would enumerate us if we nudged it */ 3134 msleep(100); 3135 return omap_wakeup(&udc->gadget); 3136} 3137 3138/*-------------------------------------------------------------------------*/ 3139 3140static struct platform_driver udc_driver = { 3141 .probe = omap_udc_probe, 3142 .remove = __exit_p(omap_udc_remove), 3143 .suspend = omap_udc_suspend, 3144 .resume = omap_udc_resume, 3145 .driver = { 3146 .owner = THIS_MODULE, 3147 .name = (char *) driver_name, 3148 }, 3149}; 3150 3151static int __init udc_init(void) 3152{ 3153 INFO("%s, version: " DRIVER_VERSION 3154#ifdef USE_ISO 3155 " (iso)" 3156#endif 3157 "%s\n", driver_desc, 3158 use_dma ? " (dma)" : ""); 3159 return platform_driver_register(&udc_driver); 3160} 3161module_init(udc_init); 3162 3163static void __exit udc_exit(void) 3164{ 3165 platform_driver_unregister(&udc_driver); 3166} 3167module_exit(udc_exit); 3168 3169MODULE_DESCRIPTION(DRIVER_DESC); 3170MODULE_LICENSE("GPL"); 3171