1/* 2 * Trantor T128/T128F/T228 defines 3 * Note : architecturally, the T100 and T128 are different and won't work 4 * 5 * Copyright 1993, Drew Eckhardt 6 * Visionary Computing 7 * (Unix and Linux consulting and custom programming) 8 * drew@colorado.edu 9 * +1 (303) 440-4894 10 * 11 * DISTRIBUTION RELEASE 3. 12 * 13 * For more information, please consult 14 * 15 * Trantor Systems, Ltd. 16 * T128/T128F/T228 SCSI Host Adapter 17 * Hardware Specifications 18 * 19 * Trantor Systems, Ltd. 20 * 5415 Randall Place 21 * Fremont, CA 94538 22 * 1+ (415) 770-1400, FAX 1+ (415) 770-9910 23 * 24 * and 25 * 26 * NCR 5380 Family 27 * SCSI Protocol Controller 28 * Databook 29 * 30 * NCR Microelectronics 31 * 1635 Aeroplaza Drive 32 * Colorado Springs, CO 80916 33 * 1+ (719) 578-3400 34 * 1+ (800) 334-5454 35 */ 36 37/* 38 * $Log: t128.h,v $ 39 * Revision 1.1.1.1 2007/08/03 18:52:57 rnuti 40 * Importing Linux MIPS Kernel 2.6.22 41 * 42 */ 43 44#ifndef T128_H 45#define T128_H 46 47#define T128_PUBLIC_RELEASE 3 48 49#define TDEBUG 0 50#define TDEBUG_INIT 0x1 51#define TDEBUG_TRANSFER 0x2 52 53/* 54 * The trantor boards are memory mapped. They use an NCR5380 or 55 * equivalent (my sample board had part second sourced from ZILOG). 56 * NCR's recommended "Pseudo-DMA" architecture is used, where 57 * a PAL drives the DMA signals on the 5380 allowing fast, blind 58 * transfers with proper handshaking. 59 */ 60 61/* 62 * Note : a boot switch is provided for the purpose of informing the 63 * firmware to boot or not boot from attached SCSI devices. So, I imagine 64 * there are fewer people who've yanked the ROM like they do on the Seagate 65 * to make bootup faster, and I'll probably use this for autodetection. 66 */ 67#define T_ROM_OFFSET 0 68 69/* 70 * Note : my sample board *WAS NOT* populated with the SRAM, so this 71 * can't be used for autodetection without a ROM present. 72 */ 73#define T_RAM_OFFSET 0x1800 74 75/* 76 * All of the registers are allocated 32 bytes of address space, except 77 * for the data register (read/write to/from the 5380 in pseudo-DMA mode) 78 */ 79#define T_CONTROL_REG_OFFSET 0x1c00 /* rw */ 80#define T_CR_INT 0x10 /* Enable interrupts */ 81#define T_CR_CT 0x02 /* Reset watchdog timer */ 82 83#define T_STATUS_REG_OFFSET 0x1c20 /* ro */ 84#define T_ST_BOOT 0x80 /* Boot switch */ 85#define T_ST_S3 0x40 /* User settable switches, */ 86#define T_ST_S2 0x20 /* read 0 when switch is on, 1 off */ 87#define T_ST_S1 0x10 88#define T_ST_PS2 0x08 /* Set for Microchannel 228 */ 89#define T_ST_RDY 0x04 /* 5380 DRQ */ 90#define T_ST_TIM 0x02 /* indicates 40us watchdog timer fired */ 91#define T_ST_ZERO 0x01 /* Always zero */ 92 93#define T_5380_OFFSET 0x1d00 /* 8 registers here, see NCR5380.h */ 94 95#define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */ 96 97#ifndef ASM 98static int t128_abort(struct scsi_cmnd *); 99static int t128_biosparam(struct scsi_device *, struct block_device *, 100 sector_t, int*); 101static int t128_detect(struct scsi_host_template *); 102static int t128_queue_command(struct scsi_cmnd *, 103 void (*done)(struct scsi_cmnd *)); 104static int t128_bus_reset(struct scsi_cmnd *); 105 106#ifndef CMD_PER_LUN 107#define CMD_PER_LUN 2 108#endif 109 110#ifndef CAN_QUEUE 111#define CAN_QUEUE 32 112#endif 113 114#ifndef HOSTS_C 115 116#define NCR5380_implementation_fields \ 117 void __iomem *base 118 119#define NCR5380_local_declare() \ 120 void __iomem *base 121 122#define NCR5380_setup(instance) \ 123 base = ((struct NCR5380_hostdata *)(instance->hostdata))->base 124 125#define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20)) 126 127#if !(TDEBUG & TDEBUG_TRANSFER) 128#define NCR5380_read(reg) readb(T128_address(reg)) 129#define NCR5380_write(reg, value) writeb((value),(T128_address(reg))) 130#else 131#define NCR5380_read(reg) \ 132 (((unsigned char) printk("scsi%d : read register %d at address %08x\n"\ 133 , instance->hostno, (reg), T128_address(reg))), readb(T128_address(reg))) 134 135#define NCR5380_write(reg, value) { \ 136 printk("scsi%d : write %02x to register %d at address %08x\n", \ 137 instance->hostno, (value), (reg), T128_address(reg)); \ 138 writeb((value), (T128_address(reg))); \ 139} 140#endif 141 142#define NCR5380_intr t128_intr 143#define do_NCR5380_intr do_t128_intr 144#define NCR5380_queue_command t128_queue_command 145#define NCR5380_abort t128_abort 146#define NCR5380_bus_reset t128_bus_reset 147#define NCR5380_proc_info t128_proc_info 148 149/* 15 14 12 10 7 5 3 150 1101 0100 1010 1000 */ 151 152#define T128_IRQS 0xc4a8 153 154#endif /* else def HOSTS_C */ 155#endif /* ndef ASM */ 156#endif /* T128_H */ 157